Patents Issued in May 6, 2004
  • Publication number: 20040088575
    Abstract: An embodiment of a secure remote network access method comprises monitoring a state of a first storage medium using a shared access point operable to enable a process to read data on the first storage medium. The method also comprises, when a threshold has been reached, selecting at least one file resident on the first storage medium, and transferring the at least one file to a second storage medium.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Inventors: Allen J. Piepho, Gregory J. Lipinski
  • Publication number: 20040088576
    Abstract: Preventing replay attacks with no user involvement. A method according to one embodiment of the invention includes generating and providing a client with a ticket. When making a request to access the resource, the client digitally signs and includes the ticket. The request is received and the ticket and signature are verified before access to the resource is granted.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Ward Scott Foster, Robert John Madril, Shell Sterling Simpson
  • Publication number: 20040088577
    Abstract: The invention relates to an apparatus and method for evaluating security threats from information available on the Internet or an Intranet. The method comprises gathering information from the Internet or an Intranet using at least one analyst defined parameter. The method then proceeds to generate a visual display of the gathered information. After generating the visual display of the information, the method provides a plurality of software tools for analyzing the visual display and the gathered information to identify a potential security threat. The method then generates an automated report based on the gathered information, the visual display, and the security threat analysis.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: Battelle Memorial Institute, a corporation of Ohio
    Inventor: Kenneth J. Render
  • Publication number: 20040088578
    Abstract: A system and method for run-as credentials delegation using identity assertion is presented. A server receives a request from a client that includes the client's user identifier and password. The server authenticates the client and stores the client's user identifier without the corresponding password in a client credential storage area. The server determines if a run-as command is specified to communicate with a downstream server. If a run-as command is specified, the server retrieves a corresponding run-as identity which identifies whether a client credential type, a server credential type, or a specific identifier credential type should be used in the run-as command. The server retrieves an identified credential corresponding to the identified credential type, and sends the identified credential in an identity assertion token to a downstream server.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: International Business Machines Corporation
    Inventors: Ching-Yun Chao, Hyen Vui Chung, Ajay Reddy, Vishwanath Venkataramappa
  • Publication number: 20040088579
    Abstract: A request including a call for the information in a bean and a purpose for the call is received. Upon receipt, the purpose is compared to a privacy control policy that is packaged with the bean. If the purpose complies with the privacy control policy, the requested access and/or use of the information is permitted.
    Type: Application
    Filed: November 5, 2002
    Publication date: May 6, 2004
    Applicant: International Business Machines Corporation
    Inventors: Calvin S. Powers, Martin Presler-Marshall
  • Publication number: 20040088580
    Abstract: Moving replicas in a cryptographically secure manner such that the target location and timing of the movements are completely hidden from any user, or is kept as a secret by a limited number of users who have been given advanced notice of the new location and relocation time for a replica. A catalog of replica locations that describe the current location of the replicas is stored in encrypted form so as to prevent individuals from determining the exact location of the replicas. Since the location of the replicas is hidden at any given moment, attackers may not use the location of the replicas in order to attack all of the replicas at the same time. Accordingly, recovery mechanisms may have an opportunity to recover from any given attack by once again creating replicas from those replicas that had not been attacked.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Inventors: Luis Felipe Cabrera, Marvin M. Theimer, Christopher G. Kaler
  • Publication number: 20040088581
    Abstract: A method of identifying a software vulnerability in computer systems in a computer network includes a multiple level scanning process controlled from a management system connected to the network. The management system runs a root scanner which applies an interrogation program to remote systems having network addresses in a predefined address range. When a software vulnerability is detected, the interrogation program causes the respective remote system to scan topologically local systems, the remote system itself applying a second interrogation program to the local systems to detect and mitigate the vulnerability using an associated mitigation payload. Whilst that local scanning process is in progress, the root scanner can be applied to remote systems in other predefined address ranges.
    Type: Application
    Filed: January 16, 2003
    Publication date: May 6, 2004
    Inventors: John Melvin Brawn, Andrew Patrick Norman, Chris Ralph Dalton, Jonathan Griffin
  • Publication number: 20040088582
    Abstract: The invention relates to a data network-based system (1′) which is adapted for data communication and which includes a number of users (2) belong-ing to a first category and a number of users (3) belonging to a second category. A first user (2) belonging to the first category is adapted to use a chosen security protocol (20, 21) to establish a secure session with a second user (3) belonging to said second category, and subsequent to positive authentication allow data com-munication to pass through a firewall (6). A means (8) pre-coupled to the firewall (6) is adapted to establish the identity of the first user through the medium of a handshake procedure (21) belonging to the security protocol (20), and to allow messages to be forwarded from the first user to the second user belonging to said secure session in response to accepted authentication.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 6, 2004
    Inventors: Torbjorn Hovmark, Lars Resenius
  • Publication number: 20040088583
    Abstract: An alert transmission apparatus for a policy-based intrusion detection and response has a central policy server (CPS) and an intrusion detection and response system (IDRS). In the CPS, a policy management tool generates security policy information and then stores the generated security policy information in a policy repository. A COPS-IDR server sends the information to the IDRS and an IDMEF-XML-type alert transmission message to a high-level module. An IDMEF-XML message parsing and translation module stores a parsed and translated IDMEF-XML-type alert transmission message in an alert DB or provides the message to an alert viewer. In the IDRS, a COPS-IDR client generates the IDMEF-XML-type alert transmission message and provides the message to the CPS. An intrusion detection module detects an intrusion. An intrusion response module responds to the intrusion. An IDMEF-XML message building module generates an IDMEF-XML alert message and provides the message to the COPS-IDR client.
    Type: Application
    Filed: May 30, 2003
    Publication date: May 6, 2004
    Inventors: Seung Yong Yoon, Gae Il Ahn, Ki Young Kim, Jong Soo Jang
  • Publication number: 20040088584
    Abstract: There is provided a system and method of selectively directing collected security data that may be displayed concurrently at a first security station and at a supervisor station, and providing a communication link between such first security station and such supervisor station so that a supervisor may assist a security operator in the evaluation of the collected security data and in making a decision about such collected data.
    Type: Application
    Filed: October 21, 2003
    Publication date: May 6, 2004
    Inventors: Yair Shachar, Isac Winter, Andi Forsthofer
  • Publication number: 20040088585
    Abstract: Multiple different credentials and/or signatures based on different credentials may be included in a header portion of a single electronic message. Different recipients of intermediary computing systems may use the different credentials/signatures to identify the signer. The electronic message may include an encoding algorithm and a type identification of a credential included in the electronic message, allowing the recipient to decode and process the credential as appropriate given the type of credential. Also, the electronic message may include a pointer that references a credential associated with a signature included in the electronic message. That referenced credential may be accessed from the same electronic message, or from some other location. The recipient may then compare the references credential from the credentials used to generate the signature. If a match occurs, the integrity of the electronic message has more likely been preserved.
    Type: Application
    Filed: October 23, 2003
    Publication date: May 6, 2004
    Inventors: Christopher J. Kaler, John P. Shewchuk, Giovanni M. Della-Libera
  • Publication number: 20040088586
    Abstract: The present invention provides a firewall that achieves maximum network security and maximum user convenience. The firewall employs “envoys” that exhibit the security robustness of prior-art proxies and the transparency and ease-of-use of prior-art packet filters, combining the best of both worlds. No traffic can pass through the firewall unless the firewall has established an envoy for that traffic. Both connection-oriented (e.g., TCP) and connectionless (e.g., UDP-based) services may be handled using envoys. Establishment of an envoy may be subjected to a myriad of tests to “qualify” the user, the requested communication, or both. Therefore, a high level of security may be achieved. The usual added burden of prior-art proxy systems is avoided in such a way as to achieve fall transparency-the user can use standard applications and need not even know of the existence of the firewall. To achieve full transparency, the firewall is configured as two or more sets of virtual hosts.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 6, 2004
    Inventors: Ralph E. Wesinger, Christopher D. Coley
  • Publication number: 20040088587
    Abstract: An authentication framework is provided which enables dynamic user authentication that combines multiple authentication objects using a shared context and that permits customizable interaction design to suit varying user preferences and transaction/application requirements. Such a framework provides a high degree of flexibility, accuracy, convenience and robustness. In one illustrative aspect of the invention, an automated technique for user authentication comprises the following steps/operations. First, user input is obtained. At least a portion of the user input is associated with two or more verification objects. Then, the user is verified based on the two or more verification objects in accordance with at least one verification policy operating on a context shared across the two or more verification objects.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: International Business Machines Corporation
    Inventors: Ganesh N. Ramaswamy, Ran Zilca, Oleg Alecksandrovich
  • Publication number: 20040088588
    Abstract: A method of rapid access to resources on a computing system is provided that differentiates between applications, data and devices that require password protection and those that do not, enabling those applications, data and devices that do not require protection to be accessed without entry of a password. In one embodiment, application programs include an option that enables a user to specify whether or not the application, or specific operations within the application, can be initiated without first entering a password. In a second embodiment, the protection is provided at an operating system level by protecting designated resources. Another embodiment employs two passwords—the second of which is required to access rapid access applications or operations and may or may not timeout. In this manner, an authorized user can gain access to particular applications, data or devices in less time than otherwise necessary with a standard password protection scheme.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: International Business Machines Corporation
    Inventors: Faisal M. Awada, Joe Nathan Brown, Herman Rodriguez, Newton James Smith
  • Publication number: 20040088589
    Abstract: A mechanism is provided for a personal computer to preserve user and system state data in the event of an AC power failure when the computer is in a standby state. When the AC power failure occurs, a switchover circuit connects a rechargeable energy storage medium, such as a rechargeable battery, to the power supply of the computer for powering components of computer, and the computer is awaken. A critical battery alarm is then issued to trigger the operating system of the computer to perform a transition into a hibernation state, during which the state data of the computer are persistently stored. The energy storage medium is disconnected from the power supply after the computer system has entered hibernation.
    Type: Application
    Filed: March 6, 2003
    Publication date: May 6, 2004
    Applicant: Microsoft Corporation
    Inventors: William J. Westerinen, Jason M. Anderson, Allen Marshall, Tony D. Pierce
  • Publication number: 20040088590
    Abstract: The present invention relates to a system and method adapted to optimize power consumption in a communication system used in a Gigabit Ethernet environment. The method comprises determining at least one power mode of a host from a plurality of possible host power modes. The method further comprises selecting at least one network interface power management state from a plurality of possible network interface power management states based, at least in part, on the determined power mode.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 6, 2004
    Inventors: Johathan Lee, John Lenell, Gregory Youngblood
  • Publication number: 20040088591
    Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Hwang, Kun Wu
  • Publication number: 20040088592
    Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Davide Rizzo, Osvaldo Colavin
  • Publication number: 20040088593
    Abstract: A system for protecting against overheating of a CPU whose operation frequency is changed due to voltage variation of a driving power, includes a CPU temperature sensor to detect the temperature of the CPU, a reference temperature sensor to detect the temperature of a circuit block or multiple circuits heated due to the operation frequency of the CPU, a comparing part to output a signal indicating a higher temperature of the temperature of the CPU and the temperature of the circuit block or multiple circuits by comparing temperature values detected by the respective CPU and reference temperature sensors, and a CPU power supply to supply a stepwise decreasing driving power to decrease the operation frequency of the CPU in a stepwise fashion when the temperature value increases based on the signal indicating the higher temperature indicated by the comparing part.
    Type: Application
    Filed: June 13, 2003
    Publication date: May 6, 2004
    Applicant: SAMSUNG Electronics Co., Ltd.
    Inventor: Seong-Geun Park
  • Publication number: 20040088594
    Abstract: A receiver circuit is provided with a front amplifier to receive data from an I/O link driven by a remote clock signal; an interpolator to generate a local clock signal to track the remote clock signal encoded in the data; and a tracking mechanism to extract phase information about the remote clock signal from the data and to dynamically adjust the phase of the local clock signal that tracks the remote clock signal in accordance with extracted phase information for subsequent data processing functions, wherein the tracking mechanism is configured to predict the direction of a phase drift, and force the interpolator to move against the phase drift so as to reduce lock time.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Karthisha S. Canagasaby, Sanjay Dabral, Chamath Abhayagunawardhana, Ken Drottar, David S. Dunning
  • Publication number: 20040088595
    Abstract: A circuit system (100) and a method for synchronized transmission of audio data streams in a bus system, in particular based on the IEEE 1394 Standard, by which, among other features, the sample data frequency of the data source may be recovered in the data sink without a PLL circuit system, including the following:
    Type: Application
    Filed: December 23, 2003
    Publication date: May 6, 2004
    Inventor: Wolfgang Baierl
  • Publication number: 20040088596
    Abstract: An output of a first data register is coupled to an input of a second data register. The same periodic clock signal clocks both data registers. A controller monitors the clock signal, a first load signal and a read signal. The controller generates a guard band signal using the clock signal and the first load signal. The controller also generates a second guard band signal from the read signal and the clock signal. A second load signal, that is used to load the second data register, is created by performing a logical AND operation on the two guard band signals.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 6, 2004
    Applicant: ADC DSL Systems, Inc.
    Inventors: Dennis J. Vandenberg, Douglas G. Gilliland
  • Publication number: 20040088597
    Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Inventor: Chung-Hsiao R. Wu
  • Publication number: 20040088598
    Abstract: A technique includes receiving a first signal from a data signal line. The first signal includes an edge that is indicative of a transition between logical states. The first signal is sampled at different times to form a plurality of sampled signals. In response to the sampled signals, the technique includes selecting a subset of the times to sample data from the data signal line.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventor: Gordon R. McLeod
  • Publication number: 20040088599
    Abstract: In an interface control semiconductor integrated circuit including a plurality of protocol circuits for processing a protocol such as AV- or PC-oriented protocols engaged in an IEEE 1394 standard-compliant data transmission, power consumption is reduced. To achieve this, the interface control semiconductor integrated circuit including the protocol circuits is provided with a plurality of switches associated with the respective protocol circuits and each of the switches performs a switching between supply and shut-off of a clock. A clock is supplied to one of the protocol circuits which should be used whereas clock to unused protocol circuits are shut-off, by controlling each of the switches.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.
    Inventors: Takayuki Matsui, Ryougo Yanagisawa, Kiyotaka Iwamoto
  • Publication number: 20040088600
    Abstract: A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Applicant: International Business Machines Corporation
    Inventors: Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik
  • Publication number: 20040088601
    Abstract: Method, system and program product are provided for a self-diagnose and self-repair facility for an automated machine or system. The facility monitors at least one operational parameter of the automated system, and automatically detects an abnormal status of the at least one operational parameter when present. The abnormal status is automatically evaluated to isolate a possible fault in the automated system resulting in the abnormal status, and automated repair of the possible fault is undertaken. After the automated repair, the facility determines whether the abnormal status has been eliminated.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: General Electric Company
    Inventors: Rasik P. Shah, Michael E. Kelly
  • Publication number: 20040088602
    Abstract: A method of regression testing a software application in an execution environment is disclosed. The software application interacts with a data storage and is run a first time. While running the software application for the first time, interactions of the software application with the data storage are monitored. Also while running the software application for the first time, first output data written from the software application to the data storage are recorded, and input data received by the software application from the data storage are recorded. The software application is run a second time after the first time. While running the software application the second time, when the software application calls for data from the data storage, at least a portion of the recorded input data is provided to the software application, and, when the software application writes data to the data storage, second output data written by the software application are recorded.
    Type: Application
    Filed: November 5, 2002
    Publication date: May 6, 2004
    Inventors: Richard M. Cohen, William H. Vollers
  • Publication number: 20040088603
    Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.
    Type: Application
    Filed: October 21, 2003
    Publication date: May 6, 2004
    Inventors: David H. Asher, Brian Lilly, Joel Grodstein, Patrick M. Fitzgerald
  • Publication number: 20040088604
    Abstract: Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Applicant: International Business Machines Corporation
    Inventors: Patrick Maurice Bland, Jeffrey B. Williams, Brandon R. Wyatt, Kit H. Wong
  • Publication number: 20040088605
    Abstract: An embodiment of the invention comprises a method and system for testing a networking system's performance. The invention solves a problem related to upgrading system components associated with different steps of the testing process for networking systems. Systems embodying the invention comprise a processing apparatus and a testing apparatus, each of which contains a data bus. The two data buses are linked together through a bi-directional communication bridge that allows the testing apparatus and the processing apparatus to transparently communicate such that the bridged data buses behave as through they exist on a same local bus. The architecture provided by the invention allows for the upgrading of a processing apparatus for enhanced data processing performance without changing existing adequate testing devices.
    Type: Application
    Filed: November 5, 2002
    Publication date: May 6, 2004
    Inventors: Ed Nakamoto, Floyd Cash
  • Publication number: 20040088606
    Abstract: A measurement apparatus which is reconfigurable in accordance with at least one category and at least one metric, to apply at least one threshold to the at least one category and at least one metric and generate at least one event exception if the at least one threshold is violated. The measurement apparatus is capable of setting one or more threshold for categories of events.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Terry Robison, Thomas Vachuska
  • Publication number: 20040088607
    Abstract: A method and apparatus for error handling in networks have been described.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Inventors: Wolf-Dietrich Weber, Chien-Chun Chou, Jeffrey Allen Ebert, Stephen W. Hamilton, Michael J. Meyer
  • Publication number: 20040088608
    Abstract: The system and method described herein automatically detect various corruptions in a file system and notify a system administrator of the corruption. Detailed information on the file system is collected by a probe process. If the file system is corrupt or inaccessible, the system and method marks the file system as bad, notifies the system administrator and then ceases to attempt to collect information on that system again until it has been repaired.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Liem M. Nguyen, Thomas Vachuska, Fengliang Hu
  • Publication number: 20040088609
    Abstract: A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected timing error is output. The timing error correction comprises performing an early-late correlation on the signal that has the corrected timing error. The early-late correlation comprises the generation of at least one early and late sample pair, the generation of an error signal that is indicative of the difference between the early and late samples, and the generation of at least one control signal based on the error signal. A time offset correction algorithm is performed dependent on the control signal.
    Type: Application
    Filed: June 19, 2003
    Publication date: May 6, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Uwe Eckhardt, Jorg Borowski, Tilo Ferchland
  • Publication number: 20040088610
    Abstract: Multipliers multiply corresponding input signals X1(n)˜Xm(n) by adaptive weights W1(n)˜Wm(n). An adder adds the output of the multipliers. The error function generating unit computes an error function e(n) indicating the difference between a sum Y(n) and a reference signal r(n). The adaptive weight update unit 4 computes the next adaptive weights W1(n+1)˜Wm(n+1) based on the error function e(n). The error function generating unit 3 includes a correction factor generation unit for generating correction factors &agr;(n) and &bgr;(n) based on the adaptive weights W1(n)˜Wm(n), an arithmetic unit for multiplying the sum Y(n) by the correction factor &bgr;(n), an arithmetic unit for multiplying the reference signal r(n) by the correction factor &agr;(n), and a subtracter 14 for computing the difference between output of the arithmetic units.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 6, 2004
    Inventor: Shuji Kobayakawa
  • Publication number: 20040088611
    Abstract: A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to produce an initial symbol erasure margin and then modifying the initial symbol erasure threshold using the initial symbol erasure margin to produce a modified symbol erasure threshold. By then periodically modifying the modified symbol erasure threshold adaptive via updating the symbol erasure threshold and/or symbol erasure margin based on various error quantities, the technique can compensate for time-variant considerations, such as drifting noise levels.
    Type: Application
    Filed: June 5, 2003
    Publication date: May 6, 2004
    Applicant: Broadcom Corporation
    Inventors: Miguel Peeters, Geert Arnout Albert Goris
  • Publication number: 20040088612
    Abstract: There are provided a redundancy circuit of a semiconductor memory device and a fail repair method, which are capable of repairing both a fail main cell and a fail redundancy cell when the redundancy cell substituted for the fail main cell is defective.
    Type: Application
    Filed: December 30, 2002
    Publication date: May 6, 2004
    Inventor: Jin-Yong Seong
  • Publication number: 20040088613
    Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.
    Type: Application
    Filed: January 15, 2003
    Publication date: May 6, 2004
    Inventors: Helmut Fischer, Ullrich Menczigar, Johann Pfeiffer
  • Publication number: 20040088614
    Abstract: A defect management system allows the usage of memory devices with a plurality of defective memory cells to be used for data storage. The system is especially suitable for the storage of streaming media data. The defect management system provides significant manufacturing costs benefits to products that store significant quantities of data in solid state memory, such as MP3 players or MPEG-4 video players. A non-volatile memory stores a map of defective areas within the memory devices that is generated using in Built In Self Test (BIST) procedure. The system employed are low overhead and can be realise in software code or a hardware implementation. The technique can be applied to a very wide range memory technologies include DRAM, Flash, FeRAM and MRAM.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Inventor: Ting-Chin Wu
  • Publication number: 20040088615
    Abstract: An approach for power supply noise modeling for test pattern development. For one aspect, conditions that may result in power supply noise-related failures are identified and the resulting faults are ranked.
    Type: Application
    Filed: June 26, 2002
    Publication date: May 6, 2004
    Inventor: Sandip Kundu
  • Publication number: 20040088616
    Abstract: The present invention includes a multi-mode SCSI backplane and a detection logic that is used in conjunction with the backplane. In this invention, the SCSI backplane can be configured in different modes, included simplex mode and duplex mode. The detection logic can also detect when an illegal configuration is connected to the SCSI backplane and indicate the presence of the illegal configuration by triggering a light emitting diode (LED) or some other indicating mechanism. The detection logic is implemented with a handful of cost-effective field effect transistors (FETs), resistors and LEDs and no additional IC logic gates or Programmable Array Logic (PAL) is necessary.
    Type: Application
    Filed: July 11, 2002
    Publication date: May 6, 2004
    Inventor: Vinh T. Vuong
  • Publication number: 20040088617
    Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.
    Type: Application
    Filed: October 10, 2003
    Publication date: May 6, 2004
    Applicant: Micron Technology, Inc.
    Inventor: Timothy B. Cowles
  • Publication number: 20040088618
    Abstract: A scan chain comprising a series of flip-flops and two clock signals, where each clock signal is coupled to alternating flip-flops in the series. The second clock signal is typically 180 degrees out of phase with the first clock signal. The two clock signals may be generated from a base clock signal that is coupled to two clocking devices. The first clock signal is output from one clocking device and the second clock signal is output from the other. One clocking device typically passes the base clock signal without delay and the second typically delays it. The clocking devices may be MUXes that can be switched to place the clock signals in or out of phase. The scan chain can be incorporated within an integrated circuit wherein the clock signals are out of phase during testing of the integrated circuit and are in phase after testing of the integrated circuit is complete.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Inventor: Joel Lurkins
  • Publication number: 20040088619
    Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.
    Type: Application
    Filed: October 7, 2003
    Publication date: May 6, 2004
    Applicant: Media Tek Inc.
    Inventors: Tse-Hsiang Hsu, Ding-Jen Liu, Jong-Woei Chen, Chih-Cheng Chen
  • Publication number: 20040088620
    Abstract: An MTIE test signal generating apparatus generates a predetermined MTIE test signal. An MTIE measuring unit includes a low-pass measuring filter having a predetermined high-cut characteristic. A cycle-amplitude setting portion sets a cycle corresponding to an observation time of each of desired plural specific points for a predetermined MTIE characteristic and an amplitude corresponding to a difference in the MTIE value between adjacent specific points. Plural signal generating portions generate plural signals each having the cycle and the amplitude having repetitive waveforms and then outputting to each of the desired plural specific points. A holding time setting portion sets a holding time for holding the upper and lower limit values of the repetitive waveforms over the predetermined time so that a signal cycle having at least the shortest cycle of the plural signals is longer than a predetermined time corresponding to the predetermined high-cut characteristic of the low-pass measuring filter.
    Type: Application
    Filed: October 7, 2003
    Publication date: May 6, 2004
    Applicant: Anritsu Corporation
    Inventors: Ken Mochizuki, Osamu Sugiyama
  • Publication number: 20040088621
    Abstract: A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.
    Type: Application
    Filed: May 13, 2003
    Publication date: May 6, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Ryuji Shimizu
  • Publication number: 20040088622
    Abstract: An embodiment of the present invention includes a range generator to simplify equivalence checking. A range generator is constructed. The range generator is represented by a characteristic function of a range of a cut function for a cut circuit in an implementation circuit and a reference circuit. The range generator is simpler than the cut circuit. Equivalence of the implementation circuit and the reference circuit is checked using the range generator.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Inventors: Robert M. Graham, Kenneth S. McElvain
  • Publication number: 20040088623
    Abstract: A digital signal voting circuit (10) is described for each module in a modular uninterruptible power supply (UPS) in which a plurality of modules are connected in parallel The voting circuit (10) includes a first comparator (14) for comparing a decision output signal of the Voting circuit, and the cumulative effect of the decision output signals of the voting circuits in parallel modules with a reference threshold signal (VREF). Comparator (14) generates a first comparison result signal when the decision output signal (D) is greater than the reference threshold signal (VREF) Logic element (12) has two inputs, one of which is fed with a control signal (A1) from the module and a second input which receives an output signal (A2) from the first comparator (14). When the output signal (A3) of logic element (12) is low, it will go high when either one of the input signals (A1 or A2) goes high.
    Type: Application
    Filed: July 10, 2003
    Publication date: May 6, 2004
    Inventor: Pit-Kin Loh
  • Publication number: 20040088624
    Abstract: A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.
    Type: Application
    Filed: October 22, 2002
    Publication date: May 6, 2004
    Inventors: Claude R. Gauthier, Aninda K. Roy, Brian W. Amick