Abstract: An oxygen sensor interface circuit is configurable on the fly by an electronic controller such as an engine controller to support oxygen sensors having unique interface requirements, to reliably identify various oxygen sensor faults, and to enable rapid detection of a warmed up sensor. The interface circuit is configurable in a first respect to enable operation with any of a number of different sensors, and in a second respect to enable more reliable fault detection, including measurement of leakage to ground or battery.

Abstract: The objects of the invention are to provide a low cost, stable, portable, and rugged field-use device that measures wet density, moisture content, and dry density in soils that have been constructed for use as road beds and building foundations. This data is used to ensure the quality control of the constructed foundation. The present invention integrates the complex science of soil mechanics with electrical engineering to provide efficient evaluation of soil materials that are used in civil construction.

Abstract: An orientation sensor especially suitable for use in an underground device is disclosed herein. This orientation sensor includes a sensor housing defining a closed internal chamber, an arrangement of electrically conductive members in a predetermined positional relationship to one another within the chamber and a flowable material contained within the housing chamber and through which electrical connections between the electrically conductive members are made such that a comparison between an electrical property, specifically voltage, of a first combination of conductive members to the corresponding electrical property of a second combination of conductive members can be used to determine a particular orientation parameter, specifically pitch or roll of the sensor.

Abstract: A direct current and a modulation signal are simultaneously applied to contact pads on a wafer to test certain devices, such as a laser diode. A probe, probing system, and method of probing reduces signal distortion and power dissipation by transmitting a modulated signal to the device-under-test through an impedance matching resistor and transmitting of a direct current to the device-under-test over a signal path that avoids the impedance matching resistor.

Abstract: In a jig for inspecting a device provided with at least a radio frequency signal terminal and an earth terminal, a metal block is formed with a through hole extending in a first direction. A contact probe is inserted into the through hole. The contact probe is provided with a metal pipe extending in the first direction. A plunger is retractably projected from one longitudinal end of the metal pipe to be brought into contact with the radio frequency signal terminal. At least two dielectric ring members are provided on an outer periphery of the metal pipe, and fitted with the through hole while forming a gap between the outer periphery of the metal pipe and an inner wall of the through hole, in order to form a coaxial path in which the contact probe serves as a core conductor and the metal block serves as an external conductor.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided.

Abstract: A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously.

Abstract: A first dynamic logic circuit has an output node on which a scan value is provided during scan. One of one or more second dynamic logic circuits has an input coupled to the output node of the first dynamic logic circuit, and an output of the second dynamic logic circuits is sampled in response to the scan value during scan. In one embodiment, clock generation circuitry may be included which generates a first clock, a second clock, and a third clock. At least one evaluate pulse on the first clock prior is generated prior to sampling the output of the second dynamic logic circuits, the first clock controlling at least the evaluation of the second dynamic logic circuits. The second and third clocks are generated to isolate the output node from inputs to the first dynamic logic circuit responsive to the scan mode signal indicating that scan is active.

Abstract: A pseudo-NMOS circuit includes a load PFET electrically connected between a power supply and an output node, and an NFET circuit having a plurality of inputs connected between the output node and ground. A feedback PFET is electrically connected between the power supply and the output node, in parallel with the load PFET, and is controlled by a signal at the output node of the pseudo-NMOS circuit.

Abstract: The present invention relates to circuits having differential structure which uses complementary devices for processing single-ended signal. The single-ended differential circuit in accordance with the present invention, comprises first and second complementary devices having first, second, and third terminals, respectively, wherein current flowing from the second terminal to the third terminal has its quantity and direction being varying in dependant on the voltage driven to the first terminal, wherein the currents flowing through the first and second complementary devices vary in opposite relationship.

Abstract: A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

Abstract: A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.

Abstract: A clock switching circuit comprises:

Abstract: A waveform generator for generating a desired waveform is provided, including a noise kernel configured to store a plurality of samples from a predetermined waveform, the plurality of samples being assigned to a plurality of memory blocks; and an address arrangement configured to randomly select a selected one of the plurality of memory blocks; wherein the noise kernel is configured to communicate the plurality of samples assigned to the selected memory block.

Abstract: Pixel circuits 20 include a driving transistor Qd, a first switching transistor Qs1, a second switching transistor Qs2, a storage capacitor Co, and an organic EL element 21, respectively. Each control circuit TS, which is connected to second electrode E2 of the organic EL element 21 through an electric potential control line Lo and sets the electric potential of the second electrode E2 to a driving voltage Vdd or a cathode voltage Vo, is provided between first and second voltage supply lines La and Lb and the pixel circuits 20 in the rightmost column direction of the pixel circuits arranged on a display panel in a matrix.

Abstract: A rewritable memory (120) stores a plurality of regulation amounts (increase amounts and decrease amounts) related to values of signals (240b and 240c) (to give information about a difference amount between an oscillation frequency of a ring oscillator (110) and a desired frequency). A control circuit (131) selects one of the regulation amounts from the memory (120) corresponding to the values of the signals (240b and 240c) and increases or decreases a value of a counter (132) by the regulation amount thus selected. The oscillation frequency is regulated by the value of the counter (132).

Abstract: A synchronization circuit comprises a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock; a delay selection circuit for adding a delay to the input signal on the basis of the control signal; and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Abstract: A reset signal generating circuit and a nonvolatile ferroelectric memory device using the same are disclosed. The reset signal generating circuit comprises: a power detector for maintaining the size of an applied voltage for a predetermined period; a threshold voltage controller for outputting a voltage by regulating the level of a power voltage for generating a reset signal depending on variations of the power voltage and a bias voltage; a feedback controller for pulling down an output voltage of the power detector when the power voltage reaches a predetermined level depending on an output voltage of the threshold voltage controller; a pull-up controller for pulling up an output voltage of the power detector and outputting an output voltage variation of the power detector as the reset signal; and a self-bias unit for outputting the bias voltage and regulating the amount of a current supplied from the threshold voltage controller to the feedback controller depending on variations of the power voltage.

Abstract: The present invention aims to economically implement an ultra-compact semiconductor device having an identification number according to the efficient utilization of an electron-beam writing method.

Abstract: A reset pulse generator. The CPU generates an oscillating disable signal after initialization. The oscillating circuit is coupled to the CPU to output a sequence of reset pulses to the CPU. The oscillating disable circuit is coupled to the oscillating circuit for disabling the oscillating circuit and initiating normal mode CPU operation when the oscillating disable signal is received.

Abstract: The present invention provides a duty cycle correction circuit (DCC) and a delay locked loop (DLL) including the same. The inventive duty cycle correction circuit includes: a first clock dividing unit and a second clock dividing unit for dividing an ordinary input clock and a sub ordinary input clock; a first clock mixing unit; a second clock mixing unit; and a logic combination unit for generating a duty cycle correction clock. In addition, the inventive delay locked loop (DLL) includes: a first and second clock dividing unit; a frequency detecting unit; a first variable delaying unit; a second variable delaying unit; a first clock mixing unit; a second clock mixing unit; and a logic combination unit.

Abstract: A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto. By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%.

Abstract: A system for reducing current leakage in an integrated circuit. The system includes a first circuit component and a second circuit component in a path between a high voltage state and a low voltage state, such as ground. A feedback mechanism selectively provides feedback from an output of the second circuit component to an input of the first circuit component to selectively cutoff the path at the first circuit when the path is not cutoff at the second circuit. In a more specific embodiment, feedback mechanism preserves data in the integrated circuit via a multiplexer that selectively enables the feedback when the integrated circuit is in sleep mode. The first and second circuit components are High Voltage Threshold (HVT) CMOS inverters. The feedback path is chosen so that when the feedback path is activated, leakage paths through the CMOS inverters are cutoff.

Abstract: A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: It is an objective of the present invention to provide a pipe latch circuit with simpler control, smaller footprint, and higher speed operation.

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract: The present invention relates to a semiconductor device and, more particularly, to a clock enable buffer to output a clock enable signal which enables a clock buffer to produce an internal clock signal. The semiconductor device according to the present invention comprises: a clock buffer for receiving and buffering an external clock signal and then outputting an internal clock; a clock enable buffer for comparing a reference voltage having a constant potential with a clock enable buffer signal and then enabling the clock buffer; and a clock enable signal latch circuit for enabling the clock enable buffer using the clock enable buffer signal after a power-up signal is inputted.

Abstract: A multiplexer includes first through fourth switching sections 10A through 10D in a pre-stage gate and each of the switching sections 10 includes a serial capacitor 3 and a FET 4. The serial capacitor 3 includes a ferroelectric capacitor 1 and a paraelectric capacitor 2 and an intermediate node of the serial capacitor 3 is connected to a gate electrode 8 of the FET 4. In a unit selector Use11 made up of the switching sections 10A and 10B, a voltage applied to the intermediate node 9 is distributed according to the difference between the capacitances of the two capacitors so that in the switching section 10A and 10B, the FETs 4 alternately turn ON and OFF according to the logical value, 1 or 0, of a selection signal D1. Accordingly, an operation state is stored in a nonvolatile state in the ferroelectric capacitor 1.

Abstract: A switch circuit includes an input terminal which receives an input signal and an internal circuit which executes a predetermined function. The switch circuit also includes a first switch element which is coupled between the input terminal and the internal circuit and which has a control gate receiving a control signal, a first electrode coupled to the input terminal, and a second electrode. The switch circuit also includes a second switch element which is coupled between the input terminal and the internal circuit and which has a control gate receiving the control signal, a first electrode coupled to the second electrode of the first switch element, and a second electrode coupled to the internal circuit.

Abstract: A transconductance circuit (16) and method for protecting an H-bridge power circuit (10) that provides power to a load that includes an inductive component (14) connected between one side of the inductive component (14) and a gate (25) of a low side transistor (24) of the H-bridge (10). The transconductance circuit (16) operates to pull current from the inductive component (14) to ground (30) when the inductive load (14) sources current to a body diode of the high side transistor (20). The transconductance circuit (16) creates a regulated voltage to the gate (25) of the low side transistor (24) to cause the low side transistor (24) to conduct the current away in a regulated manner from the inductor (14) and the high side transistor (20) to ground (30).

Abstract: A driving circuit for a light emitting device keeping its excellent eye pattern by improving an extinction ratio and reducing power consumption, can be provided by arranging the following way. The driving circuit has a driving unit having a frequency response curve indicating opposite property to a frequency response curve of the light emitting device. The driving unit comprises a power outputting type amplifier constituted by a transistor having a gain curve increasing with a predetermined gradient starting from a cut-off frequency of the light emitting device. The amplifier comprises a frequency generating unit constituted by a capacitor and a resistance for generating a desired frequency, a current multiplier unit constituted by a current mirror circuit comprising 7 transistors and a discharge circuit for applying a reverse current, which is distributed from the current multiplier circuit, to the light emitting device.

Abstract: In an up-converter feed forward control of the output current is effected by rendering the conduction time of the switching element proportional to Vout/Vin2. This control is fast and avoids interference and loss of efficiency.

Abstract: A bandgap voltage reference circuit that utilize a two-stage transconductance amplifier as a feedback control loop to improve the accuracy and stability of the output reference voltage without the need for an additional biasing circuit. The high gain provides a good power-supply rejection ratio, and improves the circuit performance. The amplifier does not require a biasing circuit, thus saving valuable chip space. Furthermore, eliminating the need for a biasing circuit reduces the power consumption of the circuit.

Abstract: A modified Brokaw cell-based circuit produces a current which varies linearly with temperature. The collector-emitter current flow path of a diode-connected transistor is connected in series with the PTAT current produced by a control transistor. The base of the control transistor receives a control voltage whose value defines a limited range of variation of output current with temperature. The output transistor is coupled to an input port of a current mirror, which mirrors the linear collector current from the output transistor. The current through the output transistor is controlled by a composite of a CTAT base-emitter voltage of the diode-connected transistor and a PTAT voltage across a resistor, so that the output transistor produces an output current having a linear temperature coefficient.

Abstract: A current source circuit for generating a low-noise current has a current mirror circuit with a first and a second transistor. The current mirror circuit contains a capacitor connected between a source connection and a gate connection of the second transistor. The current mirror circuit likewise contains a switching element disposed between a drain connection of the first transistor and the gate connection of the second transistor. The switching element may be controlled as a function of an operating state of the current source circuit.

Abstract: A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an output signal. If the output signal edge is out of phase with the input clock edge, the circuit shifts the output signal by 180 degrees to effectively produce a single double-length clock phase. The synchronized phase-locked loop circuit provides predictable phase-locked loop output phase synchronization with an input clock.

Abstract: A balanced power amplifier circuit arrangement comprises a driver amplifier stage (22) adapted to receive and amplify a signal. The amplified signal is input to a first coupler (26). The first coupler (26) produces an in-phase signal and an out-of-phase quadrature signal. A first power amplifier (38) receives and amplifies the in-phase signal. A second power amplifier (40) receives and amplifies the out-of-phase signal. A first switch (28) alternately connects an isolated port of the first coupler to ground (32) or a bypass path (36). A second coupler (42) receives and combines the amplified in-phase signal and the amplified out-of-phase signal to produce a combined signal. A second switch (30) alternately connects an isolated port of the second coupler (42) to either ground (34) or the bypass path (36). When the power amplifiers (38, 40) are powered down, the first coupler (26) splits the RF-signal into an in-phase signal and an out-of-phase signal.

Abstract: Apparatus, methods and articles of manufacture are shown for modifying electromagnetic waves. Through using various wave characteristics such as amplitude to regulate a current source, a current is output that may be used in any number of ways, such as driving an antenna or other load.

Abstract: An adaptive bias control circuit for use with a radio frequency (RF) power amplifier, the RF power amplifier having an input (112) for receiving an input signal having a varying amplitude, an output (116), a first transistor (110), and a plurality of operating performance characteristics responsive to a quiescent operating point established by a bias current in the RF power amplifier, the bias control circuit having: a first circuit (120) coupled to the RF power amplifier for receiving a portion of the input signal; and a second transistor (122) for generating a rectified signal from the portion of the input signal, the rectified signal for causing the bias current to be controlled as a function of the amplitude of the input signal, the second transistor having a first and second terminal connected together and coupled to the first circuit and a third terminal coupled to a ground potential.

Abstract: An adaptive bias control circuit for use with a radio frequency (RF) power amplifier, the RF power amplifier having an input (112) for receiving an input signal having a varying amplitude, an output (116), a first transistor (110), and a plurality of operating performance characteristics responsive to a quiescent operating point established by a bias current in the RF power amplifier, the bias control circuit having: a first circuit (120) coupled to the RF power amplifier for receiving a portion of the input signal; and a second transistor (122) for generating a rectified signal from the portion of the input signal, the rectified signal for causing the bias current to be controlled as a function of the amplitude of the input signal, the second transistor having a first and second terminal connected together and coupled to the first circuit and a third terminal coupled to a fixed voltage.

Abstract: A system for dynamically trimming a voltage controlled oscillator operable to receive a trim signal for adjusting a voltage-to-frequency operating characteristic of the voltage controlled oscillator and receive a tune signal to generate an output signal having an output frequency determined by the voltage-to-frequency operating characteristic includes a trim circuit operable to receive the tune signal and generate the trim signal and increment or decrement the trim signal and condition a change in the trim signal during the increment or decrement so that the voltage-to-frequency operating characteristic of the voltage controlled oscillator drifts from a first voltage-to-frequency operating characteristic to a second voltage-to-frequency operating characteristic.

Abstract: Provided is an adaptive loop bandwidth phase locked loop (PLL) including a deglitch circuit for providing short lock time. The adaptive loop bandwidth can perform a lock operation without having any bad influence on other devices and can detect a difference between the frequency and phase of a signal using a deglitch circuit in an adaptive loop bandwidth manner that can provide short lock time.

Abstract: A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

Abstract: A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time.

Abstract: A voltage-controlled oscillator (VCO) having a bandpass filter includes an oscillation circuit and a bandpass filter. The oscillation circuit outputs a first oscillation frequency with a harmonic distortion according to a tuning voltage. The first oscillation frequency is then input to the bandpass filter and the harmonic distortion of the first oscillation frequency is filtered. Therefore, a second oscillation frequency without the harmonic distortion is output from the bandpass filter. The invention is characterized by that the bandpass filter that removes the harmonic distortion from the VCO.

Abstract: A surface mount crystal unit comprising a crystal blank, a planar mounting substrate made of silicon and a cover having a shape with a recess and made of glass containing ions having high mobility. The mounting substrate and the cover are bonded by means of anode bonding and the crystal blank is hermetically sealed in a case made up of the mounting substrate and the cover. The mounting substrate has connection electrodes used for a connection with the crystal blank and external terminals to be used to surface-mount the crystal unit. The connection electrodes and external terminals are electrically connected.

Abstract: The respective ends of input wiring on a printed wiring board of a signal transmission circuit are connected to an input terminal section and a transistor. The respective one terminals of a first capacitor and a first resistor are connected to the input wiring. A leading-side transmission path from a connection point with the first capacitor to a connection point with the input terminal section is formed by only a conductive pattern. An intermediate transmission path from the connection point with the first capacitor to a connection point with the first resistor includes two or more through holes or via holes. The intermediate transmission path is placed near grounding wiring on the printed wiring board. When one terminal of a second capacitor is connected to the intermediate transmission path, a transmission path between the respective connection points with the two capacitors includes one or more through holes or via holes.

Abstract: An electromagnetic coupling connector for three-dimensional electronic circuits is described. The coupling connector includes two coupling layers each having multiple electromagnetic coupling elements. Each coupling element can communicate through an electromagnetic path to a mating coupling element in a separate coupling connector. A routing layer is disposed between the two coupling layers and conducts an electrical signal between a coupling in one layer and at least one coupling element in the other layer. The coupling connector can also include a device layer having devices such as analog processors, memory modules and switching processor modules.

Abstract: A continuously variable quarter-wave transformer (103) including a quarter-wave element (110). The quarter-wave transformer has a characteristic impedance and is at least partially coupled to a fluidic dielectric (108). A controller (136) is provided for controlling a composition processor (101) which is adapted for dynamically changing a composition of the fluidic dielectric (108) to vary the permittivity and permeability in response to a control signal (137). The permeability and permittivity can be varied together to maintain approximately constant impedance and length in wavelengths at different operating frequencies, or to vary impedance and maintain constant length at a given frequency. The quarter-wave transformer (103) can be coupled to a solid dielectric substrate material. A plurality of component parts can be dynamically mixed together in the composition processor (101) responsive to the control signal (137).