Patents Issued in June 1, 2004
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Patent number: 6743644Abstract: The present invention relates to metallization line layouts that minimize focus offset sensitivity by a substantial elimination of thin isolated metallization line segments that are inadequately patterned during formation of a mask. The present invention also relates to a metallization line layout that staggers unavoidable exposures. Embodiments of these metallization line layouts include enhanced terminal ends of isolated metallization lines, filled inter-metallization line spaces, and additional “dummy” metal shapes in open areas. The present invention also relates to a method of forming a metallization layer such that a substantially deposited, planarized interlayer dielectric layer can be formed without etchback or chemical-mechanical polishing.Type: GrantFiled: March 25, 2002Date of Patent: June 1, 2004Assignee: Micron Technology, Inc.Inventor: Werner Juengling
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Patent number: 6743645Abstract: A method of inspecting a process for manufacturing a semiconductor device, used to determine the status of a processing operation during the manufacturing process, according to the embodiment of the present invention, comprises: detecting an image of a desired area of a surface of a semiconductor workpiece after it has been subjected to the processing operation, using an image signal detector; detecting image signal intensity at each pixel of a plurality of pixels of the image signal detector; and determining the status of the processing operation based on the relationship between the image signal intensity and the number of pixels at each of certain levels of the image signal intensity. A method of manufacturing a semiconductor device is made by utilizing the above-described inspection method.Type: GrantFiled: March 28, 2002Date of Patent: June 1, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Takeo Kubota, Atsushi Shigeta
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Patent number: 6743646Abstract: One embodiment of the present invention is a method of designing underlying structures in a wafer with pads of varying sizes and varying loading factors, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with random shapes of varying sizes and varying loading factors. Still another embodiment is the use of periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer.Type: GrantFiled: October 22, 2001Date of Patent: June 1, 2004Assignee: Timbre Technologies, Inc.Inventors: Nickhil Jakatdar, Xinhui Niu
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Patent number: 6743647Abstract: A method of the present invention of manufacturing a semiconductor memory device provided with a capacitor over a semiconductor substrate, which has a lamination of a lower electrode made of a first conductive film, a capacitor dielectric film made of a dielectric film, and an upper electrode made of a second conductive film, comprises the steps of forming an insulating film, forming a capacitor on the insulating film, forming a dielectric monitor that is made of same material and has a same layer structure as the capacitor on the insulating film, measuring characteristics of the dielectric monitor in middle of a step of forming the capacitor, and evaluating the capacitor based on measured results of the characteristics of the dielectric monitor.Type: GrantFiled: February 6, 2003Date of Patent: June 1, 2004Assignee: Fujitsu LimitedInventor: Yukinobu Hikosaka
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Patent number: 6743648Abstract: A method for forming a set of DFB lasers includes the steps of forming active layers having different peak gain wavelengths, measuring the peak gain wavelengths of the active layers, and forming diffraction gratings having periods based on the measured peak gain wavelengths, the periods allowing the detuning amount of the DFB laser device to fall within a design value.Type: GrantFiled: June 13, 2002Date of Patent: June 1, 2004Assignee: The Furukawa Electric Co., Ltd.Inventors: Tomofumi Kise, Masaki Funabashi
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Patent number: 6743649Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.Type: GrantFiled: January 7, 2003Date of Patent: June 1, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yasuyuki Arai
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Patent number: 6743650Abstract: In an active matrix semiconductor display device in which pixel TFTs and driver circuit TFT are formed on the same substrate in an integral manner, the cell gap is controlled by gap retaining members that are disposed between a pixel area and driver circuit areas. This makes it possible to provide a uniform cell thickness profile over the entire semiconductor display device. Further, since conventional grainy spacers are not used, stress is not imposed on the driver circuit TFTs when a TFT substrate and an opposed substrate are bonded together. This prevents the driver circuit TFTs from being damaged.Type: GrantFiled: September 9, 2002Date of Patent: June 1, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiharu Hirakata, Takeshi Nishi, Shunpei Yamazaki
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Patent number: 6743651Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i.e., heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.Type: GrantFiled: April 23, 2002Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Jack O. Chu, Feng-Yi Huang, Steven J. Koester, Devendra K. Sadana
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Patent number: 6743652Abstract: Fast and efficient photodiodes with different structures are fabricated using CMOS process technology by adapting transistor structures to form the diode structures. The anode regions of the photodiodes correspond to either PLDD regions of PMOS transistors or P-wells of NMOS transistors to provide two different photodiode structures with different anode region depths and thus different drift region thicknesses. An antireflective film used on the silicon surface of the photodiodes is employed as a silicide-blocking mask at other locations of the device.Type: GrantFiled: February 1, 2002Date of Patent: June 1, 2004Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Gilles E. Thomas
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Patent number: 6743653Abstract: A micromachine manufacturing method according to this invention includes at least the movable portion formation step of selectively etching a single-crystal silicon layer by using a movable portion formation mask pattern as a mask, thereby forming on the single-crystal silicon layer a movable portion which is coupled to the surrounding single-crystal silicon layer via a coupling portion on a buried oxide, the movable portion protective film formation step of forming a movable portion protective film on the single-crystal silicon layer so as to cover the movable portion while the movable portion is formed on the buried oxide, and the step of forming a buried protective film which covers the movable portion exposed in the substrate opening and movable portion opening, and the single-crystal silicon layer around the movable portion while the movable portion protective film is formed.Type: GrantFiled: May 8, 2003Date of Patent: June 1, 2004Assignee: Nippon Telegraph and Telephone CorporationInventors: Yasuyuki Tanabe, Katsuyuki Machida, Hiromu Ishii, Shouji Yagi
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Patent number: 6743654Abstract: A method of making a monolithically integrated pressure sensor includes making a cavity in the semiconductor substrate. This may be formed by plasma etching the front side or the back side of the silicon wafer to cut a plurality of trenches or holes deep enough to extend for at least part of its thickness into a doped buried layer of opposite type of conductivity of the substrate and of the epitaxial layer grown over it. The method may also include electrochemically etching through such trenches, and the silicon of the buried layer with an electrolytic solution suitable for selectively etching the doped silicon of the opposite type of conductivity, thereby making the silicon of the buried layer porous. The method may also include oxidizing and leaching away the silicon so made porous.Type: GrantFiled: December 11, 2001Date of Patent: June 1, 2004Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Coffa, Luigi Occhipinti
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Patent number: 6743655Abstract: A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.Type: GrantFiled: July 25, 2002Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Fen Chen, Roger Aime Dufresne, Baozhen Li, Alvin Wayne Strong
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Patent number: 6743656Abstract: An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer fabrication and packaging technology. The device is contained within a hermetic cavity produced by bonding a silicon wafer with active circuits to an etched silicon wafer having cavities which surround each device, and bonding the two wafer by either thin film glass seal or by solder seal. The etched wafer and thin film sealing allow conductors to be kept to a minimum length and matched for improved electrical control of the circuit. Further, the device has capability for a ground ring in the solder sealed device. The devices may be packaged in plastic packages with wire bond technology or may be solder connected to an area array solder connected package.Type: GrantFiled: July 23, 2002Date of Patent: June 1, 2004Assignee: Texas Instruments IncorporatedInventors: John W. Orcutt, Andrew Steven Dewa, Tsen-Hwang Lin
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Patent number: 6743657Abstract: An Indium/Gallium/Arsenide (InGaAs) detector having avalanche photodiodes (APD's) and p-i-n photodiodes on a single chip is provided. A method of fabricating the InGaAs device is also provided. The bias on the APD and p-i-n photodiodes are separately controlled.Type: GrantFiled: March 24, 2003Date of Patent: June 1, 2004Assignee: Finisar CorporationInventors: J. Christopher Dries, Michael Lange
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Patent number: 6743658Abstract: The present invention includes integrated circuit packages, ballgrid array integrated circuit packages and methods of packaging an integrated circuit. One aspect of the present invention provides an integrated circuit package including a substrate having opposing first and second substrate surfaces and at least one electrical connection supported by the first substrate surface and adapted to couple with circuitry external of the package; a semiconductor die including circuitry electrically coupled with the at least one electrical connection; a first die surface coupled with the second substrate surface; a second die surface; and a cover coupled with the second die surface.Type: GrantFiled: October 2, 2001Date of Patent: June 1, 2004Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 6743659Abstract: A method for manufacturing multi-layer package substrates is shown. A substrate with a first side and a second side is first provided, and a layer of release film is formed on the first side and second side of the substrate. After drilling a plurality of through holes on the substrate bonded to the release film and plugging the through holes with a conductive material, the release film is removed. A first copper film is formed on the first and second side of the substrate. First, circuit layer patterns are formed on the first and second side of the substrate through photolithography and etching processes. After coating an build-up layer on the first and second side of the substrate and drilling the build-up layers with a laser to form counter vias on the first side and second side of the substrate, a copper seed layer is formed on the inner surfaces of the counter vias. Second circuit layer patterns are formed on the first side and second side of the substrate.Type: GrantFiled: May 20, 2002Date of Patent: June 1, 2004Assignee: Via Technologies, Inc.Inventors: Moriss Kung, Kwun-Yao Ho
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Patent number: 6743660Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.Type: GrantFiled: January 12, 2002Date of Patent: June 1, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
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Patent number: 6743661Abstract: An apparatus and method for flexibly bonding an integrated circuit package to a printed circuit board are provided. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first end is configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.Type: GrantFiled: September 17, 2002Date of Patent: June 1, 2004Assignee: Novellus Systems, Inc.Inventor: John Stephen Drewery
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Patent number: 6743662Abstract: An RF semiconductor device is fabricated from a starting substrate comprising a polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the oxide layer.Type: GrantFiled: July 1, 2002Date of Patent: June 1, 2004Assignee: Honeywell International, Inc.Inventors: Mohammed A. Fathimulla, Thomas Keyser
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Patent number: 6743663Abstract: The invention relates to a method for producing a hybrid frame (1) or hybrid housing. According to said method, a leadframe (3) with soldering and/or bonding tags (3a), made from a plated strip, is placed into an injection mould and moulded with plastic in order to form a housing part (2) of the hybrid frame or the hybrid housing (1). According to the invention, the soldering and/or bonding tags (3a) of the leadframe (3) are kept in the injection moulding die at least during part of the injection-moulding process, by means of a plunger.Type: GrantFiled: July 30, 2001Date of Patent: June 1, 2004Inventors: Jorg Anderl, Herbert Bender, Winfried Lutte, Jurgen Vogel, Norbert Voll
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Patent number: 6743664Abstract: A method is provided including attaching an encapsulant to an integrated circuit (IC), forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, attaching a first surface of the substrate to the encapsulant so that the substrate is connected to the IC, attaching an electrical element to a second surface of the substrate, and electronically connecting the first surface of the substrate and the second surface of the substrate.Type: GrantFiled: December 6, 2001Date of Patent: June 1, 2004Assignee: Intel CorporationInventors: Chunlin Liang, Larry Eugene Mosley, Chun Mu
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Patent number: 6743665Abstract: Disclosed is a method for forming an isolation layer in a semiconductor device, in which when a masking insulation layer and an isolation oxide layer are sequentially subjected to a dry etching process in accordance with an isolation mask pattern, the isolation oxide layer is etched to have a thickness of approximately hundreds of angstroms from the top surface of the silicon substrate, thereby preventing the silicon substrate from being damaged by plasma. Therefore, reliability of the device can be improved. To this end, the method comprises the steps of forming an isolation oxide layer and a masking insulation layer on an silicon substrate in order; etching the masking insulation layer and the isolation oxide to form a trench; and growing an epitaxial silicon layer in the trench to form an epitaxial silicon active area.Type: GrantFiled: December 18, 2002Date of Patent: June 1, 2004Assignee: Dongbu Electronics Co., Ltd.Inventor: Cheol Soo Park
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Patent number: 6743666Abstract: A method of making a semiconductor device includes thickening source and drain regions. After a field effect device having a source region, a drain region, and a gate, is formed, a layer of semiconductor material is deposited on the device by a directional deposition method, such as collimated sputtering. Then the semiconductor material is selectively removed from side walls on either side of the gate, such as by isotropic back etching, leaving thickened semiconductor material in the source and drain regions, and on the gate.Type: GrantFiled: April 29, 2002Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Simon Siu-Sing Chan
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Patent number: 6743667Abstract: An amorphous semiconductor film comprising silicon is provided with a metal element which is capable of promoting a crystallization of silicon. Then, the semiconductor film is crystallized by hating at a relatively low temperature. After introducing impurity ions into source and drain regions of the semiconductor film, the source and drain regions are recrystallized by heating. During the recrystallization, the channel region having crystallinity functions as crystalline nuclei. Accordingly, it is possible to avoid defects occurring in the boundary regions between the channel region and source/drain regions.Type: GrantFiled: February 2, 2001Date of Patent: June 1, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masamitsu Hiroki, Yasuhiko Takemura, Mutsuo Yamamoto, Naoaki Yamaguchi, Satoshi Teramoto
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Patent number: 6743668Abstract: The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.Type: GrantFiled: April 29, 2003Date of Patent: June 1, 2004Assignee: Motorola, Inc.Inventors: James K. Schaeffer, III, Mark V. Raymond, Bich-Yen Nguyen
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Patent number: 6743669Abstract: A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si3N4 is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.Type: GrantFiled: June 5, 2002Date of Patent: June 1, 2004Assignee: LSI Logic CorporationInventors: Hong Lin, Shiqun Gu, Peter McGrath
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Patent number: 6743670Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.Type: GrantFiled: March 6, 2003Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Louis L. Hsu, Carl J Radens, Joseph F. Shepard, Jr.
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Patent number: 6743671Abstract: An integrated capacitor including a semiconductor substrate is disclosed. An outer vertical plate is laid over the semiconductor substrate. The outer vertical plate of a plurality of first conductive slabs connected vertically using multiple first via plugs. The outer vertical plate defines a grid area. An inner vertical plate is laid over the semiconductor substrate in parallel with the outer vertical plate and is encompassed by the grid area defined by the outer vertical plate. The inner vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A horizontal conductive plate is laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The inner vertical plate is electrically connected with the horizontal conductive plate using at least one third via plug.Type: GrantFiled: November 7, 2002Date of Patent: June 1, 2004Assignee: Ali CorporationInventors: Man-Chun Hu, Wen-Chung Lin
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Patent number: 6743672Abstract: A method for manufacturing a capacitor including forming an electrode with a top portion having relatively smaller width than its bottom portion. The method includes the steps of: forming a seed layer on a semiconductor substrate; forming a first insulating layer on the seed layer; forming an opening unit which has relatively larger width in a top portion than a bottom portion by selectively etching the first insulating layer and the seed layer; forming a second insulating layer on the seed layer which is exposed after forming the opening unit; removing the first insulating layer using an etching which uses a selective etching ratio between the first insulating layer and the second insulating layer; after removing the first insulating layer, forming a bottom electrode on the exposed seed layer using an electro plating (EP) method; and removing the second insulating layer.Type: GrantFiled: May 2, 2002Date of Patent: June 1, 2004Assignee: Hynix Semiconductor Inc.Inventor: Jong-Bum Park
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Patent number: 6743673Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.Type: GrantFiled: May 16, 2002Date of Patent: June 1, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kozo Watanabe, Atsushi Ogishima, Masahiro Moniwa, Syunichi Hashimoto, Masayuki Kojima, Kiyonori Ohyu, Kenichi Kuroda, Nozomu Matsuda
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Patent number: 6743674Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. The control gate polysilicon is formed over the substrate, and protected by a layer of protective material, before the formation of other polysilicon elements associated with the memory array, to ensure the proper remove of residual polysilicon stringers.Type: GrantFiled: July 24, 2002Date of Patent: June 1, 2004Assignee: Silicon Storage Technology, Inc.Inventor: Chih Hsin Wang
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Patent number: 6743675Abstract: A silicon nitride layer (120) is formed over a semiconductor substrate (104) and patterned to define isolation trenches (130). The trenches are filled with dielectric (210). The nitride layer is removed to expose sidewalls of the trench dielectric (210). The dielectric is etched to recess the sidewalls away from the active areas (132). Then a conductive layer (410) is deposited to form floating gates for nonvolatile memory cells. The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.Type: GrantFiled: October 1, 2002Date of Patent: June 1, 2004Assignee: Mosel Vitelic, Inc.Inventor: Yi Ding
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Patent number: 6743676Abstract: The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.Type: GrantFiled: November 4, 2002Date of Patent: June 1, 2004Assignee: Hynix Semiconductor Inc.Inventors: Sung Kee Park, Ki Seog Kim, Keun Woo Lee, Keon Soo Shim
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Patent number: 6743677Abstract: The present invention is a method for fabricating nitride memory cells using a floating gate fabrication process. In one embodiment of the present invention, the fabrication process of a floating gate memory cell is accessed. The floating gate memory cell fabrication process is then altered to produce an altered floating gate memory cell fabrication process. The altered floating gate memory cell fabrication process is then used to form a nitride memory cell.Type: GrantFiled: November 27, 2002Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Mark W. Randolph, Darlene G. Hamilton, Binh Quang Le, Wei Zheng
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Patent number: 6743678Abstract: A lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer. Diffusion of second metal atoms into the lower electrode may reduce or prevent crystal grain growth and agglomeration on a surface of the lower electrode during a subsequent high temperature process.Type: GrantFiled: April 28, 2003Date of Patent: June 1, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-hee Lee, Sung-tae Kim, Cha-young Yoo, Han-jin Lim, Wan-don Kim, Se-hoon Oh
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Patent number: 6743679Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.Type: GrantFiled: April 19, 2002Date of Patent: June 1, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Xi-Wei Lin, Gwo-Chung Tai
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Patent number: 6743680Abstract: A method of manufacturing an integrated circuit includes providing an amorphous semiconductor material including germanium, annealing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.Type: GrantFiled: June 22, 2000Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6743681Abstract: Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.Type: GrantFiled: November 9, 2001Date of Patent: June 1, 2004Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 6743682Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer.Type: GrantFiled: March 18, 2002Date of Patent: June 1, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Pierre Hermanus Woerlee, Jurriaan Schmitz, Andreas Hubertus Montree
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Patent number: 6743683Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.Type: GrantFiled: December 4, 2001Date of Patent: June 1, 2004Assignee: Intel CorporationInventors: Chris E. Barns, Mark Doczy
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Patent number: 6743684Abstract: Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a gate structure over the semiconductor substrate, wherein a dopant material is implanted at an angle around the gate structure to form a halo structure in a source/drain region of the substrate and underlying a portion of the gate structure. A trench is formed in the source/drain region of the semiconductor substrate thereby removing at least a portion of the halo structure in the source/drain region. A silicon material layer is then formed in the trench using an epitaxial deposition.Type: GrantFiled: October 11, 2002Date of Patent: June 1, 2004Assignee: Texas Instruments IncorporatedInventor: Kaiping Liu
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Patent number: 6743685Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.Type: GrantFiled: February 15, 2001Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventors: David D. Wu, Michael P. Duane, Scott D. Luning
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Patent number: 6743686Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.Type: GrantFiled: June 14, 2002Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Kam Leung Lee, Ying Zhang, Maheswaran Surendra, Edmund M. Sikorski
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Patent number: 6743687Abstract: Micro-miniaturized semiconductor devices having transistors with abrupt high concentration shallow source/drain extensions are fabricated by sequentially forming deep source/drain regions, pre-amorphizing intended shallow source/drain extension regions, ion implanting impurities into the pre-amorphized regions and then laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions. Embodiments include forming the deep source/drain regions using removable sidewall spacers on the gate electrode, removing the sidewall spacers, forming the ion implanted pre-amorphized source/drain exension implants, forming laser transparent oxide sidewall spacers on the gate electrode and laser thermal annealing through the oxide laser transparent sidewall spacers to selectively activate the source/drain extensions.Type: GrantFiled: September 26, 2002Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6743688Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.Type: GrantFiled: January 5, 1998Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. James Fulford, Charles E. May
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Patent number: 6743689Abstract: Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.Type: GrantFiled: January 14, 2003Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Qi Xiang, Bin Yu
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Patent number: 6743690Abstract: A method of forming a metal-oxide semiconductor (MOS) transistor. A semiconductor substrate is provided. A polysilicon layer is then deposited on the semiconductor substrate. The polysilicon layer is selectively etched to form a gate electrode. A silicon oxide layer is grown on the top and the sidewall. Ions (or dopants) are doped into the semiconductor substrate to form a lightly doped region. Then, a nitride spacer is formed on the sidewall of the silicon oxide layer. Finally, ions are doped into the semiconductor substrate to form a heavily doped region to serve as a source/drain of the MOS transistor.Type: GrantFiled: September 10, 2002Date of Patent: June 1, 2004Assignee: Silicon Integrated Systems Corp.Inventors: Tzu-Kun Ku, Wen-Chu Huang
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Patent number: 6743691Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.Type: GrantFiled: December 27, 2001Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Masao Yamane, Kazuhiro Mochizuki
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Patent number: 6743692Abstract: It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film (17) is formed on a side surface of a gate structure (60) provided on a semiconductor substrate (1), and epitaxial layers (19a) and (19b) are formed in self-alignment on n-type impurity regions (13a) and (13b) so that the sidewall insulating film (17) lies between the epitaxial layers (19a) and (19b) and a gate electrode (50). An etching blocking film (20) and an interlayer insulating film (21) are formed over a whole surface in this order. Using the etching blocking film (20) as an etching stopper, the interlayer insulating film (21) is etched and the exposed etching blocking film (20) is subsequently etched. Consequently, contact holes (30a) and (30b) reaching the epitaxial layers (19a) and (19b) are formed.Type: GrantFiled: March 11, 2003Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventors: Shigeru Shiratake, Masahiko Takeuchi
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Patent number: 6743693Abstract: A photomask includes patterns corresponding to openings, a pattern corresponding to a trench and dummy patterns not to be transferred to a photoresist. The patterns are arranged in a matrix at a second pitch in the column direction and at a first pitch in the row direction. The dummy patterns are spaced at the second pitch from the most adjacent ones of the patterns aligned in the row direction, and the dummy patterns are spaced at a first pitch from the most adjacent ones of the patterns aligned in the column direction. Using such photomask, openings on each of which a lower electrode of a capacitor is to be formed are formed in an insulation layer in a memory cell array forming region, and the trench is formed in the insulation layer at the border between the memory cell array forming region and a peripheral circuit forming region.Type: GrantFiled: November 22, 2002Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventor: Yoshitaka Fujiishi