Abstract: A new method of forming a laser mark without damage to the wafer surface is described. A pad oxide layer is formed on a silicon wafer. A nitride layer is deposited overlying the pad oxide layer. A first trench is laser cut through the nitride layer and the pad oxide layer into the silicon wafer. The trench is etched to a second depth wherein the nitride layer is used as a hard mask and wherein the trench forms an identification mark.

Abstract: In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Abstract: A method of coupling a single crystal semiconductor layer to a support substrate. Thinning the single crystal layer. Introducing an integrated circuit into the single crystal layer. And removing the thinned single crystal layer with the integrated circuit from the support substrate.

Abstract: There are disclosed a semiconductor wafer which has undulation components on wafer back surface and/or wafer front surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; method for producing a semiconductor wafer by polishing front surface of the semiconductor wafer which is held at its back surface, which utilizes a semiconductor wafer to be polished having undulation components on wafer back surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; and wafer chuck provided with a holding surface for holding a wafer by chucking, wherein the holding surface has undulation components of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.

Abstract: A plurality of semiconductor dice are provided on a substrate having a first side and a second side, with the semiconductor dice being spaced from one another by scribe line area. A stencil is positioned over at least one of the first side and the second side of the substrate. The stencil has masking sections which cover at least portions of the scribe line area. A polymer is applied through the positioned stencil onto the first or second side of the substrate over which the stencil is received, with the stencil substantially precluding the polymer from being applied on the covered portions of the scribe line area. After the applying, portions of the scribe line area are cut into and the plurality of dice are singulated from the substrate. Other aspects and implementations are contemplated.

Abstract: A semiconductor film having a crystalline structure is formed by using a metal element that assists the crystallization of the semiconductor film, and the metal element remaining in the film is effectively removed to decrease the dispersion among the elements. The semiconductor film or, typically, an amorphous silicon film having an amorphous structure is obtained based on the plasma CVD method as a step of forming a gettering site, by using a monosilane, a rare gas element and hydrogen as starting gases, the film containing the rare gas element at a high concentration or, concretely, at a concentration of 1×1020/cm3 to 1×1021/cm3 and containing fluorine at a concentration of 1×1015/cm3 to 1×1017/cm3.

Abstract: A method for forming an active area in a substrate includes the steps of growing an isolation oxide on a silicon substrate, providing a photresist mask to define the active areas on the substrate, performing etching and stripping processes, removing the residual oxide from the active areas and selectively growing an epitaxial silicon layer.

Abstract: A highly reliable semiconductor laser device having a low operating voltage is obtained by increasing adhesive force of the overall electrode layer to a nitride-based semiconductor layer without deteriorating a low contact property. This nitride-based semiconductor laser device comprises a nitride-based semiconductor layer formed on an active layer and an electrode layer formed on the nitride-based semiconductor layer, while the electrode layer includes a first electrode layer containing a material having strong adhesive force to the nitride-based semiconductor layer and a second electrode layer, formed on the first electrode layer, having weaker adhesive force to the nitride-based semiconductor layer than the first electrode layer for reducing contact resistance of the electrode layer with respect to the nitride-based semiconductor layer.

Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Abstract: A CMOSFET in which a p-type gate electrode and an n-type gate electrode are formed on a silicon substrate. The p-type gate electrode includes, in order, a p-type polycrystalline silicon layer and a tungsten silicide layer. The n-type gate electrode includes, in order, an n-type polycrystaline silicon layer and a tungsten silicide layer. A carbon-containing polycrystalline silicon layer, which is an impurity thermal diffusion prevention layer to suppress the interdiffusion of impurities, is provided between the p-type polycrystalline silicon layer and the tungsten silicide layer.

Abstract: A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body.

Abstract: The present invention provides a bump fabrication process. A wafer is provided with a patterned photoresist layer formed on the wafer. The patterned photoresist layer has a plurality of openings, corresponding to bonding pads. A conductive layer is formed on the photoresist layer and the exposed bonding pads. Afterwards, a sticker film is the provided to lift off the conductive layer on the photoresist layer, while the conductive layer within the openings is not removed. A solder paste is filled into the openings. A reflow step is performed to turn the filled solder paste into globular bumps. At last, the protoresist layer is removed.

Abstract: An interlayer insulation film (31) on a plug (11) is etched using a silicon nitride film (32) used in pattern etching of a bit line (12) as a hard mask such that the plug (11) projects into a groove (40). Another silicon nitride film (33) is provided to cover an exposed surface of the groove (40), the bit line (12) and the silicon nitride film (32), thereby forming another interlayer insulation film (34) on the silicon nitride film (33) to fill the groove (40). The silicon nitride films (33, 32) are used as an etching stopper to etch the interlayer insulation film (34) above the plug (11). The silicon nitride film (33) on the plug (11) is etched to expose the plug (11) into a recess.

Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: A method for forming a dual damascene line structure includes forming an inter-metal dielectric including a first region and a second region on a semiconductor substrate, forming a first hard mask material layer on an entire surface of the inter-metal dielectric, removing the first hard mask material layer on the first region, forming a second hard mask material layer on an entire surface of the inter-metal dielectric, forming a hard mask to remove a portion of the first hard mask material layer on the second region, etching the inter-metal dielectric of the first region to a first thickness using the hard mask, exposing the inter-metal dielectric of the second region, and etching the exposed inter-metal dielectric to simultaneously form a via hole and a trench having the via hole.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A method of forming a via-first type dual damascene structure in the absence of an etch stop layer and without via-edge erosion or via-bottom punch-through is described. The invention uses two organic films deposited within via hole prior to trench etching. A via hole over a lower level metal line is first etched in the dielectric film. Two, preferably organic, bottom anti-reflective coating (BARC) films, first one being the conformal type to coat the surfaces and the walls of the via and the second one being the planarizing type to at least partially fill the via, are then deposited. Using a mask aligned to via hole, a wiring trench of desired depth is etched in the top portion of the dielectric film. During trench etching, the conformal BARC-1 film protects the via-edges from eroding and the planarizing BARC-2 film prevents punch-through of the via-bottom. Desired metal such as aluminum or copper are deposited within said dual damascene pattern.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: A method for forming a gate silicide portion comprising the following steps. A substrate having a gate oxide layer formed is provided. A gate layer is formed over the gate oxide layer. An RPO layer is formed over the gate layer. A patterned photoresist layer is formed over the RPO layer exposing a portion of the RPO layer. The portion of the RPO layer having a patterned photoresist residue thereover. The structure is subjected to a dry plasma or gas treatment to clean the exposed portion of the RPO layer and removing the patterned photoresist residue. The RPO layer is etched using the patterned photoresist layer as a mask to expose a portion of the gate layer. The dry plasma or gas treatment preventing formation of defects or voids in the RPO layer and the poly gate layer during etching of the RPO layer. A metal layer is formed over at least the exposed portion of the gate layer.

Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Abstract: A method for forming silicide at source and drain. The method includes providing a semiconductor substrate having an active region and peripheral region, wherein gates with source and drain on two sides are formed in the peripheral region, conformally forming a barrier layer to cover the active region and the peripheral region, forming a mask layer to cover the barrier layer at the active region, removing the barrier layer from the peripheral region; removing the mask layer, forming a metal layer to cover the peripheral region, and subjecting the metal layer to thermal process such that silicon reacts with the metal to form silicide at the source and the drain.

Abstract: A thin nitrode film having a low resistance is formed at a low film-forming temperature. In the step of forming a thin nitride film of a high temperature-melting point metal by introducing a feedstock gas having the high temperature-melting point metal and a reductive nitrogen-containing gas having a nitrogen atom into a vacuum atmosphere; an auxiliary reductive gas free from nitrogen is also introduced. The high temperature-melting point metal deposited due to the auxiliary reductive gas compensates for the deficiency of the high temperature-melting point metal of the deposited nitride; and thus enable the growth of the thin nitride film having a low resistance.

Abstract: The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of copper oxide (105) over the deposited copper seed layer (110) by exposure to a substantially copper-free reducing agent solution (120), such that the copper oxide (105) is substantially converted to elemental copper, followed by electrochemical deposition of a second copper layer (125) over the copper seed layer (110). Such methods and resulting conductive structures thereof may be advantageously used in methods to make integrated circuits comprising interconnection metal lines.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Abstract: A method of relieving surface stress on a thin wafer by removing a small portion of the wafer substrate, the substrate being removed by applying a solution of KOH to the wafer while the wafer spins.

Abstract: A fabrication method of semiconductor device comprising a step of forming an electroconductive material film on a substrate, a step of polishing the electroconductive material film, and a step of washing a polished surface of the electroconductive material film, wherein the washing step is a step of carrying out ultrasonic washing with a washing solution to which an ultrasonic wave is applied, prior to physical washing.

Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

Abstract: The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.

Abstract: A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.

Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Abstract: A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.

Abstract: The present invention relates to etching for removing a carbon thin film formed on a surface of a sample, to prevent a damage on a sample and eliminate the necessity of providing a special device (such as vacuum pump) as is required in plasma etching. A sealed reaction chamber 100A in which a sample 500 formed with a carbon thin film 510 on its surface is to be set, a gas feed means 200A for feeding argon gas which is an inert gas Ar into which a predetermined proportion of oxygen gas O2 has been mixed from one end to the interior of the reaction chamber 100A, an exhaust means 300A for discharging carbon dioxide gas CO2 from the downstream side of the inert gas Ar fed from the gas feed means 200A, and a heating means 400A for heating the sample 500 to 550° C. or higher are provided.

Abstract: A plasma processing method that makes it possible to remove a photoresist film and fence portion while maintaining a specific shape of the opening is provided. After a wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of an ashing apparatus 100, power with its frequency set at 60 MHz and its level set at 1 kW and power with its frequency set at 2 MHz and its level set at 250 W are respectively applied to an upper electrode 122 and the lower electrode 106. A processing gas induced into the processing chamber 102 is raised to plasma, a photoresist film 208 at the wafer W is ashed and, at the same time, fence portion 214 formed around the opening of a via hole 210 during the etching process is removed. The level of the power applied to the lower electrode 106 is set equal to or lower than 10 W before the photoresist film 208 is completely removed.

Abstract: A method for making a radio frequency (RF) component includes forming a dielectric layer on a semiconductor substrate and forming and patterning a conductive layer on the dielectric layer to define the RF component. The dielectric layer may include SiN, the conductive layer may include aluminum, and the semiconductor substrate may include silicon, for example. At least one opening may be formed through the RF component at least to the semiconductor substrate. Moreover, the at least one opening may either extend into the semiconductor substrate or substantially terminate at a surface of the semiconductor substrate. The RF component may then be released from the semiconductor substrate by exposing the semiconductor substrate to an etchant passing through the at least one opening to the semiconductor substrate. Releasing the RF component may include exposing the semiconductor substrate to a dry etchant, such as XeF2, for example.

Abstract: A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast.

Abstract: By conducting etching treatment using at least two steps with different compositions of gases for each step, and at least one step comprising using a gas capable of decomposing and vaporizing etching products in an etching apparatus continuously, semicondictor devices can be produced with high productivity, low contaminant and good reproducibility of treatment state.

Abstract: A bi-layer resist process. A layer to be etched is provided on a substrate. The layer to be etched is coated with a bottom silicon-containing resist layer. The bottom silicon-containing resist layer is baked. The bottom silicon-containing resist layer is treated to form a silicon oxide layer on a surface of the bottom silicon-containing resist layer. The silicon oxide layer is coated with a top resist layer. The top resist layer is baked. The top resist layer is exposed to light and developed to form a pattern in the top resist layer. The pattern is transferred through the silicon oxide layer to the bottom resist layer.

Abstract: Removing photoresist from alignment marks on a semiconductor wafer using a wafer edge exposure process is disclosed. The alignment marks on the wafer are covered by photoresist used in conjunction with semiconductor processing of one or more layers deposited on the semiconductor wafer. One or more parts of the edge of the wafer are exposed to remove the photoresist from these parts and thus reveal alignment marks on the wafer. The exposure of the one or more parts of the wafer is accomplished without performing a photolithographic clear out process. Rather, a wafer edge exposure (WEE) process is inventively utilized. Once the WEE process is performed, subsequent layers may be deposited by aligning them using the revealed alignment marks.

Abstract: The invention includes reactive gaseous deposition precursor feed apparatus and chemical vapor deposition methods. In one implementation, a reactive gaseous deposition precursor feed apparatus includes a gas passageway having an inlet and an outlet. A variable volume accumulator reservoir is joined in fluid communication with the gas passageway. In one implementation, a chemical vapor deposition method includes positioning a semiconductor substrate within a deposition chamber. A first deposition precursor is fed to an inlet of a variable volume accumulator reservoir. With the first deposition precursor therein, volume of the variable volume accumulator reservoir is decreased effective to expel first deposition precursor therefrom into the chamber under conditions effective to deposit a layer on the substrate.

Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10 W to about 500 W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.

Abstract: Silicon alloys and doped silicon films are prepared by chemical vapor deposition and ion implantation processes using Si-containing chemical precursors as sources for Group III and Group V atoms. Preferred dopant precursors include (H3Si)3-xMRx, (H3Si)3N, and (H3Si)4N2, wherein R is H or D, x=0, 1 or 2, and M is selected from the group consisting of B, P, As, and Sb. Preferred deposition methods produce non-hydrogenated silicon alloy and doped Si-containing films, including crystalline films.

Abstract: A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

Abstract: A laser-assisted direct imprint process enables direct transfer of patterns on a contact mold to molten semiconductor material. During the pattern transfer, sonic energy may be applied to improve the efficacy of the pattern transfer.

Abstract: A heat-fusion bonding adhesive is prepared by heating a thermoplastic resin to a temperature of no less than the softening temperature of the resin and then dispersing the resin in the softened state in an aqueous medium. Dispersing the thermoplastic resin in the aqueous medium is conducted, for example, by applying a shear force to the aqueous medium by stirring. In this case, stirring of the aqueous medium is preferably conducted till the thermoplastic resin is divided into particles with a weight-average particle size of 0.1-20 &mgr;m.

Abstract: A composite sheet has a layer of reinforcing fiber impregnated with a thermoplastic resin. Non-woven fiber is partially impregnated with the thermoplastic resin to provide a bondable surface that can be subsequently bonded to other materials, such as plastics, foam and metal. Such an apparatus may be formed by heating and compressing the thermal plastic resin against the reinforcing fibers of the base layer and against the non-woven fibers, such that the base layer may be fully impregnated while the non-woven fibers may be partially impregnated. A thermal plastic resin must have a melting point less than either the reinforcing fibers of the base layer, or the non-woven fibers.

Abstract: Optical glasses and optical articles comprised of the optical glass are disclosed. One of which comprises, by means of weight percentages, more than 32 percent and not more than 45 percent P2O5, more than 0.5 percent and not more than 6 percent Li2O, more than 5 percent and not more than 22 percent Na2O, 6-30 percent Nb2O5, 0.5-10 percent B2O3, 0-35 percent WO3, 0-14 percent K2O, and 10-24 percent Na2O+K2O, and the total of all the above components is not less than 80 percent.