Patents Issued in July 1, 2004
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Publication number: 20040124416Abstract: A deposited dielectric (e.g., PECVD silicon nitride) formed on an inexpensive glass or plastic foil substrate is modified to facilitate the formation of high mobility organic semiconductor films. In one embodiment, the dielectric is plasma treated using nitrogen or argon gas to reduce the surface roughness of the dielectric layer below 5 nm (peak-to-valley). An organic semiconductor film (e.g., pentacene) grown on the modified dielectric exhibits high mobility and large polycrystalline grain sizes.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Dietmar P. Knipp, John E. Northrup, Robert A. Street
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Publication number: 20040124417Abstract: The present invention discloses a method of manufacturing an active matrix display device, comprising: a) forming a semiconductor layer on an insulating substrate; b) forming a gate insulating layer over the whole surface of the substrate while convering the semiconductor layer; c) forming a gate electrode on the gate insulating layer over the semiconductor layer; d) forming spacers on both side wall portions of the gate electrode while exposing both end portions of the semiconductor layer; e) ion-implaing a high-density impurity into the semiconductor layer to form high-density source and drain regions in the semiconductor layer; f) depositing sequentially a transparent conductive layer and a metal layer on the inter insulating layer; g) patterning the transparent conductive layer and the metal layer to form the source and drain electrodes, the source and drain electrodes directly contacting the high-density source and drain regions and having a dual-layered structure; h) forming a passivation layer over theType: ApplicationFiled: December 17, 2003Publication date: July 1, 2004Inventors: Woo Young So, Kyung Jin Yoo, Sang Il Park
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Publication number: 20040124418Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the source wires 126 of a pixel portion 205 are formed of material having low resistance (representatively, aluminum, silver, copper). The source wires of a driving circuit are formed in the same process as the gate wires 162 of the pixel portion and a pixel electrode 163.Type: ApplicationFiled: December 16, 2003Publication date: July 1, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Publication number: 20040124419Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.Type: ApplicationFiled: December 18, 2003Publication date: July 1, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporationInventors: Setsuo Nakajima, Ritsuko Kawasaki
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Publication number: 20040124420Abstract: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Simon S.H. Lin, Weng Chang, Syun-Ming Jang, Ms Liang
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Publication number: 20040124421Abstract: A light-emitting device that uses a light-emitting element which can be minimized its deterioration as a display element is provided. And also a light-emitting device which can control power consumption and enhance reliability by using the light-emitting element as a display element, and a manufacturing method thereof are provided. A light-emitting device in which the concentration of dopant is set in the range of no fewer than 0.001%, nor more than 0.35% by weight, a photosensitive organic resin film having an anode and an opening is disposed on a first passivation film, an anode, a cathode, and a light-emitting layer are overlapped in the opening, and the organic resin film and the cathode are covered with a second passivation film.Type: ApplicationFiled: September 18, 2003Publication date: July 1, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisao Ikeda, Makoto Udagawa, Ryoji Nomura
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Publication number: 20040124422Abstract: The present invention provide a light-emitting diode capable of making its light emission more uniform without too high a concentration current and of improving efficiency of light outgoing and its life. In the light-emitting diode, the n-side electrode has an n-side connecting portion and an n-side extending portion, which extends in the longitudinal direction from a predetermined part of the n-side connecting portion, and the p-side pad member has at least p-side connecting portion to be connected to a conductive member.Type: ApplicationFiled: October 1, 2003Publication date: July 1, 2004Inventors: Takahiko Sakamoto, Takeshi Kususe
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Publication number: 20040124423Abstract: A method of fabricating an active matrix organic light emitting diode display is described. A substrate having a light-emitting region and a non-light-emitting region thereon is provided, and pixel structures have been formed in the light-emitting region. A driving IC is formed on the substrate in the non-emitting region and electrically coupled with the pixel structures. A packaging cap is disposed over the substrate and adhered to the substrate. The packaging cap covers the emitting region of the substrate and the driving IC remains being exposed. Since the driving IC is exposed from the packaging cap, the driving IC can be tested or repaired directly when the driving IC is abnormal.Type: ApplicationFiled: November 20, 2003Publication date: July 1, 2004Inventors: Jiin-Jou Lih, Chih-Feng Sung
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Publication number: 20040124424Abstract: A monolithic multiple-wavelength laser device includes a laser section of a first wavelength and a laser section of a second wavelength formed on a single GaAs substrate, wherein the laser section f the first wavelength includes a real guide structure, and the laser section of the second wavelength includes a loss guide structure. In such a multiple-wavelength laser device, loss in wave guiding can be reduced and operating current can be decreased, compared to a conventional device, when the first wavelength is within a wavelength band of about 780 nm and the second wavelength is within a wavelength band of about 650 nm, since the laser section of the first wavelength has the real guide structure.Type: ApplicationFiled: December 11, 2003Publication date: July 1, 2004Applicant: SHARP KABUSHIKI KAISHAInventor: Masaki Tatsumi
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Publication number: 20040124425Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.Type: ApplicationFiled: December 16, 2003Publication date: July 1, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroko Yamazaki, Atsushi Tokuda, Tetsuo Tsutsui
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Publication number: 20040124426Abstract: Provided is an envelope which includes: a first substrate; a second substrate opposed to the first substrate; a frame interposed between the first substrate and the second substrate; and a low melting point metal for bonding the first substrate and the frame to each other. In particular, in such a configuration, the substrate or the frame has a first region and a second region which are brought into contact with the low melting point metal, and in the first region, a material capable of higher maintaining airtightness with the low melting point metal than the second region is in contact with the low melting point metal, while in the second region, a material having a stronger binding power on the low melting point metal than the first region is in contact with the low melting point metal.Type: ApplicationFiled: August 26, 2003Publication date: July 1, 2004Applicant: CANON KABUSHIKI KAISHAInventors: Mitsutoshi Hasegawa, Masaki Tokioka, Tokutaka Miura
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Publication number: 20040124427Abstract: An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.Type: ApplicationFiled: December 12, 2003Publication date: July 1, 2004Inventors: Julia Wan-Ping Hsu, Michael James Manfra, Nils Guenter Weimann
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Publication number: 20040124428Abstract: A high reflective and conductive metal substrate instead of a GaAs substrate which is a light absorption substrate is utilized for the light emitting diode. The processes include forming a mirror protection film on the light emitting epi-layers. The mounting between the reflective and conductive metal substrate on the protection film is though a metal adhesive layer. Afterward, the temporal GaAs substrate is removed. Thereafter, a trench is formed to remove a portion of light emitting epi-layers to expose a p-type ohmic contact epi-layer and the first ohmic contact metal electrode of the light emitting epi-layers. Then the second ohmic contact metal electrode and a wire bonding layer formation are followed. The LED can enhance capability of the light reflect instead of light absorption.Type: ApplicationFiled: May 13, 2003Publication date: July 1, 2004Applicant: United Epitaxy Co., Ltd.Inventors: Jin-Ywan Lin, Huan-Pin Huang, Chung-Cheng Tu
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Publication number: 20040124429Abstract: A light emitting device comprised of a light emitting diode on a mounting surface, the light emitting diode includes a substrate layer and at least one active region. A resilient substantially transparent and substantially phosphor free polymer layer extends from the mounting surface to above at least one quarter of a height of the substrate layer but below a top surface of the light emitting diode. A second phosphor containing layer extends from the phosphor free polymer layer to above the top surface of the light emitting diode.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Edward Stokes, Donald Buckley, Thomas McNulty, Daniel Doxsee
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Publication number: 20040124430Abstract: An LED lamp includes at least one LED chip having an emission peak wavelength of 400 nm to 490 nm, and a wavelength converting portion including a phosphor for transforming the emission of the LED chip into light having a longer wavelength than that of the emission. The LED lamp further includes a filtering member, of which the spectral transmittance is adjusted so as to minimize color shifting even if the amount of current supplied to the LED chip to make the LED chip produce the emission has changed.Type: ApplicationFiled: November 24, 2003Publication date: July 1, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tadashi Yano, Masanori Shimizu, Nobuyuki Matsui, Tatsumi Setomoto, Tetsushi Tamura
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Publication number: 20040124431Abstract: A method of fabricating a dense pixel array comprising the steps of: (a) printing a photoresist mask and applying said mask to a semiconductor material substrate to form a masked area and an unmasked area on said substrate; (b) applying a photoresist material layer to the unmasked area of the substrate, then applying a metal layer over the photoresist material layer and the substrate, and then applying a solvent to remove the photoresist material layer and said metal layer applied over said photoresist material layer to leave a plurality of metal layers superimposed over the unmasked area of the substrate; (c) removing the substrate to a depressed substrate surface between the metal layers formed in step (b) to form a plurality of pixels each having an upper metal layer; (d) superimposing an insulative layer over each of the metal layers formed in step (c); (e) forming a hole in at least one of the insulative layers formed in step (d) so as to expose the metal layer under the insulative layer; and (f) superimType: ApplicationFiled: December 12, 2003Publication date: July 1, 2004Inventor: Lawrence F. DePaulis
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Publication number: 20040124432Abstract: A method of manufacturing an organic light-emitting device having reduced ambient-light reflection is disclosed. The method comprises the following steps. First, a metal reflective layer is formed on a provided substrate. Then a transparent anode, an organic layer, a translucent electron-injecting cathode, a buffer layer and a transparent electrode are sequentially deposited on the metal reflective layer. In order to reduce the affect of the ambient-light reflection, adjusting the thickness of the aforementioned layers that the reflected lights generate destructive optical interference and improve the visually perceived contrast of the emitted light.Type: ApplicationFiled: April 22, 2003Publication date: July 1, 2004Applicant: AU Optronics Corp.Inventor: Chung-Wen Ko
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Publication number: 20040124433Abstract: The present invention comprises a process of mixing a luminous substance in powder form to a transferable grade molding compound in a pelletized or powder form, such as a clear epoxy, to derive a homogeneous mixture that can be pressed and sintered into solid pellets. The solid pellets are further processed so as to permit their deposition on and around a light emitting semiconductor driver so as to obtain a white light emitting semiconductor device. This white light emitting device can be used in a variety of lighting applications.Type: ApplicationFiled: July 18, 2003Publication date: July 1, 2004Inventor: Stephen G. Kelly
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Publication number: 20040124434Abstract: There is provided a GaN single crystal at least about 2 millimeters in diameter, with a dislocation density less than about 104 cm−1, and having no tilt boundaries. A method of forming a GaN single crystal is also disclosed. The method includes providing a nucleation center, a GaN source material, and a GaN solvent in a chamber. The chamber is pressurized. First and second temperature distributions are generated in the chamber such that the solvent is supersaturated in the nucleation region of the chamber. The first and second temperature distributions have different temperature gradients within the chamber.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Applicant: GENERAL ELECTRIC COMPANYInventors: Mark Phillip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Peter Micah Sandvik
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Publication number: 20040124435Abstract: There is provided an electronic device. The electronic device includes at least one epitaxial semiconductor layer disposed on a single crystal substrate comprised of gallium nitride having a dislocation density less than about 105 per cm2. A method of forming an electronic device is also provided. The method includes providing a single crystal substrate comprised of gallium nitride having a dislocation density less than about 105 per cm2, and homoepitaxially forming at least one semiconductor layer on the substrate.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Applicant: GENERAL ELECTRIC COMPANYInventors: Mark Phillip D'Evelyn, Nicole Andrea Evers, An-Ping Zhang, Jesse Berkley Tucker, Jeffrey Bernard Fedison
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Publication number: 20040124436Abstract: An epitaxial layer structure that achieves reliable, high speed, and low noise device performance in indium phosphide (InP) based heterojunction bipolar transistors (HBTs) for high data rate receivers and optoelectronic integrated circuits (OEIC). The layer consists of an n+InGaAs subcollector, an n+InP subcollector, an unintentionally doped InGaAs collector, a carbon-doped base, an n-type InP emitter, an n-type InGaAs etch-stop layer, an n-type InP emitter, and an InGaAs cap layer.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Milton Feng, Shyh-Chiang Shen, David C. Caruth
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Publication number: 20040124437Abstract: A self-identifying integrated circuit contains a primary function circuit and an immutable, unique identification code, which is presented at an output port thereof upon demand by, an external circuit. The unique identification code may be an N bit digital number or may be a response signal to an interrogating excitation signal. The circuitry to store the unique identification code is fabricated on a microscopic scale such as by a direct-write laser forward transfer of material process or by a laser ablation of select material process. The identification storage means may be disposed on a package substrate or on an integrated circuit die and is permanently encased within the integrated circuit package so as to be protected from alteration by external means.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventor: Nicholas Doudoumopolous
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Publication number: 20040124438Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.Type: ApplicationFiled: May 22, 2003Publication date: July 1, 2004Inventors: Shyama Mukherjee, Joseph Levert, Donald BeBear
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Publication number: 20040124439Abstract: A hollow region is formed in a silicon substrate. A plurality of openings formed in the silicon layer on the hollow region is filled with a buried film. The bottom portion of the hollow region is formed with a plurality of silicon pillars, which support the silicon layer.Type: ApplicationFiled: September 4, 2003Publication date: July 1, 2004Inventors: Yoshihiro Minami, Takashi Yamada, Yusuke Kohyama, Tsutomu Sato, Hajime Nagano
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Publication number: 20040124440Abstract: A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.Type: ApplicationFiled: November 6, 2003Publication date: July 1, 2004Inventors: Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata, Shinichi Miyatake, Hiromasa Noda, Kazuhiko Kajigaya
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Publication number: 20040124441Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.Type: ApplicationFiled: December 11, 2003Publication date: July 1, 2004Inventors: John T. Moore, Scott Jeffrey DeBoer, Mark Fischer, J. Brett Rolfson, Annette L. Martin, Ardavan Niroomand
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Publication number: 20040124442Abstract: In an active matrix display device using an SRAM, the number of transistors configuring the SRAM circuit is large. Therefore, the transistors cannot be embedded in a pixel when a pixel area is small, otherwise an aperture ratio is reduced. In view of the foregoing, it is an object of the present invention to provide a display device without a refreshing operation and thus with small power consumption. According to the invention, a display device including a pixel which comprises a switching element and a nonvolatile memory element is provided. When a still image is displayed by utilizing a ferroelectric element as a nonvolatile memory element and storing a signal, writing is not required per frame. Further, as the ferroelectric element occupies a small area, a memory circuit can be incorporated without decreasing an aperture ratio.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Jun Koyama
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Publication number: 20040124443Abstract: A method for efficiently manufacturing a semiconductor device, the semiconductor device having an FET and a pn junction diode provided on the same semiconductor substrate, the FET having a Schottky junction for a gate electrode and a gate recess, includes the steps of forming a channel layer, a first etching stopper layer, an n-type common layer, a second etching stopper layer, a p-type layer, and a third etching stopper layer on the semiconductor substrate in that order; etching away the p-type layer and the third etching stopper layer in specific regions; simultaneously forming a source electrode, a drain electrode, a cathode; forming a mask having an opening for forming a gate recess and a gate electrode and an opening for forming an anode; forming the gate recess by etching while the third etching stopper layer prevents the p-type layer from being etched; and simultaneously forming the gate electrode and the anode.Type: ApplicationFiled: December 16, 2003Publication date: July 1, 2004Applicant: Murata Manufacturing Co., Ltd.Inventor: Kazuhiro Yoshida
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Publication number: 20040124444Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).Type: ApplicationFiled: May 21, 2003Publication date: July 1, 2004Inventors: Amol M. Kalburge, Kevin Q. Yin
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Publication number: 20040124445Abstract: A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer.Type: ApplicationFiled: November 17, 2003Publication date: July 1, 2004Inventors: Masanobu Ogino, Yoshikatsu Suto, Yoshiro Baba
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Publication number: 20040124446Abstract: A series of conductive layers separated by interlayer gaps is formed adjacent a substrate layer, the conductive layer and interlayer gap dimensions defining aspect ratios for trenches between the conductive layers. A layer of dielectric material is deposited over the conductive layers using plasma enhanced chemical vapor deposition. Trenches having aspect ratios within specified geometric categories are incompletely filled, leaving interlayer voids which may have desirable dielectric properties.Type: ApplicationFiled: December 28, 2002Publication date: July 1, 2004Inventors: Wilmer F. Borger, Jeffrey T. West, Ebrahim Andideh
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Publication number: 20040124447Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.Type: ApplicationFiled: July 23, 2003Publication date: July 1, 2004Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Publication number: 20040124448Abstract: An integrated power supply circuitry that supplies power in an integrated circuit to a chip may provide protection against transistor junction breakdowns from a supply voltage. For example, in a nonvolatile memory, such as a flash memory, a transistor PN-junction breakdown (e.g., a gate-aided drain-substrate PN-junction breakdown (BVD)) of metal silicon oxide (MOS) transistors may be prevented even though the supply voltage exceeds the BVD voltage limit thereof.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventor: Mase J. Taub
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Publication number: 20040124449Abstract: A MOSFET and the method for fabricating them are disclosed to make the inkjet head chips. The MOSFET has the scaled-down junction formation for the source and drain. Using a lower temperature process and interlayer dielectric, the source and drain dopants can not be diffused deeply due to high-temperature driver-in. The contact holes of the drain are provided with plugs of refractory material to avoid spiking between the metal and silicon. This achieves the requirement of high-density devices on the print head chip.Type: ApplicationFiled: July 28, 2003Publication date: July 1, 2004Inventors: Chien-Hung Liu, Jian-Chiun Liou, Chun-Jung Chen, Je-Ping Hu
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Publication number: 20040124450Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: December 16, 2003Publication date: July 1, 2004Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
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Publication number: 20040124451Abstract: A thin film transistor array substrate and a method for manufacturing the same is disclosed, in which it is possible to prevent mobile ions contained in a substrate from penetrating into a semiconductor layer by the gettering effect or neutralization in case soda lime glass is used for the substrate. The method includes forming a buffer layer on a substrate; doping impurity ions in the buffer layer; and forming a pixel electrode and a thin film transistor including a semiconductor layer on the buffer layer.Type: ApplicationFiled: June 17, 2003Publication date: July 1, 2004Inventors: Jae Young Oh, Seung Hee Nam
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Publication number: 20040124452Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Uwe Wellhausen, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, JingYu Lian, Nicolas Nagel
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Publication number: 20040124453Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.Type: ApplicationFiled: July 8, 2003Publication date: July 1, 2004Inventors: Nam-Kyeong Kim, Soon-Yong Kweon, Seung-Jin Yeom
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Publication number: 20040124454Abstract: The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.Type: ApplicationFiled: July 18, 2003Publication date: July 1, 2004Inventors: Eun-Seok Choi, Seung-Jin Yeom
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Publication number: 20040124455Abstract: A ferroelectric memory device includes a lower interlayer dielectric on a semiconductor substrate, a plurality of ferroelectric capacitors, and a plate line. The ferroelectric capacitors are on the lower interlayer dielectric. The plate line extends across and electrically connects to surfaces of at least two adjacent ones of the plurality of ferroelectric capacitors.Type: ApplicationFiled: July 22, 2003Publication date: July 1, 2004Inventors: Kyu-Mann Lee, Sang-Don Nam, Kun-Sang Park
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Publication number: 20040124456Abstract: An MRAM cell and a method of forming the an MRAM cell minimizes the occurrence of electrical shorts along the side walls of the stacked cell structure during fabrication. Specifically, a first conductor is provided in a trench in an insulating layer, and then an upper surface of the insulating layer and the first conductor are planarized. Next, as the layers forming the stacks of the MRAM cells are deposited on the planarized insulating layer and first conductor, the critical layers are physically separated from adjacent layers at regions surrounding an interior region of the stacked layers. The stacked layers at the interior region form an MRAM cell, while the separated edges prevent conductive layers from being formed along the sidewalls of the MRAM cell due to sputtering during the etching process(es) performed to define the cell.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Inventor: Paul A. Morgan
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Publication number: 20040124457Abstract: A memory cell part of a semiconductor substrate is formed with a cylindrical capacitor opening extending perpendicularly to the main surface of the semiconductor substrate. The cylindrical capacitor opening passes through a silicon oxide film, a silicon nitride film and another silicon oxide film in this order. A capacitor lower electrode, a dielectric film and a capacitor upper electrode are formed in the cylindrical capacitor opening along the surface of the cylindrical capacitor opening. The bottom surface of the cylindrical capacitor opening is formed below the main surface of silicon nitride film. Thus obtained is a semiconductor device capable of improving refreshability and soft error resistance.Type: ApplicationFiled: April 30, 2003Publication date: July 1, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Shunji Kubo
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Publication number: 20040124458Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventor: Chandrasekharan Kothandaraman
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Publication number: 20040124459Abstract: The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material.Type: ApplicationFiled: April 17, 2003Publication date: July 1, 2004Inventors: Yoshitaka Sasago, Takashi Kobayashi
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Publication number: 20040124460Abstract: The present invention is related to a stack gate electrode capable of suppressing a formation of a non-uniform silicide layer at an interface between a polysilicon layer and a metal layer during a selective oxidation process and a thermal process both being performed after a gate patterning process and a method for fabricating a semiconductor device including the same. The stack gate electrode includes: a silicon layer; a reaction prevention layer formed on the silicon layer, wherein the reaction prevention layer containing nitrogen and silicon has a surface density of nitrogen above about 1×1015/cm2; and a metal layer formed on the reaction prevention layer.Type: ApplicationFiled: July 10, 2003Publication date: July 1, 2004Inventors: Kwan-Yong Lim, Heung-Jae Cho, Jung-Ho Lee
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Publication number: 20040124461Abstract: The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a).Type: ApplicationFiled: December 11, 2003Publication date: July 1, 2004Inventor: Mark A. Gajda
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Publication number: 20040124462Abstract: A lateral RF MOS transistor with at least one conductive plug structure comprising: (1) a semiconductor material of a first conductivity type having a first dopant concentration and a top surface; (2) a conductive gate overlying and insulated from the top surface of the semiconductor material; (3) at least two enhanced drain drift regions of the second conductivity type of the RF MOS transistor; the first region laying partially underneath the gate; the second enhanced drain drift region contacting the first enhanced drain drift region, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region; (4) a drain region of the second conductivity type contacting the second enhanced drain drift region; (5) a body region of said RF MOS transistor of the first conductivity type with the dopant concentration being at least equal to the dopant concentration of the semiconductor epi layer; (6) a source region of the second conductiviType: ApplicationFiled: February 8, 2003Publication date: July 1, 2004Applicant: SIRENZA MICRODEVICES, INC.Inventors: Pablo D'Anna, Alan Lai-Wai Yan
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Publication number: 20040124463Abstract: To provide a semiconductor integrated circuit device with a reduced noise at a low cost in a semiconductor integrated circuit composed of an MOSFET and adapted to operate, in particular, through DC drive or low-frequency drive. The semiconductor integrated circuit device is configured, in which a surface channel P-type MOSFET (101) and a buried channel N-type MOSFET (100) constitute a complementary MOS transistor with a P+ type gate electrode.Type: ApplicationFiled: June 30, 2003Publication date: July 1, 2004Inventors: Hirofumi Harada, Jun Osanai
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Publication number: 20040124464Abstract: A first insulator (710) having an opening within a central region (551) is formed on a main surface (61S) of an epitaxial layer (610). Then, p-type impurities are ion implanted through the opening of the first insulator (710) and then heat treatment is carried out, thereby to form a p base layer (621) in the main surface (61S). An insulating film is formed to fill in the opening and then etched back, thereby to form a second insulator (720) on a side surface (71W) of the first insulator (710). Under conditions where the second insulator (720) is present, n-type impurities are ion implanted through the opening and then heat treatment is carried out, thereby to form an n+ source layer (630) in the main surface (61S) of the p base layer (621).Type: ApplicationFiled: May 14, 2003Publication date: July 1, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Atsushi Narazaki
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Publication number: 20040124465Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: ApplicationFiled: December 12, 2003Publication date: July 1, 2004Applicant: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka