Abstract: A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer.

Abstract: Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.

Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the semiconductor layer includes a minute protruding portion, and the side surface inclination angle of the gate electrode is larger than the inclination angle of the protruding portion of the semiconductor layer.

Abstract: A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, a field effect transistor formed in the well region, and a diffused region, formed across the well region and the substrate for applying back gate potential to the well region, and forming a PN junction together with its periphery. The field effect transistor and the PN junction are connected between terminals for absorbing excess current so that an internal circuit connected to the terminals is protected.

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: At least two switching devices each including a substrate formed of a wide bandgap semiconductor, source and gate electrodes formed in a principal surface side of the substrate, and a drain electrode formed on the back surface of the substrate are stacked so that respective upper surface sides of the switching face each other.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of the gate electrode, wherein the gate electrode is made of SiGe, the sidewall insulating film is an insulating film obtained by oxidizing the sidewall surface of the gate electrode, and the sidewall insulating film contains silicon oxide as a main component.

Abstract: A semiconductor integrated circuit device having a capacitor element including a lower electrode provided over an element isolation region of a principal surface of a semiconductor substrate, and an upper electrode provided over the lower electrode via a dielectric film interposed therebetween, has oxidation resistant films between the element isolation region of the principal surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.

Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Abstract: This specification relates to a process for manufacturing a semiconductor device, comprising the steps of: forming a lower gate electrode film on a semiconductor substrate 10 via a gate insulating film 11; forming an upper gate electrode film on the lower gate electrode film, the upper gate electrode film being made of a material having a lower oxidation rate than that of the lower gate electrode film; forming a gate electrode 12 by patterning the upper gate electrode film and the lower gate electrode film, the gate electrode 12 comprising a lower gate electrode element 12a and an upper gate electrode element 12b; forming source/drain regions 15 by introducing an impurity into the semiconductor substrate 10; and forming oxide film sidewalls 13 by oxidizing the side faces of the lower gate electrode element 12a and the upper gate electrode element 12b, the thickness of the oxide film sidewalls 13 in the gate length direction being larger at the sides of the lower gate electrode element 12a than at the sides of

Abstract: A thin film transistor including a lightly doped drain (LDD) region or offset region, wherein the thin film transistor is formed so that primary crystal grain boundaries of a polysilicon substrate are not positioned in the LDD or offset region.

Abstract: A method for releasing from underlying substrate material micromachined structures or devices without application of chemically aggressive substances or excessive forces. The method starts with the step of providing a partially formed device, comprising a substrate layer, a sacrificial layer deposited on the substrate, and a function layer deposited on the sacrificial layer and possibly exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Next there are the steps of cleaning residues from the surface of the device, and then directing high-temperature hydrogen gas over the exposed surfaces of the sacrificial layer to convert the silicon dioxide to a gas, which is carried away from the device by the hydrogen gas.

Abstract: In a piezoelectric element having a piezoelectric film sandwiched between a lower electrode and an upper electrode, the lower electrode and/or the upper electrode and the piezoelectric film comprise perovskite oxide and a contact interface between the lower electrode and/or the upper electrode and the piezoelectric film does not exist and a region where crystals of the lower electrode and/or the upper electrode and crystals of the piezoelectric film are mixed exists between the lower electrode and/or the upper electrode and the piezoelectric film.

Abstract: A method for adjusting with high precision the width of gaps between micromachined structures or devices in an epitaxial reactor environment. Providing a partially formed micromechanical device, comprising a substrate layer, a sacrificial layer including silicon dioxide deposited or grown on the substrate and etched to create desired holes and/or trenches through to the substrate layer, and a function layer deposited on the sacrificial layer and the exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Cleaning residues from the surface of the device, then epitaxially depositing a layer of gap narrowing material selectively on the surfaces of the device. The selection of deposition surfaces determined by choice of materials and the temperature and pressure of the epitaxy carrier gas.

Abstract: A spin-tunnel transistor having a tunnel barrier layer formed of an antiferromagnetic material which is exchange coupled with a first or second ferromagnetic metal layer of a base B formed adjoining to the antiferromagnetic material, so as to fix magnetization of the adjoining ferromagnetic layer. The base B includes a nonmagnetic metal layer which is formed between the first and second ferromagnetic metal layers and decouple magnetization coupling between the first and second ferromagnetic metal layers. The base B is formed between a collector and an emitter to form tri-terminal device. Those spin-tunnel transistor may be used as a sensor of a magnetic reproducing head used in a hard disk drive.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: The present invention discloses an image sensor die that has structures intended to more efficiently package the image sensor die. The structures include a spacer ring and stack bumps. The spacer ring serves to support a glass lid over the pixel array of the image sensor die. The stack bumps are raised in order to facilitate direct connection to flexible tape or a printed circuit board.

Abstract: A light emitting die package and a method of making the light emitting die package are disclosed. The die package includes a stem substrate having grooves, a wire lead attached to the grooves, and a light emitting diode (LED) mounted on the stem substrate. Also coupled to the substrate are a sleeve, a reflector, and a lens. To make the light emitting die package, a long substrate is formed and wire leads attached to the substrate. Then, the substrate including the attached wire leads is cut to predetermine lengths to form individual stem substrates. To each stem substrate, LED, reflector, and lens are coupled.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: A power semiconductor device includes a substrate having an upper surface and a lower surface. The substrate has a trench. First and second doped regions are provided proximate the upper surface of the substrate. A first source region is provided within the first doped region. A second source region is provided within the second doped region. A gate is provided between the first and second source regions. The gate includes a first portion extending downward into the trench. A depth of the trench is no more than a depth of the first doped region.

Abstract: The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pad oxide layer over the thin silicon body layer; forming a silicon nitride layer over the pad oxide layer; forming a photoresist over the silicon nitride layer; forming an opening in the photoresist; removing the silicon nitride layer in the opening; partially or completely removing the pad oxide layer in the opening; removing the photoresist over the silicon nitride layer; forming a field oxide layer from the thin silicon body layer in the opening; removing the silicon nitride layer over the pad oxide layer; and removing the pad oxide layer over the thin silicon body layer.

Abstract: A high impurity concentration region (31) that an impurity concentration is higher than that of a center part of a channel region (24) is placed in parts which intersect a Y direction in a side surface (14T) of an active region (14). Furthermore, a low impurity concentration region (32) that an impurity concentration is lower than that of the high impurity concentration region (31) is placed in parts which intersect an X direction in the side surface (14T). A source/drain region (231) overlaps with the low impurity concentration region (32), and in that overlapped part, the formation of a high concentration PN junction is suppressed.

Abstract: A semiconductor device comprising a semiconductor substrate having a recess whose depth is not more than 6 nm, a source region and a drain region which are formed in a surface region of the semiconductor substrate so as to sandwich the recess, each of the source region and the drain region being constituted of an extension region and a contact junction region, a gate insulating film formed between the source region and the drain region in the semiconductor substrate, and a gate electrode formed on the gate insulating film.

Abstract: Upper, inner and lower sections (182, 180 and 184) of a PCB (100) are formed with each section having a substrate (140, 150 and 160) having patterned layers of metallization (105 and 110, 115 and 120, and 125 and 130), respectively Some of the patterned layers of metallization (110, 115, 120, and 125) have thicker portions(171, 173) and part (188) of portion(186), and thinner portions(172, 174, 187, 190, 191, 192 and 193). The resultant thinner portion(175 and 194)in the prepreg layers (145 and 155) with the respective thicker portions of metallization provide decoupling capacitors, while the resultant thicker portions (196 and 198), for example, provide a lower capacitance for improved trace impedance for the signal traces (191 and 192).

Abstract: A process for forming trenches with an oblique profile and rounded top corners, including the steps of: in a semiconductor wafer, through a first polymerizing etch, forming depressions delimited by rounded top corners; and through a second polymerizing etch, opening trenches at the depressions. The second polymerizing etch is made in variable plasma conditions, so that the trenches have oblique walls with a constant slope.

Abstract: A method for implementing a bismaleimide (BMI) polymer as a sacrificial material for an integrated circuit air gap dielectric. The method of one embodiment comprises forming a first and second metal interconnect lines on a substrate, wherein at least a portion of the first and second metal interconnect lines extend parallel to one another and wherein a trough is located between the parallel portion of said first and second metal interconnect lines. A layer of bismaleimide is spin coated over the substrate. The layer of bismaleimide is polished with a chemical mechanical polish, wherein the trough remains filled with the bismaleimide. A diffusion layer is formed over the substrate. The substrate is heated to activate a pyrolysis of the bismaleimide. An air gap is formed in the trough in the space vacated by the bismaleimide.

Abstract: Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

Abstract: A micro electromechanical switchable capacitor is disclosed, comprising a substrate, a bottom electrode, a dielectric layer deposited on at least part of said bottom electrode, a conductive floating electrode deposited on at least part of said dielectric layer, an armature positioned proximate to the floating electrode and a first actuation area in order to stabilize the down state position of the armature. The device may furthermore comprise a second actuation area. The present invention provides shunt switches and series switches with actuation in zones attached to the floating electrode area or with relay actuation.

Abstract: A charge pump circuit includes MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a multiplicity of first electrodes formed in one region of the substrate, insulating layers formed on/above respective substrate regions between neighboring first electrodes, each layer covering at least the respective substrate region, and a multiplicity of second electrodes formed on/above the respective insulating layers. The MOS capacitors have improved frequency response.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: In a gallium nitride semiconductor device comprising an active layer made of an n-type gallium nitride semiconductor that includes In and is doped with n-type impurity and a p-type cladding layer made of a p-type gallium nitride semiconductor that includes Al and is doped with p-type impurity,

Abstract: A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a second thickness. The method includes forming one or more via structures through a portion of the second thickness of compound semiconductor material to a portion of the underlying metal substrate, whereupon the via structure electrically connects to the metal substrate.

Abstract: A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract: Compositions are provided comprising aqueous dispersions of electrically conducting organic polymers and a plurality of nanoparticles. Films cast from invention compositions are useful as buffer layers in electroluminescent devices, such as organic light emitting diodes (OLEDs) and electrodes for thin film field effect transistors. Buffer layers containing nanoparticles have a much lower conductivity than buffer layers without nanoparticles. In addition, when incorporated into an electroluminescent (EL) device, buffer layers according to the invention contribute to higher stress life of the EL device.

Abstract: Methods for manufacturing a semiconductor device package (10) with a leadframe (14) to plastic (12) mold lock are disclosed along with the associated package (10). A method of the invention discloses manufacturing a packaged semiconductor device (10) using steps for forming a leadframe (14) with at least one borehole (20). The borehole (20) region of the leadframe (14) is coined such that a lip (34) is formed at the junction of the borehole (20) and a leadframe (14) surface. Encapsulating the lip (34) with mold compound (12) forms a leadframe (14) to plastic (12) lock incorporated in the completed semiconductor device package (10).

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract: A contact structure and production method provides an easy and simple way of assembling the contact structure. The contact structure includes a contact substrate for mounting a plurality of contactors in through holes formed thereon, a seed layer formed on a bottom surface of the contact substrate in a manner to cover the through hole, and a solder pad formed on a bottom surface of the seed layer. Under temperature higher than a reflow point of the solder pad, the contactor is inserted into the through hole so that a lower end of the contactor pierces the seed layer and reaches the solder pad, thereby bonding the contactor to the contact substrate.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: Method and structure for vertically stacking microelectronic devices are disclosed. Subsequent to appropriate deposition, patterning, trenching, and passivation subprocesses, a conductive layer is formed wherein one end comprises an external contact portion for C4 interfacing, and another end establishes electrical contact with an internal contact at the bonding interface between the two interfaced devices. The conductive layer may be formed using electroplating, and may be formed in a single electroplating treatment, to form a continuous structure from via portion to external contact portion.

Abstract: According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.

Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.

Abstract: A thermal enhance MCM package mainly comprises a first chip, a second chip, a substrate and a thermally conductive device. The first chip and the second chip are electrically connected to the substrate, and the thermally conductive device is mounted on the substrate. The thermally conductive device is exposed to the outside so as to prevent the heat generated from the first chip and the second chip from being accumulated in the substrate and transmitted to the motherboard. Accordingly, the thermal performance of the MCM package will be upgraded.

Abstract: The invention discloses a high-density multi-chip module package which can integrates active and passive devices stacked by a three-dimensional face-to-back interconnection. The multichip module package of the invention at least comprises a multichip module substrate which has an semiconductor substrate, an insulating layer on the semiconductor substrate, a multilayer interconnection structure on the insulating layer, and a plurality of conductive plugs penetrating the semiconductor substrate and the insulating layer to provide electric connection with the multilayer interconnection structure; and a plurality of chips disposing on the semiconductor substrate and electrically connecting to the multilayer interconnection structure through the conductive plugs.

Abstract: A surface mount chip package comprises a package housing made of a prescribed resin, which is formed to cover a semiconductor chip while avoiding a plurality of conductors extending from the semiconductor chip. A plurality of solder balls are arranged in the package housing in correspondence with a main surface of the semiconductor chip having an integrated circuit and are interconnected with the conductors respectively. An index serving as a marking member is arranged together with the solder balls so as to bring a directivity realized by the shape thereof when viewed in the thickness direction of the semiconductor chip. This allows a user to easily recognize the inclination and position of the package housing without using the solder balls in view of the index, thus establishing a prescribed positioning for an electrical test such as a probing test.

Abstract: The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a top surface and a bottom surface facing the substrate. A molding compound is formed to cover the semiconductor chip, the substrate, the top surface and the bottom surface of the stiffener. Afterwards, a singulation step is performed to cut the molding compound, the substrate and the stiffener.