Abstract: A method of fabricating a liquid crystal display device is disclosed in the present invention. The method includes forming a thin film transistor in a pixel region and a pad on an edge region of a first substrate, depositing an organic passivation layer over the first substrate, and removing the organic passivation layer in the edge region using a diffraction mask to expose a portion of the pad, wherein the diffraction mask has a slit portion including a plurality of slits having different widths.

Abstract: A method of manufacturing a liquid crystal display device includes steps of forming a gate line, a gate pad and a gate electrode on a first substrate through a first mask process, forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the first substrate including the gate line, the gate pad and the gate electrode through a second mask process, forming a pixel electrode and a data pad terminal on the first substrate including the data line, the data pad, the source electrode and the drain electrode through a third mask process, forming a passivation layer on an entire surface of the first substrate including the pixel electrode and the data pad terminal, attaching the first substrate including the passivation layer with a second substrate, wherein a gate pad portion including the gate pad and a data pad portion including the data pad are exposed by the second substrate, providing a liquid crystal material into a gap between the first and second substrates, and removing t

Abstract: A light emitting layer 4 composed of a single or a plurality of semiconductor layers is laminated on a nondope type, weak p-type, or n-type first semiconductor substrate (not shown in FIG. 1). On the light emitting layer 4, n-type semiconductor layers 5-7 composed of a single layer or a plurality of layers are laminated. On the surface of the n-type semiconductor layer 7, a second semiconductor substrate 8 transparent to the wavelength of emitted light from the light emitting layer 4 is formed. Then, the first semiconductor substrate is removed. On the plane exposed by removal of the first semiconductor substrate, a translucent electrode layer 9 transparent to the wavelength of emitted light from the light emitting layer is formed.

Abstract: A crystallization apparatus includes a mask and an illumination system which illuminates the mask with a light beam, the light beam from the illumination system becoming a light beam having a light intensity distribution with an inverse peak pattern when transmitted through the mask, and irradiating a polycrystal semiconductor film or an amorphous semiconductor film, thereby generating a crystallized semiconductor film. The mask includes a light absorption layer having light absorption characteristics according to the light intensity distribution with the inverse peak pattern.

Abstract: The present invention provides a micro inertia sensor and a method of manufacturing the same, the micro inertia sensor includes a lower glass substrate; a lower silicon including a first border, a first fixed point and a side movement sensing structure; an upper silicon including a second border, a second fixed point being connected to a via hole, in which a metal wiring is formed, on an upper side, and an sensing electrode, which correspond to the first border, the first fixed point and the side movement sensing structure; a bonded layer by a eutectic bonding between the upper silicon and the lower silicon; and a upper glass substrate, being positioned on an upper portion of the upper silicon, for providing the via hole on which an electric conduction wiring is formed, thereby aiming at the miniaturization of the product and the simplification of the process.

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.

Abstract: Disclosed are a photo diode sensing a short-wavelength light in a blue band, an opto-electronic integrated circuit device comprising the photo diode, and a method of manufacturing the photo diode. The method for manufacturing the photo diode, comprising the steps of: preparing a silicon substrate; forming a first conductive impurity region at a first region on the silicon substrate; forming a second conductive impurity region at a second region on the silicon substrate, said second region being separated from the first region; and forming a porous silicon layer by chemically etching a surface of the second conductive impurity region.

Abstract: A method for removing the edge bead from a substrate by applying an impinging stream of a medium that is not a solvent for the material to be removed. The medium is applied to the periphery of the substrate with sufficient force to remove the material. Also an apparatus to perform the inventive method.

Abstract: The present invention provides a wafer center calibrator to improve the uniformity of the etching, or deposition on a wafer, which is spoiled by the poor assembly of the focus ring with the wafer loader. Thus comprising of a main part, at least one arc part, a handle or any other means by which the calibrator is rotated a round. To use the wafer center calibrator provided by the present invention, at least one arc part is placed into the ring-shaped gap formed between the focus ring and the wafer loader, then the wafer center calibrator is rotated around by a user or any other means. At least one arc part rubs against the focus ring and pushes through where the ring-shaped gap is narrower. Meanwhile, the calibration is rapid and simple, therefore the improvement of the uniformity of the etching or deposition on the wafer can be made in an economical and effective way.

Abstract: A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.

Abstract: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

Abstract: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Abstract: A low-k precursor reactant compound containing silicon and carbon atoms is flowed into a CVD reaction chamber. High-frequency radio-frequency power is applied to form a plasma. Preferably, the reaction chamber is part of a dual-frequency PECVD apparatus, and low-frequency radio-frequency power is applied to the reaction chamber. Reactive components formed in the plasma react to form low-dielectric-constant silicon carbide (SiC) on a substrate surface. A low-k precursor is characterized by one of: a silicon atom and a carbon-carbon triple bond; a silicon atom and a carbon-carbon double bond; a silicon-silicon bond; or a silicon atom and a tertiary carbon group.

Abstract: A method of producing a semiconductor device, wherein after a trench is formed on a field region of a semiconductor substrate, an adsorption reaction of TEOS and a decomposition/recomposition reaction of TEOS using as a catalyst oxygen atoms decomposed from O3 are independently and repeatedly performed. As disclosed, the oxide layer can be buried in the trench with a fine width without generating voids therein, increasing electrical property of the semiconductor device.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device (10) with a heat sink (30) is described. In one aspect, a thermally conducting filled gel elastomer material (50) or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface (18) to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material (38) which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die.

Abstract: A method of manufacturing a semiconductor device is provided including preparing a lead frame having a plurality of leads, wherein the lead widths of the lead tips are smaller than the lead thickness of the tips. A plate is also prepared having a first portion and second portion on a main surface thereof, the second portion being located at the outer periphery of said first portion. A semiconductor chip having a semiconductor element and a plurality of electrodes is fastened to the first portion of the plate and the lead tips are fastened on the second portion of the plate. Bonding wires are then formed to electrically connect the lead tips and the electrodes of the semiconductor chip, and then the lead tips, the plate, the semiconductor chip and the bonding wires are sealed with a molding member.

Abstract: An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies secured to a single semiconductor support structure is inserted into an encapsulation mold. The mold contains a first section and a second section, which form a cavity around the assembly. The mold contains an aperture for transferring encapsulating material into the mold cavity. One of the mold sections has a design feature, such as a raised rib or groove interconnecting at approximately the separation or saw-cut regions of the individual dies of the assembly. Encapsulation material is inserted into the mold cavity until the cavity is filled. The mold section design feature shapes the top surface of the encapsulation layer. The mold is removed leaving the exterior surface of the encapsulation layer patterned with the design feature.

Abstract: In a semiconductor device in which a wiring layer having an area which overlaps a connecting position and a wiring layer having an area which does not overlap the connecting position exist, if the wiring layer having the area which overlaps the connecting position is formed by connecting exposure, a pattern is formed in consideration of an alignment margin. Therefore, it is not advantageous in terms of a wiring width and a space between the wirings as compared with those in the case of forming the wiring layer by a batch processing of exposure. In a manufacturing method of a semiconductor device having a plurality of wiring layers, a first wiring layer is formed as a pattern by dividing a desired pattern into a plurality of patterns, connecting the divided patterns, and exposing them, and a second wiring layer is formed, as a pattern, by the batch processing of exposure.

Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.

Abstract: An example method for fabricating a semiconductor device includes forming a well, a source region, and a drain region in a substrate, forming a gate oxide film on the substrate and coating a polysilicon film on the gate oxide film. Further, the example method includes forming a trench isolation in the substrate by a dry etching process, forming a oxide film on the inside surface of the trench isolation, providing a dielectric material to fill in the trench isolation, planarizing the dielectric material to expose the top surface of the polysilicon film, and forming a gate by dry etching the polysilicon film.

Abstract: In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers.

Abstract: A method of forming a polycrystalline silicon active layer for use in a thin film transistor is provided.

Abstract: A method of substantially reducing and/or eliminating the amount of defects and/or impurities that amass at interfacial surfaces that are present in a multilayer structure is provided. Specifically, the method improves the efficiency of a forming gas anneal by providing a multilayer structure having a catalytic layer formed thereon or buried therein which allows for a significant increase in the amount of hydrogen or deuterium which can be incorporated into the structure. The method is also conducted at a low temperature (on the order of about 400° C. or less). Multilayer structures are also provided which include an annealed multilayer structure having at least one interfacial surface present therein. The at least one material interface contains a region of hydrogen or deuterium which substantially reduces defects and impurities present at the at least one interface.

Abstract: A thin film transistor has a structure capable of decreasing deterioration in Vgs-Ids characteristics. The thin film transistor has a source region composed of an N-type impurity-diffused region, a drain region, and a gate electrode, and a channel region formed directly below the gate electrode. To the source region and the drain region are connected a source electrode and a drain electrode, respectively, through a plurality of contact holes. In the channel region are formed a plurality of P-type impurity-diffused regions at constant intervals.

Abstract: A method of manufacturing a thin film transistor with a reduced number of manufacturing steps is provided, in which the possibility of light entering the channel forming layer of the thin film transistor can be obviated. The thin film transistor comprising a gate electrode (16a), a drain electrode (12a), a source electrode (17a) and a channel (24) and a shield layer (21) on a transparent substrate (20). The channel (24) is formed in that a channel forming layer is photolithographically patterned with the shield layer (21) as mask. As shield layer (21), the gate electrode (16a) can be used, this giving a bottom gate thin film transistor. The transistor is very suitable for use in a liquid crystal display.

Abstract: A data pad region of a liquid crystal display panel includes a plurality of data lines vertically arranged at specified intervals, a plurality of data pads respectively connected to the data lines, at least one first side contact with a first area formed in each data pad and at least one second side contact with a second area formed in each data pad, wherein the first area is larger than the second area.

Abstract: A method of fabricating a semiconductor device includes the step of forming a source and a drain doped with a first conductivity type in an active area, which is made on both sides of a word line by an isolation layer of a second conductivity type doped substrate, each word line being separated by a predetermined interval; forming a first contact and a second contact by using the isolation layer which is separated at a wider interval on the source than on the drain to expose the source and the drain; and selectively implanting the second conductivity type dopant ion in the source by using the isolation layer and the word line as a ion implanting mask during a tilt ion implantation process.

Abstract: Methods are provided for fabricating a transistor gate structure in a semiconductor device, comprising growing an interface oxide layer to a thickness of about 18 Å or less over a semiconductor body using an oxidant comprising N2O and hydrogen or NO and hydrogen at a temperature of about 800 degrees C. or more and a pressure of about 200 Torr or less. A high-k dielectric layer is formed over the interface oxide layer, and a gate contact layer is formed over the high-k dielectric layer. The gate contact layer, the high-k dielectric layer, and the interface oxide layer are then patterned to form a transistor gate structure.

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract: A method for forming a transistor of a semiconductor device wherein a deposition of a buffering oxide film prior to deposition of a nitride film for a gate spacer is performed at a low temperature to prevent out-diffusion of impurities implanted in a source/drain region, thereby providing a semiconductor device with low contact resistance for a bitline and a storage electrode is disclosed. The method for forming a transistor of a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate; ion-implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source/drain junction region; forming an oxide film on the resulting structure at a temperature below 700° C.; and forming a nitride film spacer on a sidewall of the gate electrode.

Abstract: The present invention provides a p-channel metal-oxide-semiconductor (pMOS) device having an ultra shallow epi-channel satisfying a high doping concentration required for a device of which gate length is about 30 nm even without using a HALO doping layer and a method for fabricating the same. The pMOS device includes: a semiconductor substrate; a channel doping layer being formed in a surface of the semiconductor substrate and being dually doped with dopants having different diffusion rates; a silicon epi-layer being formed on the channel doping layer, whereby constructing an epi-channel along with the channel doping layer; a gate insulating layer formed on the silicon epi-layer; a gate electrode formed on the gate insulating layer; a source/drain extension region highly concentrated and formed in the semiconductor substrate of lateral sides of the epi-channel; and a source/drain region electrically connected to the source/drain extension region and deeper than the source/drain region.

Abstract: The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a depth from a lastly deposited nitride layer to a bottom surface of a trench is shallower, and thereby decreasing incidences of a void generation. Also, the present invention provides an advantage of an elaborate manipulation of well and channel dopings by performing ion-implantations with two different approaches. Furthermore, it is possible to enhance device characteristics by decreasing gate induced drain leakage (GIDL) currents and improving a capability of driving currents. This decrease of the GIDL currents and the improved driving current capability are obtained by forming the gate oxide layer with different thicknesses.

Abstract: Disclosed are an electrode of a semiconductor device and a method of forming the same. A polysilicon layer is formed on a semiconductor substrate. An amorphous silicon capping layer is then formed on the polysilicon layer. A silicide layer is formed on the capping layer. The capping layer prevents chlorine ions from diffusing downward to the polysilicon layer. Accordingly, abnormal growth of the polysilicon layer can be prevented, thus improving the stability of the electrical characteristics of a semiconductor device electrode.

Abstract: A fabrication process for transistor array substrates of different sizes on a common substrate provides quality control, yield, and space efficiency advantages. In particular, a four-mask process, including a mask with diffraction slits, may be employed to fabricate transistors that share common channel characteristics for each of the transistor array substrates.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of securing a bottom contact area of a storage node contact as well as of preventing losses of a bit line hard mask insulation layer. These effects are achieved by planarizing an inter-layer insulation layer, which is filled into etched portions formed between conductive patterns, with the bit line hard mask insulation layer through a CMP process. This planarization process decreases a thickness of an etch target to thereby provide more vertical etch profile compared to a typical etch profile that is tapered or inclined at a bottom contact area. As a result of the decreased thickness of the etch target and the more vertical etch profile, it is possible to obtain the wider bottom contact area and prevent losses of the bit line hard mask insulation layer.

Abstract: The present invention is directed to improving defect performance in semiconductor processing systems. In specific embodiments, an apparatus for processing semiconductor substrates comprises a chamber defining a processing region therein, and a substrate support disposed in the chamber to support a semiconductor substrate. At least one nozzle extends into the chamber to introduce a process gas into the chamber through a nozzle opening. The apparatus comprises at least one heat shield, each of which is disposed around at least a portion of one of the at least one nozzle. The heat shield has an extension which projects distally of the nozzle opening of the nozzle and which includes a heat shield opening for the process gas to flow therethrough from the nozzle opening. The heat shield decreases the temperature of nozzle in the processing chamber for introducing process gases therein to reduce particles.

Abstract: A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a metal layer over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying under high vacuum a laser beam to the metal proximate each via for a sufficient period of time to melt the metal for sealing the via.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: A thin film transistor and its fabrication method. The transistor includes a buffer layer on a substrate, and a poly-crystalline semiconductor layer on the buffer layer. The poly-crystalline semiconductor layer includes a channel layer, offset regions along sides of the channel layer, sequential doping regions along sides of the offset regions, and source and drain regions. The doping concentration is sequentially changed in the sequential doping region. A sloped gate insulation layer is on the poly-crystalline semiconductor layer. A gate electrode having a main gate electrode and auxiliary gate electrodes is on the sloped insulation layer. An interlayer is over the gate electrode and source and drain electrodes are formed in contact with the source and drain regions and on the interlayer. The poly-crystalline semiconductor layer is formed by ion doping a poly-crystalline semiconductor layer through the gate insulation layer while using the gate electrode as a mask.

Abstract: A method of forming a gate dielectric includes the steps of forming a gate oxide layer on a substrate, forming a buffer layer over the gate oxide layer and incorporating nitrogen into the gate oxide layer through the buffer layer. A semiconductor device having a gate structure is also provided. The gate includes a nitrogen enriched gate oxide layer formed on a substrate, a silicon nitride or poly-silicon buffer layer formed on the gate oxide layer and a gate electrode formed over the buffer layer.

Abstract: The present invention relates to a process for integrating air as dielectric in semiconductor devices, comprising the steps of:

Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.

Abstract: The present invention is related to a method for fabricating a ferroelectric memory device effectively preventing a deformation and lift of a lower electrode caused by a different thermal expansion rate between the lower electrode and a inter layer dielectric film at a succeeding heat treatment process. The method for fabricating a ferroelectric memory device includes: forming a lower electrode on a predetermined surface of a semiconductor substrate; forming a metal oxide layer over a surface of the lower electrode and a surface of the semiconductor substrate; forming an inter layer dielectric film over the metal oxide layer; performing a blanket etching for the inter layer dielectric film and the metal oxide layer; and forming an opening having a predetermined depth.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Abstract: A method of fabricating a shallow trench isolation. A wafer on which a mask layer is formed is provided. A blank wafer is provided and disposed in an etching machine to perform an etching process. Whether the blank wafer contains a defect is inspected. If the number of defects occurring on the blank wafer is within an acceptable quantity, the wafer is disposed in the etching machine for performing an etching process and defining a trench. The trench is then filled with an insulation layer. The mask layer is removed to form a shallow trench isolation.

Abstract: A capacitor is fabricated over a first layer having a first conductive plug formed on a substrate in a semiconductor memory. On the first layer, a silicon nitride film, a first capacitor oxide film, and a second oxide film are sequentially formed. The first and the second oxide films have different wet etch rates. Dry and wet etchings are sequentially performed to the first and second oxide films to form a second contact hole. The second contact hole is then etched. Thereafter, a silicon film and a filler film are sequentially formed on the resultant surface of the structure. A cylindrical storage node electrode is then formed by etching a predetermined portion of the filler film and the silicon film. After removing the remaining filler film and the oxide films, a Ta2O5 dielectric film covering the storage node electrode and a TiN film for an upper electrode are then sequentially formed.

Abstract: A method for fabricating a capacitor of a semiconductor device for improving a capacitance and concurrently enhancing a leakage current characteristic and a breakdown voltage characteristic. The method includes the steps of: (a) forming a conductive silicon layer for a bottom electrode on a substrate; (b) nitridating the conductive silicon layer; (c) oxidizing the nitridated conductive silicon layer; (d) forming a silicon nitride layer on a surface of the oxidized layer; (e) forming a dielectric layer on the silicon nitride layer; and (f) forming a top electrode on the dielectric layer.

Abstract: In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.