Abstract: A method for forming a semiconductor device having improved characteristics and reliability by forming a hard mask layer on a bit line to prevent degradation of characteristics of the device in a self-alignment contact process of a storage electrode is disclosed. The hard mask layer utilizes over-hang formed at the upper portion of the bit line so as to provide sufficient protection for the bit line in the subsequent etching processes.

Abstract: Disclosed is a method of manufacturing the non-volatile memory device. The method comprises the step of forming a floating gate on a semiconductor substrate, implementing nitrification treatment for the top surface of the floating gate, forming a silicon nitride film on the floating gate experienced by the nitrification treatment, forming a metallic oxide film on the silicon nitride film, implementing annealing in order to supplement oxygen for the metallic oxide film, and forming a control gate on the metallic oxide film. As the leakage current due to irregularity of the interface is prevented, electrical characteristics could be improved. Furthermore, the process equipment used in the existing DRAM (dynamic random access memory) capacitor could be utilized intact.

Abstract: According to the present invention, there is provided a semiconductor memory having a memory cell array region and peripheral circuit region, comprising, a gate electrode formed on a semiconductor substrate via a first insulating film in each of said memory cell array region and peripheral circuit region, and including a conductive layer which at least partially includes a silicon layer, and a second insulating film, a first oxide film formed on side surfaces of said conductive layer included in said gate electrode and on said semiconductor substrate in said memory cell array region, a second oxide film formed on side surfaces of said conductive layer included in said gate electrode and on said semiconductor substrate in said peripheral circuit region, and having a film thickness smaller than that of said first oxide film, a first nitride film formed on side surfaces of said gate electrode in said memory cell array region, and a second nitride film formed on side surfaces of said gate electrode in said periph

Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

Abstract: A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed.

Abstract: A manufacturing method for fabricating flash memory semiconductor devices is disclosed.

Abstract: Disclosed is a method of manufacturing the flash memory device.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.

Abstract: A method and device for manufacturing a mask ROM integrated circuit device to reduce influences of punch through between source and channel regions that output improper program readings. The method includes forming well regions using an implant process on semiconductor substrate and forming a plurality of buried implant regions through first patterned mask. The first patterned mask is formed overlying the semiconductor substrate. Each of the buried implant regions includes a source region and a drain region for each respective memory cell region. The memory cell region is one of a plurality of memory cell regions. The method also forms pocket regions adjacent to a vicinity of each of the buried implant regions within the channel region for each of the memory cell regions. A first pocket region is defined between the channel region and source region and a second pocket region is defined between the channel region and the drain region for each memory cell region.

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode, thereby forming a low concentration source/drain electrode for a lightly doped drain (LDD) structure not by conventional ion implanting process but by out diffusion of impurities contained in the sidewall. Thus, it is made possible to minimizes damages of substrate due to ion implanting process, since the number of process of ion implantation may be naturally minimized through the above mentioned ion implantation process according to the present invention. Also, it is made possible for gate electrode to maintain its size independently, regardless of distance between source electrode and drain electrode, by excluding a role of ion implanting mask which has been performed by gate electrode.

Abstract: A process for producing an electronic component includes covering a substrate with a portion defining, with the substrate, a volume at least partly filled with a temporary material. The temporary material is then removed via chimney for access to said volume. A deposition of a fill material is then made in said volume, the fill material being obtained from precursors supplied via the chimney. The process is particularly suitable for producing a gate of an MOS-type transistor. In this case, the fill material is conducting or semiconducting, and an electrically insulating coating material may also be deposited in said volume before the (semi)conducting fill material. The process also includes defining a trench in a substrate filled with a temporary material. The filled trench is then covered with a circuit portion. The temporary material is then removed via a chimney for access to the trench. A deposition of low dielectric fill material is then made in the trench.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: A bipolar transistor having a base semiconductor layer structure to minimize base parasitic resistance and a method of manufacturing the bipolar transistor are provided. In the provided bipolar transistor, a collector region of a second conductivity type, which is defined by isolation regions, is formed on a semiconductor substrate of a first conductivity type. A first base semiconductor layer of the first conductivity type extends from the upper surface of the collector region to the upper surface of the isolation regions. Here, the first base semiconductor layer is formed of a silicon germanium (SiGe) layer. Second base semiconductor layers of the first conductivity type are formed on the portions of the first base semiconductor layer except for the portions having the emitter region and the emitter insulating layers. Base ohmic layers are formed on the second base semiconductor layers.

Abstract: The present invention provides a method for fabricating a capacitor constituted with double hafnium oxide layers through a plasma enhanced chemical vapor deposition (PECVD) process and a low pressure chemical vapor deposition (LPCVD) process. The method for fabricating the capacitor constituted with the double hafnium oxide layers includes: forming a lower electrode layer over a semiconductor substrate; performing a heat treatment with the lower electrode; forming a first HfO2 layer over the first HfO2 layer by using a plasma enhanced chemical vapor deposition (PECVD) method; forming a second HfO2 layer over the first HfO2 layer by using a low pressure chemical vapor deposition (LPCVD) method; and performing a plasma treatment process at a high temperature; and forming an upper electrode over the second HfO2 layer.

Abstract: Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

Abstract: The present invention is related to a method for fabricating a capacitor capable of preventing a contact between neighboring lower electrodes even if a height of the lower electrode increases. The lower electrode is formed to have a critical dimension wider at a bottom region than at a top region to thereby be firmly supported. Also, a wider distance between the lower electrodes prevents neighboring lower electrodes from contacting to each other. As a result of these effects, it is possible to prevent a failure of dual bit, which eventually results in higher yields of semiconductor devices.

Abstract: The present invention provides a method for forming a capacitor in a semiconductor device. Particularly, an aluminum oxide (Al2O3) layer deposited by using an atomic layer deposition (ALD) process is used for the capacitor. The inventive method for forming the capacitor, including; forming a lower electrode constituted with a poly-silicon layer on a semiconductor substrate a predetermined process on which a predetermined process has been completed; forming a uniform silicon oxide layer on the lower electrode; forming an aluminum oxide (Al2O3) film on the silicon oxide layer by performing an atomic layer deposition (ALD) process; and crystallizing the Al2O3 film by carrying out a heat treatment process.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.

Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structures are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

Abstract: In a method for manufacturing a merged DRAM with a logic (MDL) device with a DRAM and a logic device formed on single chip.

Abstract: A semiconductor device and a method for releasing stress exerted while fabricating the semiconductor device. The method for releasing the stress, includes forming a stack layer deposited on a semiconductor sequentially with a gate oxide layer, a poly-silicon layer, a tungsten layer, and a hard mask; selectively oxidizing, wherein only the poly-silicon layer of the stack layer is oxidized; heat treating for releasing stress exerted during the selective oxidation process; and forming a gate sealing nitride layer on the stack layer heat-treated.

Abstract: An oxidation process is performed for a surface of the SOI film exposed from the opening pattern to form and eliminate the silicon oxide film, so that the SOI film would be thinned. In the opening pattern, formed a gate oxide film as a third insulation film, on which a poly-silicon film is formed as a conductive film so as to fill in the opening pattern. The first insulation film is then eliminated while the second insulation film formed on the inner wall of the opening pattern is remained, so that a gate electrode provided on the side wall thereof with a sidewall would be formed on the gate oxide film.

Abstract: The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation trench; forming a first silicon oxide film burying the isolation trench; etching and removing the first silicon oxide film in an upper region of the isolation trench; etching and removing the exposed second silicon nitride film; chemical-mechanical-polishing the second silicon oxide film; and etching and removing the exposed first silicon nitride film.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In a disclosed example, a multi-layered insulating structure is deposited on a semiconductor substrate, an opening is formed in the multi-layered insulating structure above the semiconductor substrate, and a trench is formed in the semiconductor substrate under the opening. Then, a groove is formed on an edge position of an intermediate layer of the multi-layered insulating structure by wet-etching the intermediate layer of the multi-layered insulating layer transversely using a pull back process. Then, a liner oxide layer is deposited on the groove and the trench. An oxide layer then fills the trench and the groove without generating voids or divots in the oxide layer of the trench.

Abstract: Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.

Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of 2500 mJ/m2 have also be achieved herein.

Abstract: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seam-less bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Abstract: A method for forming scribed grooves on a wafer and an apparatus for implementing the method. The method moves the cutting part such that its cutting edge forms an inverted trapezoid-shaped path, thereby reducing the scribing angle of the cutting edge to an acute angle. Consequently, the stress produced by the mechanical shock at the time of the scribing can be dispersed in the moving direction of the cutting edge and in a direction perpendicular to the surface of the wafer. The horizontal movement of the scribing cutting edge in the wafer enables the application of a sufficient load in a direction perpendicular to the scribing plane in the wafer. Consequently, vertical cracks are sufficiently generated, and the amount of dimensional deviation between the scribed groove and the cleaved plane is reduced. This method can produce chips featuring outside dimensions with higher precision and cleaved surfaces with high-quality mirror finish.

Abstract: In a substrate machining method for machining a substrate, there are provided a substrate machining method in which a disk-like blade is rotated to cut the substrate from its one surface, and the cut surfaces of the substrate, which are positioned in the vicinity of the other surface of the substrate, are irradiated with laser light; and a substrate machining apparatus which carries out the substrate machining method. The entirety of the cut surfaces of the substrate may be irradiated with the laser light. The laser may be a YAG laser or a CO2 laser. Further, a dicing tape may be adhered to the other surface of the substrate, and the laser light may be irradiated after cutting only the substrate and expanding the dicing tape. Modified layers are formed by an irradiation of the laser light, so that dice are prevented from being broken in an assembling operation of the dice.

Abstract: A method for manufacturing integrated circuit devices including metal interconnect structures. The method includes forming a first dielectric material overlying a surface of a semiconductor substrate. The method also includes forming a metal damascene structure in the first dielectric material, which surrounds the metal damascene structure. The method selectively removes the first dielectric material surrounding a portion of the metal damascene structure to expose the portion of the metal damascene structure. The method forms a porous dielectric material surrounding a vicinity of the exposed portion of the metal damascene structure, whereupon the porous dielectric material has a dielectric constant ranging from no greater than 2.6 but greater than 1.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: Lamp based spike annealing was improved to address the aggressive requirements of <100 nm Ultra Shallow Junction (USJ) technologies. Improvements focused on enhancing cool down rates, and thereby improving spike sharpness. Boron ion implanted substrates with varying ion-implanted energy and dose were then annealed to characterize the improvements in spike annealing. A greater than 10% improvement in sheet resistance and junction depth was realized on substrates that were annealed with the improved spike profile. The improved spike anneal had the same comparable uniformity to the standard spike anneal.

Abstract: One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.

Abstract: A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

Abstract: Disclosed is a method of forming the metal line in the semiconductor device. The method comprising the steps of forming an interlay insulating film on a semiconductor substrate in which a lower line is formed, patterning the interlay insulating film to form an aperture unit for forming an upper line connected to the lower line, cooling the semiconductor substrate in which the aperture unit is formed at a given temperature, implementing a cleaning process using a hydrogen reduction reaction in order to remove polymer formed on the sidewall of the aperture unit and a metal oxide film formed on the lower line, implementing an annealing process in-situ within a chamber in which the cleaning process is implemented, and burying the aperture unit with a conductive material to form an upper line.

Abstract: Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion layer over the substrate or any intentional interface layers, and a high-k gate dielectric is formed over the nucleation promotion layer. The nucleation promotion layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprising a metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapor deposition of high-k gate dielectric materials by increasing the density of nucleation sites on the substrate or intentional interface layer.

Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, comprises the steps of: forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a silicon-based film on the impurity diffusion preventing film; forming a refractory metal on the silicon-based film; forming a nitride film on the refractory metal silicide film; patterning the impurity diffused polysilicon film, the impurity diffusion preventing film, the silicon-based film, the refractory metal silicide film and the nitride film on a gate electrode; and performing an oxidation process.

Abstract: Disclosed is a method of manufacturing the semiconductor devices. The method comprising the steps of forming a gate electrode on a semiconductor substrate, depositing an oxide film for a spacer on the gate electrode, implementing an anisotropic dry etch process for the oxide film for the spacer to form spacers at the sidewalls of the gate electrode, and implementing a rapid thermal annealing process for the spacers under an oxygen atmosphere in order to segregate hydrogen contained within the spacers toward the surface. Therefore, hydrogen contained within the spacer oxide film is not diffused into the tunnel oxide film and the film quality of the tunnel oxide film is thus improved. As a result, program or erase operation characteristics of the flash memory device and a retention characteristic of the flash memory device could be improved.

Abstract: A method for manufacturing a semiconductor device is disclosed. One example manufacturing method includes successively depositing gate insulating layer forming material and gate electrode forming material on a semiconductor substrate and patterning the gate insulating layer forming material and the gate electrode forming material to form a gate insulating layer and a gate electrode. The example manufacturing method further includes performing a nitrogen ion-implantation to a front face of the substrate and annealing the substrate so as to form a re-oxidation layer that has different thickness on the sidewalls of the gate electrode and on the substrate. The example method results in semiconductor gate electrodes and sidewalls having different oxidation rates so that a thickness of the re-oxidation layer of the sidewalls of the gate electrode is relatively thickened.

Abstract: A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is formed on an area of the gate oxide layer exposed through the sidewall opening and on the sacrificial layer. Anisotropic etching of the polycrystalline silicon layer is performed such that sidewall gates are formed by remaining portions of the polycrystalline silicon layer on sidewalls of the sidewall opening, a width of the sidewall gates corresponding to a desired width of a gate. The sacrificial layer is removed following etching of the polycrystalline silicon layer.

Abstract: A method for producing a microsystem that has, situated on a substrate, a first functional layer that includes a conductive area and a sublayer. Situated on the first functional layer is a second mechanical functional layer, which is first initially applied onto a sacrificial layer situated and structured on the first functional layer. In addition, a layer is situated on the side of the sublayer facing away from the conductive area. The layer constitutes a protective layer on the first functional layer that acts in areas during a sacrificial layer etching process so that during removal of the sacrificial layer no etching of the areas of the first functional layer covered by the protective layer occurs, and that in the region of the areas of the first functional layer implemented without the protective layer the sublayer is removed essentially selectively to the conductive area at the same time as the sacrificial layer.

Abstract: A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls are disposed into each opening and melted partially to bond to the metallic layer temporarily by performing a heating process simultaneously. Then, a process of disposing the flux material in the openings to cover the surfaces of the solder balls is performed.

Abstract: A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned, so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls with a solidified material on the surface of each solder ball are disposed into each opening. Then, a reflow process is carried out, so that the solder balls bond with the metallic layer. Finally, the photoresist layer is removed.

Abstract: A method of assembling a passive component over the active surface of a die is provided. The method shortens the signal transmission path between the die and the passive component so that electrical performance of the die after packaging is improved. In addition, the transmission path and the number of contacts on the substrate for connecting the die and the passive component are reduced. With a reduction in transmission path, size of the substrate can be reduced. Furthermore, a plurality of passive components may be assembled onto the dies of a wafer in a single operation so that there is no need to assemble individual passive component over each packaging substrate.

Abstract: In accordance with the invention, a spaced-apart array of nanostructures is fabricated by providing a shadow mask having a plurality of spaced apart, relatively large apertures, reducing the size of the apertures to nanoscale dimensions, and depositing a material through the mask to form a plurality of spaced-apart nanostructures. In a preferred embodiment, the spaced apart nanostructures comprise nanoscale islands (nano-islands) of catalyst material, and spaced-apart nanowires such as carbon nanotubes are subsequently grown from the islands.

Abstract: A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.

Abstract: A tunable process for forming a barrier layer in an opening is provided. First, a dielectric layer is formed on a substrate. Second, an opening is formed in the dielectric layer. The opening has sidewalls and a bottom. Third, barrier layer material is deposited on the sidewalls and bottom of the opening. Fourth, sputter etching is used to remove barrier layer material from an overhang portion of the barrier layer and to redistribute barrier layer material removed from the overhang portion to the sidewalls. During the sputter etching step, the sputter etching may also remove barrier layer material from the bottom of the opening and redistributes barrier layer material removed from the bottom of the opening to the sidewalls. The sputter etching parameters may be selected to achieve a desired barrier layer configuration.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of improving a gap-fill property of a conductive wire. To achieve this effect, the inventive method includes the steps of: forming a plurality of conductive patterns on a substrate in the first region and the second region, wherein each of the conductive patterns includes sequentially stacked layers of a conductive layer and a hard mask; removing the hard mask in the second region to expose the conductive layer; forming a diffusion barrier layer on the exposed conductive layer; depositing an insulation layer on the entire resulting substrate structure in the first region and the second region; selectively etching the insulation layer in the second region to form an opening exposing the diffusion barrier layer; and forming a conductive wire electrically connected to the diffusion barrier layer through the opening.