Abstract: Disclosed are a vertical GaN based light-emitting device (LED) structure and the manufacturing method thereof. In the structure and the corresponding method, a substrate unit having a mask is used to form a multi-layer epitaxial structure and the substrate and the multi-layer epitaxial structure are separated at the mask. After the multi-layer epitaxial structure is extracted, a metal reflector may be disposed thereunder. Next, a conductive substrate is bonded to the metal reflector. Next, an upper surface of the multi-layer structure is disposed with a p-electrode and a bottom side of the conductive substrate with an n-electrode whereby an vertical LED structure is formed.

Abstract: A UV curing apparatus and method is provided for enhancing the distribution and application of UV light to UV photo initiators in a UV curable ink, coating or adhesive. The UV curing apparatus and method comprises UV LED assemblies in a first row with the UV LED assemblies spaced from adjacent UV LED assemblies. At least one second row of a plurality of UV LED assemblies are provided next to the first row but with the UV LED assemblies of the second row positioned adjacent the spaces between adjacent UV LED assemblies in the first row thereby to stagger the second row of UV LED assemblies from the UV LED assemblies in the first row. Desirably, the rows of staggered UV LED assemblies are mounted on a panel. UV curable products, articles or other objects containing UV photo initiators that are in or on a web can be conveyed or otherwise moved past the rows of UV LED assemblies for effective UV curing.

Abstract: A method of making an OLED device includes the steps of: providing a curved, rigid substrate; and forming one or more OLED elements on the substrate.

Abstract: A high performance bipolar transistor device is realized from a series of layers formed on a substrate, the series of layers including a first set of one or more layers each comprising n-type dopant material, a second set of layers forming a p-type modulation doped quantum well structure, and a third set of one or more layers each comprising n-type dopant material. The first set of layers includes an n-type ohmic contact layer. A collector terminal metal layer is deposited and patterned on one layer of the third set. P-type ion implant regions and a patterned base terminal metal layer (which contact the p-type modulation doped quantum well structure) are formed in an interdigitated manner with respect to a patterned emitter metal layer formed on the n-type ohmic contact layer. Preferably, a capping layer that covers the sidewalls of the active device structure (as well as covering the collector metal layer) is used to form the interdigitated base and emitter metal layers of the device.

Abstract: A light emitting diode includes first and second electrical terminals of which the first terminal forms a support. A light emitting diode die is mounted on the support of the first terminal and is connected to the second terminal by a conductive wire for emitting a first light. An encapsulation is formed around the die. A phosphor layer is formed on the support and interposed between the die and the support. The phosphor receives a portion of the first light and in turn gives off a second light that is selectively different from the first light for combining with the first light that travels out of the encapsulation to control brightness and color of the light projecting out of the encapsulation. Thus, a stable lighting may be achieved and mass production of quality-controlled light emitting diodes is made possible.

Abstract: A pink light emitting diode includes a blue LED chip and a mixing fluorescent powder. The mixing fluorescent powder, which includes a yellow fluorescent powder and a red fluorescent powder, is covered on the blue LED chip, wherein the yellow fluorescent powder is capable of absorbing a part of blue light emitted by blue LED chip and emitting yellow wavelength light, the red fluorescent powder is capable of absorbing a part of blue light emitted by blue LED chip and emitting red wavelength light, so that mixing the blue light, yellow light, and the red light to produce the pink light emitting diode.

Abstract: An organic light emitting diode device includes an array layer having a plurality of thin film transistors, an organic light emitting diode formed on a second substrate, a plurality of connection patterns disposed between the first and second substrates, the connection pattern connecting a respective thin film transistor to the corresponding organic light emitting diode and a sealant between the first and second substrates, wherein each thin film transistor includes: a gate electrode on the first substrate, the gate electrode having an opening in the middle thereof; a gate insulating layer over the gate electrode; a semiconductor layer on the gate insulating layer above the gate electrode; a drain electrode on the semiconductor layer corresponding to the opening of the gate electrode; and first and second source electrodes formed respectively on both sides of the semiconductor layer and spaced apart from the drain electrode.

Abstract: A radiation-emitting semiconductor component having a layer structure which contains an n-doped cladding layer (18), a p-doped cladding layer (20), and an active layer (14) based on InGaAlP arranged between the n-doped cladding layer (18) and the p-doped cladding layer (20). A diffusion stop layer (16) is arranged between the active layer (14) and the p-doped cladding layer (20). The diffusion stop layer (16) is formed by a strained superlattice.

Abstract: In a light-emitting device, a light-emitting layer portion composed of a compound semiconductor is bonded on one main surface of a transparent conductive semiconductor substrate while placing a substrate-bonding conductive oxide layer composed of a conductive oxide in between. Between the light-emitting layer portion and the substrate-bonding conductive oxide layer, a contact layer for reducing junction resistance with the substrate-bonding conductive oxide layer so as to contact with the substrate-bonding conductive oxide layer. This is successful in providing the light-emitting device which is producible at low costs, has a low series resistance, and can attain a sufficient emission efficiency despite it has a thick current-spreading layer.

Abstract: A light-emitting device comprising: a pair of electrodes formed on a substrate; and at least one organic compound layer containing a light-emitting layer provided between the electrodes, wherein the at least one organic compound layer comprises a host material, a layer of the host material has an energy gap of not less than 3.6 eV and an ionization potential of the host material is from 5.4 eV to 6.3 eV.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Abstract: A plasma oscillation switching device of the present invention comprises semiconductor substrate 101; first barrier layer 103 that is composed of a III-V compound semiconductor and formed on the substrate; channel layer 104 that is composed of a III-V compound semiconductor and formed on the first barrier layer; second barrier layer 105 that is composed of a III-V compound semiconductor and formed on the channel layer; source electrode 107, gate electrode 109 and drain electrode 108 provided on the second barrier layer, wherein the first barrier layer includes n-type diffusion layer 103a, the second barrier layer includes p-type diffusion layer 105a, the band gap of the channel layer is smaller than the band gaps of the first and the second barrier layers, two-dimensional electron gas EG is accumulated at the conduction band at the boundary between the first barrier layer and the channel layer, two-dimensional hole gas HG is accumulated at the valence band at the boundary between the second barrier layer and

Abstract: A bidirectional switch for switching an A.C. voltage at a load, comprising a monolithic component, formed in an N-type substrate, comprising a first vertical thyristor; a second vertical thyristor; a P-type triggering region formed opposite to the cathode of the first thyristor and an N-type triggering region formed in the P-type triggering region, the P-type triggering region being intended to receive a control signal in a negative halfwave of the A.C. voltage to trigger the first thyristor; a resistive element connected to the P-type triggering region and to the anode of the first thyristor; and a capacitor having a terminal connected to the N-type triggering region and its other terminal intended to be connected to the reference voltage.

Abstract: A sealing apparatus for sealing by resin a semiconductor wafer having semiconductor elements on its surface. The apparatus includes an upper mold and a lower mold having an area where the semiconductor wafer is mounted, the lower mold having an uneven surface in the area and a shock absorber under the lower mold.

Abstract: The present invention has an object of providing a variable optical filter that can move its periodic filter characteristic over a wide range in parallel to an optical frequency axis direction. To this end, the variable optical filter of the present invention comprises: first and second filter sections connected in series via an optical path, and a control section for controlling the periodic filter characteristic of each of the first and second filter sections. The control section, when the filter characteristic of one of the first and second filter sections is required to move in parallel to the optical frequency axis direction to exceed a variable range, relatively controls the filter characteristic of each of the first and second filter sections such that the switching is performed from one filter section to the other filter section, provided that the filter characteristic of the overall variable optical filters becomes constant.

Abstract: According to an aspect of the present invention, an organic electro-luminescence display panel is provided, which includes: an insulating substrate; a polysilicon layer formed on the substrate; a first insulating layer formed on the polysilicon layer; a gate wire formed on the first insulating layer; a second insulating layer formed on the gate wire; a data wire formed on the second insulating layer and including first and second portions; a pixel electrode connected to the first portion of the data wire; a partition defining an area on the pixel electrode; an organic light emitting member formed in the area on the pixel electrode; a common electrode formed on the light emitting member; and a planar supply voltage electrode disposed between the pixel electrode and the substrate and connected to the second portion of the data wire.

Abstract: A practical operational amplifier circuit is formed using thin film transistors.

Abstract: It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing a drop in power supply voltage and a rise in ground voltage.

Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.

Abstract: A block, which is an object to be scanned, of a semiconductor integrated circuit includes a scan flip-flop and a combinational circuit. A serial-parallel conversion unit receives serial scan output data output from the scan flip-flop of the block and converts the serial scan output data into parallel scan output data. A scan output storage stores the parallel scan output data output from the serial-parallel conversion unit, and outputs the parallel scan output data stored to outside of the semiconductor integrated circuit.

Abstract: A semiconductor device includes a trench formed on the source side of the drift region, the p-type gate region and the gate formed at the bottom of the trench, and the source formed over the entire surface of the unit device through the insulating film. The narrowest portion of the channel is deeper than one-half the junction depth of the p-type gate region. This allows the width of the channel on the drain side to be reduced even with a lower energy.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the semiconductor layer, and a gate electrode arranged so as to oppose the channel region via the gate insulating film. At least a portion of the semiconductor layer includes a catalyst element capable of promoting crystallization, and the semiconductor layer further includes a gettering region that includes the catalyst element at a higher concentration than in the channel region or the source region and the drain region. The thickness of the gate insulating film on the gettering region is smaller than that on the source region and the drain region, or the gate insulating film is not disposed on the gettering region.

Abstract: There is provided an electronic device in which the deterioration of the device is prevented and an aperture ratio is improved without using a black mask and without increasing the number of masks. In the electronic device, a first electrode (113) is disposed on another layer different from the layer on which a gate wiring (145) is disposed as a gate electrode, and a semiconductor layer of a pixel switching TFT is superimposed on the gate wiring (145) so as to be shielded from a light. Thus, the deterioration of the TFT is suppressed, and a high aperture ratio is realized.

Abstract: Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.

Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.

Abstract: The MRAM has a transistor for selection, a lower insulating interlayer, a first connecting hole, a first wiring formed on the lower insulating interlayer, a tunnel magnetoresistance device formed on the first wiring through an insulating film, an upper insulating interlayer, and a second wiring, in which a lower surface of the tunnel magnetoresistance device is electrically connected to the first connecting hole through a second connecting hole, and the tunnel magnetoresistance device, the insulating film and the first wiring have nearly the same widths along the second direction.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the top electrode and the bottom electrode, an insulating region surrounding the capacitor and having a first hole which extends in a vertical direction and reaches the top electrode and a second hole which extends in the vertical direction and is spaced away from the capacitor, and a first wiring connected to the top electrode and including a first conductive portion formed in the first hole and a second conductive portion formed in the second hole, the first wiring having a barrier metal film between the insulating region and the first conductive portion and having no barrier metal film between the insulating region and the second conductive portion.

Abstract: A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1−X)OY, (0.05≦x≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM (Metal Insulator Metal) structure, dielectric breakdown of a capacitor insulating film while a relative dielectric constant of a metal oxide film used as the capacitor insulating film is kept high.

Abstract: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

Abstract: A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, a multilayer metal wiring layer, a capacitor comprising first and second elements, each element including a lower metal electrode, a dielectric film, and an upper metal electrode stacked formed on the multilayer metal wiring layer, and first and second wiring layers of an upper layer formed on an insulation film which covers the capacitor, wherein the upper metal electrodes have the same size and shape, the upper metal electrode of each element is provided within an area in which the lower metal electrode and the dielectric film of the each element are stacked, and the lower metal electrode of the first element and the upper metal electrode of the second element are connected to each other, and the upper metal electrode of the first element and the lower metal electrode of the second element are connected to each other.

Abstract: A semiconductor memory can have first lines to which memory cells are connected and that run divergently with respect to one another, and second lines to which the memory cells are connected that are curved. Combining the geometry of the memory cell array with storage capacitors laterally offset allows signal delays along word lines and bit lines to be aligned regardless of the position of a memory cell in the memory cell array. The geometry of the memory cell array allows short signal propagation times to be attained particularly along the first lines, which are divergent with respect to one another, this simplifying error-free operation of a semiconductor memory particularly at high clock frequencies.

Abstract: A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

Abstract: A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and sidewall-shaped control gates formed along both side surface of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. The first control gate and the second control gate are respectively formed on insulating layers having different thickness.

Abstract: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack.

Abstract: A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines.

Abstract: The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.

Abstract: A semiconductor device having non-volatile memory devices. Each of the non-volatile memory devices has a word gate formed above a semiconductor layer with a gate insulating layer interposed, impurity layers formed in the semiconductor layer, and sidewall-shaped control gates formed along both side surfaces of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. A first insulating layer is disposed between the first control gate and the semiconductor layer, and a second insulating layer which has the thickness less than the first insulating layer is disposed between the second control gate and the semiconductor layer. An uppermost layer of the second insulating layer is a charge transfer protection film.

Abstract: A semiconductor structure comprises a memory element, which comprises a floating gate, a control electrode, which is capacitively coupled to the floating gate, wherein a signal for controlling the memory element is applicable to the control electrode, as well as a shield, which is arranged isolated from the floating gate and covers it fully.

Abstract: A semiconductor device according to an aspect of the present invention having a first gate insulating film formed in a first active region of a semiconductor substrate and having a first film thickness, and a second gate insulating film formed in a second active region of the semiconductor substrate and having a second film thickness smaller than the first film thickness, wherein a semiconductor substrate surface in the first active region is lower than that in the second active region is provided.

Abstract: Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etching the semiconductor substrate exposed through the bottom of the hollow; and filling the trench by forming an insulation film on the side wall layer and the trench.

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

Abstract: A thin film transistor and a fabricating method of a thin film transistor for a liquid crystal display device includes forming a polycrystalline silicon film on a substrate, the polycrystalline silicon film having square shaped grains; forming an active layer by etching the polycrystalline silicon film; forming a gate electrode over the active layer, the gate electrode overlapping the active layer to form a channel region, the channel region being formed inside one of the grains; and forming source and drain electrodes connected to both sides of the active layer.

Abstract: A semiconductor circuit has an output circuit, an input circuit and an input protection circuit. The output circuit is connected to a first power supplying terminal and a reference terminal for outputting an output signal. The output circuit has first transistors serially connected between the first terminal and the reference terminal. The input circuit is connected to a second power supplying terminal and the reference terminal. The input circuit has second transistors serially connected between the second terminal and the reference terminal. Each of the first and second transistors has a gate, a source and a drain. In the source and drain, there is a first low resistance region around a contact formed thereon so that a high resistance region is located between the gate and the first low resistance region.

Abstract: A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor.