Abstract: A semiconductor substrate of the present invention is a DSP wafer or Semi-DSP wafer (FIG. 2) having a flatness of an SFQR value ≦70 (nm) and containing boron at a concentration not lower than 5×1016 (atoms/cm3) nor higher than 2×1017 (atoms/cm3) within 95% or more of rectangular regions of 25×8 (mm2) arranged on a front face of the substrate. Specifically, a silicon crystal layer by an epitaxial growth is formed on a front face of a silicon substrate having the above substrate boron concentration.

Abstract: The present invention provides a novel MOS or CMOS based active sensor array for producing electronic images from electron-hole producing light. Each pixel of the array includes a layered photodiode for converting the electron-hole producing light into electrical charges and MOS and/or CMOS pixel circuits located under the layered photodiodes for collecting the charges. The present invention also provides additional MOS or CMOS circuits in and/or on the same crystalline substrate for processing the collected charges for the purposes of producing images. The layered photodiode of each pixel is fabricated as continuous layers of charge generating material on top of the MOS and/or CMOS pixel circuits so that extremely small pixels are possible with almost 100 percent packing factors. In preferred embodiments, pixel crosstalk is minimized by careful design of the bottom photodiode layer with the addition of carbon to the doped amorphous silicon N or P layer to increase the electrical resistivity.

Abstract: A field effect transistor of the present invention is formed in a strain effect semiconductor layer, represented by a strain effect silicon layer, formed in an upper layer of a semiconductor substrate. A source/a drain of the field effect transistor are formed only in the strain effect silicon layer. The field effect transistor may be formed as an nMOS transistor, and a pMOS transistor may be formed in the strain effect silicon layer while being isolated from the nMOS transistor through an isolation region. A logic circuit can be formed of these transistors. Although when an nMOS transistor or a pMos transistor is employed in an application requiring a high performance at a low voltage, there occurs a current leak because the junction of a source/a drain is positioned in a silicon germanium layer having a low band gap or formed at an interface of silicon/silicon germanium, the field effect transistor of the present invention prevents occurrence of such a current leak.

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.

Abstract: An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Abstract: Unit cells of a static random access memory (SRAM) are provided including an integrated circuit substrate and first and second active regions. The first active region is provided on the integrated circuit substrate and has a first portion and a second portion. The second portion is shorter than the first portion. The first portion has a first end and a second end and the second portion extends out from the first end of the first portion. The second active region is provided on the integrated circuit substrate. The second active region has a third portion and a fourth portion. The fourth portion is shorter than the third portion. The third portion is remote from the first portion of the first active region and has a first end and a second end. The fourth portion extends out from the second end of the third portion towards the first portion of the first active region and is remote from the second portion of the first active region. Methods of forming SRAM cells are also described.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: A semiconductor device is provided which is capable of improving its reliability by using a material having a high relative dielectric constant as a material for its gate insulating film, by suppressing degradation of an EOT (Equivalent oxide Thickness) and by preventing crystallization of the material having a high relative dielectric constant. The semiconductor device (Field Effect Transistor) has a silicon substrate, a seed layer made up of silicon oxide, a gate insulating film made of amorphous hafnium aliminate and a gate electrode made up of polycrystalline silicon formed the gate insulating film. The gate insulating film is so formed that a hafnium concentration decreases monotonously or step by step, whereas an aluminum concentration increases monotonously or step by step along a direction of a thickness of the gate insulating film from the silicon substrate side toward the gate electrode.

Abstract: A preferred MOS transistor of the invention includes active regions defined in a substrate. An interfacial oxide thin film is upon the substrate. A WSiNy gate dielectric thin film is formed upon the interfacial oxide thin film and isolates a gate from the active regions.

Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer (8) against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer (12) having a lower redox potential than said material, the sacrificial metal layer (12) being electrically connected to said noble metal layer (8).

Abstract: A noise-proof, integrated semiconductor current detector is disclosed which has formed in a semiconductor substrate a Hall generator for providing a Hall voltage in proportion to the strength of a magnetic field applied, a control current supply circuit for delivering a control current to the Hall generator, and a Hall voltage output circuit for putting out the Hall voltage for detection or measurement. The Hall generator, control current supply circuit, and Hall voltage output circuit are all exposed at one of the pair of opposite major surfaces of the semiconductor substrate. A current-path conductor is attached to this one major surface of the substrate via insulating layers for carrying a current to be detected.

Abstract: A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers.

Abstract: The design and operation of a p-i-n device, operating in a sequential resonant tunneling condition for use as a photodetector and an optically pumped emitter, is disclosed. The device contains III-nitride multiple-quantum-well (MQW) layers grown between a III-nitride p-n junction. Transparent ohmic contacts are made on both p and n sides. The device operates under a certain electrical bias that makes the energy level of the first excitation state in each well layer correspond with the energy level of the ground state in the adjoining well layer. The device works as a high-efficiency and high-speed photodetector with photo-generated carriers transported through the active MQW region by sequential resonant tunneling. In a sequential resonant tunneling condition, the device also works as an optically pumped infrared emitter that emits infrared photons with energy equal to the energy difference between the first excitation state and the ground state in the MQWs.

Abstract: A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Abstract: The present invention improves the resolution and accuracy of the presently known two-dimensional position sensing detectors and delivers improved performance in the 1.3 to 1.55 micron wavelength region. The present invention is an array of semiconductor layers with four electrodes, the illustrative embodiment comprising a semi-insulating substrate semiconductor base covered by a semiconductor buffered layer, the buffered layer further covered by a semiconductor absorption layer and the absorption layer covered with a semiconductor layer. Four electrodes are placed on this semiconductor array: two on the top layer parallel to each other and near the ends of opposite edges, and two etched in the buffered layer, parallel to each other and perpendicular to the first set. The layers are doped as to make a p-n junction in the active area. Substantially all the layers, excepting the semi-insulating substrate layer, are uniformly resistive.

Abstract: A semiconductor device comprises a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region 22 formed to surround the heavily p-doped layer 25 and the intermediately p-doped layer 26. The heavily p-doped layer 25 has a higher dopant concentration than the well 21. The intermediately p-doped layer 26 has a higher dopant concentration than the well 21 and a lower dopant concentration than the heavily p-doped layer 25.

Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.

Abstract: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

Abstract: In a trench super junction semiconductor element having a parallel p-n junction layer 14 with n-drift regions 12 and p-partition regions 13, both extending in a depth direction, being alternately joined, a part 20 in a shape of a three-dimensional curved surface in the end portion of each of trenches is formed in a p-partition region 13. A section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface of the end portion of each of the trenches is made as a p+-region 21 in which an impurity concentration is higher than that in a section thereunder so that an electric field is increased at a boundary between the p+-region 21 and the n-drift region 12, thereby lessening electric field concentration to the part 20 in a shape of a three-dimensional curved surface of the end portion of the trench.

Abstract: A semiconductor device comprises one or two semiconductor chips, each including an input circuit having a wiring (3) for connecting an input pad (2) to an inner circuit, a first electrostatic protection element (1) electrically connected to the wiring, a second electrostatic protection element (1), and a fuse (4) provided between the wiring (3) and second electrostatic protection element (1). When the semiconductor device has one semiconductor chip, the wiring (3) and second electrostatic protection element (1) are connected to each other through the fuse (4), and when the semiconductor device has said two semiconductor chips, the fuse (4) is disconnected so that the second electrostatic protection element (1) is electrically disconnected from the wiring (3).

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits.

Abstract: A semiconductor wafer, a method of marking a crystallographic direction on the semiconductor wafer, and a method of processing the marked semiconductor wafer are disclosed. The semiconductor wafer is marked with a scribe line, which in one embodiment is provided with a commercially available scribe tool that is used to cleave III-V type wafers and/or another apparatus that provides a line that is sufficiently narrow to be associated with cleaving the wafer exactly along a predetermined crystallographic plane. Accordingly, the line is also of sufficient narrowness to precisely mark the crystallographic direction. To ensure that the scribe line does not render the marked wafer susceptible to cleavage, the scribe line, or lines, are provided away from the edges of the wafer and with reasonable depths and/or lengths.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.

Abstract: An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substrate layer, the component comprising a first area of a first doping type surrounded with a second intrinsic area, itself surrounded with a third area of a second doping type, the third area being surrounded with a fourth area of the first doping type, the fourth area being surrounded with a fifth intrinsic area, itself surrounded with a sixth area of the second doping type, the third and fourth areas being covered and connected by a metal area, each of the first and sixth areas being connected to a contact pad on which rests a welding ball.

Abstract: On an insulating substrate, a first insulating buffer layer, a heat accumulating-light shielding layer having at least a silicon layer on the surface thereof, a second insulating buffer layer and a first silicon layer are laminated in the order recited from the bottom. The lamination structure of the heat accumulating-light shielding layer, second buffer layer and first silicon layer is patterned. A laser beam is applied the patterned first silicon layer to melt and crystallize the first silicon layer. A thin film transistor is formed by using the crystallized first silicon layer. A polysilicon thin film transistor of high performance and small leak current to be caused by light as well as a display device using such thin film transistors is provided.

Abstract: A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which packages the semiconductor element having the plurality of electrodes, the plurality of bonding portions of the lead frame, and the current path material, wherein the plate-like current path material is arranged to be directly bonded to one of the plurality of electrodes and one of the plurality of bonding portions, and the middle portion of the current path material is formed apart from the surface of the semiconductor element. A method of manufacturing the same is also provided.

Abstract: An integrated circuit package includes EMI containment features. The EMI containment features may include a plurality of pins on a substrate of the integrated circuit package. The pins may be a peripheral row of pins in an array of pins. The pins may couple a lid of the package to at least one ground plane of a circuit board.

Abstract: An integrated circuit package includes a lid with EMI containment features. The lid may include a plurality of projections adapted to couple a ground plane of a circuit board.

Abstract: A molded stiffener for a package substrate is presented. The stiffener includes a molded portion. The molded portion is molded of an electrically nonconductive molding compound. A plurality of capacitors are embedded in the molded portion. The capacitors are constructed and arranged to be electrically connected to the package substrate. As such, power delivery performance is improved, and mechanical strength is added to the substrate.

Abstract: A portable electronic system configured for a secure transaction includes a card having a width, length, and thickness, wherein a ratio of length to thickness is at least 5. The card includes a storage medium to store data and an integrated circuit device (“IC”) including security information. The security information stored in the IC is used to authenticate an access request to the storage medium.

Abstract: A stacked structure includes a substrate, a lower chip, wires, an adhesive layer, an upper chip and a glue layer. A cavity and signal input terminals are formed on the substrate. The lower chip is placed within the cavity and adhered to the substrate. Each wire has a first terminal and a second terminal. The first terminals are electrically connected to bonding pads of the lower chip. The second terminals are electrically connected to the signal input terminals. The adhesive layer is coated on the lower chip. The upper chip has a lower surface and an upper surface formed with bonding pads. The upper chip is adhered to the lower chip by the adhesive layer. The wires electrically connect the bonding pads to the signal input terminals of the substrate. The glue layer is applied to the substrate to encapsulate the upper chip, lower chip and wires.

Abstract: A semiconductor device includes a base substrate including a base wiring pattern. A first circuit substrate is disposed over the base substrate and includes a first wiring pattern. A first semiconductor element is mounted on the first circuit substrate and includes a first electrode that is electrically connected to the first wiring pattern. A second circuit substrate is disposed over the first circuit substrate and includes a second wiring pattern and a second semiconductor element is mounted on the second circuit substrate and includes a second electrode that is electrically connected to the second wiring pattern. A first protruded electrode is electrically connected to the first wiring pattern and provided protruding from the first circuit substrate and bonded to the base wiring pattern and a second protruded electrode is electrically connected to the second wiring pattern and provided protruding from the second circuit substrate and bonded to the base wiring pattern.

Abstract: There is a need to provide a semiconductor device in which strain in a bonding member resulting from the difference in thermal deformation between a lead electrode and a semiconductor chip, which are electrically bonded to each other by the bonding member, is reduced for an improved thermal fatigue lifetime and the semiconductor chip has an improved current carrying capacity and enhanced heat dissipation.

Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Abstract: A method of fabricating a semiconductor package is disclosed in which a first Ni—Au plating is formed on a bonding pad for connection with a semiconductor chip, without a mechanical process or a masking operation. The method applies a copper plating on a through bore and the bonding pad, where the copper plated layer formed on the bonding pad is selectively removed, and then a second Ni—Au plating is formed on the bonding pad and a ball pad.

Abstract: In a semiconductor heat-dissipating substrate made of a Cu—W alloy whose pores have been infiltrated with copper, being a porous tungsten body whose pore diameter at a specific cumulative surface area of 95% is 0.3 &mgr;m or more, and whose pore diameter at a specific cumulative surface area of 5% is 30 &mgr;m or less, thermal conductivity of 210 W/m·K or more is obtained by decreasing the content of iron-family metal to be less than 0.02 weight %. Likewise, changing the amount of infiltrated copper in a molded object by utilizing a multi-shaft press to vary the amount of vesicles in the middle and peripheral portions makes for offering at low cost a semiconductor heat-dissipating substrate that in between middle and peripheral portions made of different materials does not have bonding matter.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads, and the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads that does not electrically connect to anyone of the first pads electrically connects to the interconnection-wiring layer. In another case, a shielding portion, which electrically connects the interconnection-wiring layer, is provided around the second pad that doesn't electrically connect to anyone of the first pads. Furthermore, this invention also discloses a semiconductor device including the substrate.

Abstract: An MCM package with bridge connection mainly comprises a carrier, a first chip, a second chip and at least one conductive body. The carrier has an upper surface and an opposite lower surface, and a plurality of contacts formed on the upper surface of the carrier. The first chip has a first active surface, a first side surface and a first boding pad formed on the first active surface. Similarly, the second chip has a second active surface, a second side surface, and a second boding pad formed on the second active surface. Therein, the first side surface of the first chip is proximate to the second side surface of the second chip, and the first active surface is coplanar to the second active chip. Accordingly, one of the conductive body can be disposed continuously on the active surface and the second surface to electrically connect the first chip and the second chip.

Abstract: An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external parts. Each of these contact members 1201 has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface 1202 on each end and a layer of reflowable material on each end. Each member is solder-attached (1204) at one end to a chip contact pad 903b, while the other end (1203) of each member is operable for reflow attachment to external parts.

Abstract: An electronic component includes a wafer and a number of bond pads disposed on the wafer. A number of functional 3-D structures are disposed on the wafer. Each functional 3-D structure includes a compliant base element. A number of reroute traces are electrically connected to one of the bond pads and extend onto a surface of one of the functional 3-D structures. A number of selected 3-D structures is disposed on the wafer to provide a mechanical reinforcement. At least some of the selected 3-D structures have a greater mechanical load-bearing capacity than some the functional 3-D structures.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a porous insulating film formed above the semiconductor substrate, the porous insulating film having a relative dielectric constant of 2.5 or less and including a first insulating material, at least a portion of pores in the porous insulating film having on the inner wall thereof a layer of a second insulating material which differs in nature from the first insulating material, and a plug and/or a wiring layer buried in the porous insulating film.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film comprising a first insulating film and a second insulating film formed on the first insulating film, the first insulating film comprising a silicon oxide film containing carbon of a concentration, the second insulating film comprising a silicon oxide film containing carbon of a concentration lower than the concentration of the first insulating film or comprising a silicon oxide film containing substantially no carbon, a via contact made of a metal material embedded in a via hole formed in the interlayer insulating film, a diameter of the via hole in the first insulating film being smaller than that in the second insulating film at an interface between the first insulating film and the second insulating film.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory transistors, a plurality of insulating layers disposed over the transistors, and a plurality of metal layers. Each of the metal layers is disposed on one of the insulating layers. The device also includes a plurality of metal plugs disposed over corresponding memory transistors. Each of the metal plugs filling in a contact hole formed in one of the insulating layers and electrically connecting the metal layers disposed on a top side and a bottom side of the corresponding insulating layer. A top metal layer of the plurality of metal layers is configured to provide bit lines that correspond to the memory transistors, the metal plugs are vertically aligned, and one of the insulating layers is configured so that whether one of the memory transistors is connected to a corresponding bit line is determined by whether a metal plug corresponding to the memory transistor exists in the insulating layer.

Abstract: A semiconductor device includes a semiconductor die and a multi-level interconnect structure that has a first insulating layer formed on the die, conductive horizontal bodies, each of which is connected to a respective bonding pad of the die and has an extension formed on the first insulating layer, a second insulating layer formed on the first insulating layer, and conductive vertical bodies, each of which is connected to the extension of a respective conductive horizontal body and extends through the second insulating layer.