Abstract: A manufacturing method for a semiconductor device, including forming on or above a semiconductor substrate a silicon film a surface of which has a first polycrystalline silicon film with mushroom or hemisphere-shaped crystal grains, and forming a Ta2O5 film on the silicon film at a pressure of 40 Pa or lower and at a temperature of 480° C. or lower, using a gas obtained by vaporizing Ta(OC2H5)5 as a tantalum source gas.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

Abstract: A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material (81) reduces diffusion of dopants in the base region during subsequent thermal processing.

Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.

Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240).

Abstract: A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: An SOI wafer includes a substrate, and an insulating intermediate layer and a surface layer successively thereon. At least one laterally limited suicide area is formed in and/or on the surface layer. Then an oxide layer is provided on the surface layer of the SOI wafer and/or on a second silicon wafer, before the two wafers are bonded to each other along the oxide layer. The substrate and the insulating intermediate layer are removed to leave a bonded multi-layered wafer. At least one device component is fabricated in and/or on the surface layer to include the silicide area as a functional element of the device component. Different types of components, e.g. MOS and bipolar transistors, can be fabricated together on the same wafer, and HF characteristics are improved by the low ohmic suicide area(s).

Abstract: Process for producing a tool insert for injection molding a part which is produced from a synthetic material, a metal or a ceramic material and which comprises an arrangement of microstructures which are formed on an outer surface of the part and have a predetermined depth.

Abstract: A semiconductor device manufacturing system for manufacturing a semiconductor device on a wafer, comprising: a first exposure apparatus for exposing the wafer using a light source while moving the wafer with a predetermined interval; and a second exposure apparatus for exposing the wafer by irradiating a plurality of electron beams on the wafer, the plurality of electron beams having an interval of substantially N times or 1/N times, where N is a natural number, of the predetermined interval.

Abstract: A method for making high quality InGaAsN semiconductor devices is presented. The method allows the making of high quality InGaAsN semiconductor devices using a single MOCVD reactor while avoiding aluminum contamination.

Abstract: A chemical vapor deposition (CVD) method for forming a microelectronic layer within a microelectronic product employs a wetting material treatment of a substrate upon which is formed the microelectronic layer. The wetting material treatment provides for an attenuated incubation or induction time when forming the microelectronic layer, particularly within the context of a digital CVD method, such as an atomic layer CVD method. The microelectronic layer is thus formed with enhanced manufacturability.

Abstract: A method of manufacturing a crystalline silicon film excellent in crystallinity. When using elements such as nickel as metal elements that promotes the crystallization of the amorphous silicon film, nickel is allowed to be contained in a solution repelled by the surface of the amorphous silicon film. Then, a part of the amorphous silicon film is removed, and the solution is held in only that part. In this way, the nickel elements are selectively introduced into a part of the amorphous silicon film, and a heat treatment is also conducted to allow crystal growth to proceed from that portion toward a direction parallel to a substrate.

Abstract: A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures. Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure.

Abstract: A metal oxide semiconductor (MOS) capacitor formed according to a process in which Fermi level enhanced oxidation is suppressed by the introduction of nitrogen impurities into an N-doped impurity region is formed to utilize the N-doped impurity region as a lower electrode and includes a capacitor dielectric having a reduced thickness with respect to other portions of the thermal oxide film formed over N-doped impurity regions. The capacitor is highly linear and includes a high capacitance density. The process used to form the capacitor includes thermally oxidizing a substrate such that an oxide film is formed to include multiple thicknesses including an enhanced oxide growth rate producing an oxide film of increased thickness in N-doped impurity regions and a section within nitrogen-doped impurity portions of the N-doped impurity region in which the enhanced oxidation growth is suppressed and the film formed in this region includes a desirably reduced thickness.

Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

Abstract: A method of fabricating a gallium nitride-based semiconductor structure on a substrate includes the steps of forming a mask having at least one opening therein directly on the substrate, growing a buffer layer through the opening, and growing a layer of gallium nitride upwardly from the buffer layer and laterally across the mask. During growth of the gallium nitride from the mask, the vertical and horizontal growth rates of the gallium nitride layer are maintained at rates sufficient to prevent polycrystalline material nucleating on said mask from interrupting the lateral growth of the gallium nitride layer. In an alternative embodiment, the method includes forming at least one raised portion defining adjacent trenches in the substrate and forming a mask on the substrate, the mask having at least one opening over the upper surface of the raised portion. A buffer layer may be grown from the upper surface of the raised portion.

Abstract: Stereolithographically fabricated conductive elements and semiconductor device components and assemblies including these conductive elements. The conductive elements may include multiple superimposed, contiguous, mutually adhered layers of a conductive material, such as a thermoplastic conductive elastomer or a metal. In semiconductor device assemblies, the stereolithographically fabricated conductive elements may electrically connect semiconductor device components to one another. The conductive elements may alternatively comprise conductive traces or vias of circuit boards or interposers.

Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

Abstract: Stereolithographically fabricated conductive elements and semiconductor device components and assemblies including these conductive elements. The conductive elements may include multiple superimposed, contiguous, mutually adhered layers of a conductive material, such as a thermoplastic conductive elastomer or a metal. In semiconductor device assemblies, the stereolithographically fabricated conductive elements may electrically connect semiconductor device components to one another. The conductive elements may alternatively comprise conductive traces or vias of circuit boards or interposers.

Abstract: A device having a landing pad structure on an underside of a device and method for fabricating same. The device is formed from a device layer with at least one landing pad protruding from an underside thereof. The landing pad is attached to the device layer by a plug passing through an opening in the device layer. The device may be attached to the device layer by one or more compliant flexures, which allow the device to rotate in and out of a plane defined by the device layer. The landing pads are fabricated by forming one or more vias through the device layer. An underlying sacrificial layer is then partially etched to form one or more depressions at locations corresponding to locations of the vias in the device layer. The vias and depressions are then filled with a landing pad material to form a structure having one or more landing pads protruding from an underside of the device layer. The sacrificial layer is subsequently removed to release the device.

Abstract: A method for depositing a solder layer or solder bump on a sloped surface. The method includes etching a sloped surface on a planar semiconductor substrate, depositing a solder-wettable layer on the sloped surface, masking the wettabler layer with a coating layer to control the position of the solder deposition, and using an organic film to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.

Abstract: An integrated electronic device having an electric connection between a first electrode of a semiconductor chip and a second electrode of a circuit board. One embodiment according to the present invention is a method for fabricating an integrated electronic device having an electric connection between a first electrode of a semiconductor chip and a second electrode of a circuit board, both surfaces of the first and second electrodes having an adhesive tendency to molten metal, the method comprising the steps of forming a metal bump on the first electrode, the metal bump being made of a soldering metal alloy consisting of a solid phase component and a liquid phase component at an operating temperature; and forming an electric connection between the first electrode and the second electrode by heating the soldering metal alloy so as to adhere to the surface of the second electrode.

Abstract: A hard mask 105 of SiCN is formed on a fluorine-containing carbon film 103. Thus, the adhesion of the hard mask 105 to the fluorine-containing carbon 103 is improved and inhibited from being peeled off. The hard mask 105 of SiCN can hare a higher etch-selectivity than those of conventional hard masks, and can have a lower dielectric constant than that of SiN or SiC.

Abstract: Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: A re-oxidation process of a semiconductor device is described. A substrate having a stacked structure thereon is provided, wherein the stacked structure includes a polysilicon/tungsten silicide interface. A thin CVD oxide layer is formed on the substrate and the stacked structure with a chemical vapor deposition (CVD) process. Then, an oxidation process is performed to form a thermal oxide layer on the substrate and the stacked structure.

Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.

Abstract: A method for preventing a diffused reflection from being generated in patterning a via hole for the metal interconnection is disclosed. The disclosed method includes: forming an insulation layer on a semiconductor substrate, wherein elements for operating a semiconductor device are formed on the semiconductor substrate; forming first photoresist patterns on the insulation layer; etching the insulation layer in order to form a first via hole using the first photoresist patterns and then forming a resulting structure; coating a first anti-reflecting coating layer on the resulting structure with a low viscosity; coating a second anti-reflecting coating layer on the resulting structure with a low viscosity; forming second photoresist patterns on the second anti-reflecting coating layer; and forming a second via hole using the second photoresist patterns.

Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.

Abstract: Disclosed is a method of forming an integrated circuit line on a wafer using a lithographic technique. The method can include forming a photo resist line having a line width smaller than a desired line width of the integrated circuit line. The photo resist line can be reacted with a coating to form a mask line having a line width corresponding to the desired line width of the integrated circuit line and with a smaller line edge roughness (LER) than of the photo resist line.

Abstract: A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

Abstract: A method of manufacturing a semiconductor device comprises steps of: forming a first metal film having a reducing property on a semiconductor substrate; thermal treating the resulting semiconductor substrate for reducing a native oxide film naturally formed on the semiconductor substrate and for forming a first silicide film on the semiconductor substrate; removing an unreacted first metal film selectively; forming a second metal film on the semiconductor substrate; and thermal treating the resulting semiconductor substrate for forming a second silicide film on a surface of the semiconductor substrate which includes a region where the first silicide film is formed.

Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

Abstract: The electromigration resistance of nitride capped Cu lines is significantly improved by treating the exposed planarized surface of inlaid Cu with a plasma containing NH3, depositing a silicon nitride capping layer at reduced temperatures, and then laser thermal annealing in N2 to densify the silicon nitride capping layer. The resulting silicon nitride capping layer also exhibits improved barrier resistance to Cu migration and improved etch stop properties. Embodiments include Cu dual damascene structures formed in dielectric material dielectric constant (k) less than about 3.9.

Abstract: Two sequential treatments within a chemical vapor deposition chamber, or within sequential chambers without a vacuum break, are performed on a copper layer to clean and passivate the copper surface prior to deposition of a copper diffusion barrier layer or a dielectric layer. The first treatment includes an ammonia, a hydrogen, or a hydrocarbon plasma cleaning of the copper surface followed by a short initiation of an organosilane precursor or a thin silicon nitride layer. A copper diffusion barrier layer may then be formed over the pretreated copper surface using an organosilane plasma, with or without a carbon dioxide or a carbon monoxide, or a silane with a nitrogen gas and an ammonia gas. Copper diffusion is retarded and film adhesion is improved for a dielectric layer or a copper diffusion barrier layer on the copper surface.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.

Abstract: Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Abstract: The invention includes a method of treating a predominantly inorganic dielectric material on a semiconductor wafer. A laser is utilized to generate activated oxygen species. Such activated oxygen species react with a component of the dielectric material to increase an oxygen content of the dielectric material. The invention also includes a method of forming a capacitor construction. A first capacitor electrode is formed to be supported by a semiconductor substrate. A dielectric material is formed over the first capacitor electrode. A precursor is provided at a location proximate the dielectric material, and a laser beam is focused at such location. The laser beam generates an activated oxygen species from the precursor. The activated oxygen species contacts the dielectric material. Subsequently, a second capacitor electrode is formed over the dielectric material.

Abstract: A method for forming a contact or via plug is described. A dielectric layer and a patterned photoresist layer are sequentially formed on a substrate. A portion of the exposed dielectric layer is removed to form a first opening. A first liner is formed on the surfaces of the photoresist layer. An anisotropic etching process is conducted using the first liner and the photoresist layer as a mask to remove a portion of the dielectric layer under the first opening to form a second opening incorporating the first opening. A second liner is formed on the photoresist layer covering the first liner. Then, the above etching step is repeated to form a third opening that incorporates the second opening and exposes the substrate. The second liner, the first liner and the photoresist layer are removed, and then a conductive material is filled into the third opening to form a contact or via plug.

Abstract: A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

Abstract: Within a sequential and repetitive thermal oxidation and stripping method for forming a plurality of gate dielectric layers having a maximum numbered plurality of thicknesses upon a semiconductor substrate, there is provided a compensating thermal annealing when forming less than the maximum numbered plurality of thicknesses of the plurality of gate dielectric layers upon the semiconductor substrate. By employing the compensating thermal annealing, the semiconductor substrate is more readily manufacturable in conjunction with related microelectronic fabrications.

Abstract: An aluminium film is formed by sputtering on a ferromagnetic layer made of, e.g., Ni—Fe alloy. The aluminum film is oxidized while an alumina film is deposited on the aluminum film by reactive sputtering, to form a tunneling barrier film. Assuming that the aluminum film has a thickness of 1 nm and the alumina film deposited has a thickness of 0.2 nm, an alumina film having a thickness of about 1.5 nm is formed on the ferromagnetic layer, this alumina film being a lamination of an alumina film which is the oxidized aluminum film and the deposited alumina film. The surface of the ferromagnetic layer is prevented from being oxidized because of the presence of the aluminum film. A thin oxide film such as alumina can be formed in a short time without oxidizing an underlying layer.

Abstract: The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.

Abstract: A method for forming oxynitride layer. The method includes (a) providing a substrate and removing the native oxide layer; (b) forming a nitride layer on the substrate; (c) oxidizing the nitride layer to form an oxynitride layer; and (d) subjecting the oxynitride layer to in-situ annealing. This method inhibits the penetration of boron into the substrate thereby improving the performance of semiconductor devices and production yield.

Abstract: A semiconductor device is manufactured using a SiC substrate. On a semiconductor region a region formed of SiC having an (11-20) face orientation is formed. A gate insulation layer is a gate oxidation layer. The surface of the semiconductor region is cleaned, and the gate insulation layer is formed in an atmosphere containing hydrogen or water vapor. After the gate insulation layer has been formed, the substrate is heat-treated in an atmosphere containing hydrogen or water vapor. This reduces the interface-trap density at the interface between the gate oxidation layer and the semiconductor region.

Abstract: A method for forming patterns of a semiconductor device is disclosed which inhibits collapse of photoresist patterns in photoresist pattern-forming processes of the semiconductor device by forming micro-bends in an anti-reflective film to increase the contact area between a photoresist and the anti-reflective film and, simultaneously prevents critical dimension (CD) alteration of the photoresist pattern by creating micro-bends and double-laminating of anti-reflective films with different refractive indices and light-absorbencies.

Abstract: A method for improving the coating capability of low dielectric layer is disclosed. The method includes steps of an etching stop layer is deposited a semiconductor substrate, an adhesion promoter layer is spun-on the etching stop layer. The pre-wetting process being performed on the adhesion promoter layer to enhance the coating capability of the low-k dielectric layer, and thus improve the coating quality through the pre-wetting process of baked adhesion promoter layer before the low-k dielectric layer is applied.