Patents Issued in July 20, 2004
  • Patent number: 6765771
    Abstract: An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: July 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Dou Ker, Hun-Hsien Chang, Wen-Tai Wang
  • Patent number: 6765772
    Abstract: The present invention determines the ESD event by detecting the voltage value of the power source. The numbers N of the diodes 441 have to follow the condition of: N×VT(0.7)>Vcc (core) Therefore, the diodes 441 will not influence normal operation outside of ESD events. When an ESD pulse is generated, the PN junction of the PMOS transistor is turned on, so the voltage value of Vcc is raised. At this time, the voltage value of Vcc (core) is “Vcc−0.7−N1×(0.7)”, N1 represents the numbers of diodes between Vcc (core) and Vcc, which follows the condition of “N1×(0.7)>Vcc—Vcc (core)” to ensure the diodes remain turned on in normal operation.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hsing Lee, Hung-Der Su
  • Patent number: 6765773
    Abstract: The invention relates to an arrangement for improving the ESD protection in an integrated circuit. In order to achieve an effective use of chip area, it is proposed to connect a passive component between the bonding pad and an integrated circuit, said passive component being arranged over an electrically non-conductive layer and under the bonding pad. In the event of damage to the bonding pad when bonding or testing, only the passive component, at most, is short-circuited, but the functionality of the output driver stage and of the integrated circuit remains unaffected.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: July 20, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Joachim Christian Reiner
  • Patent number: 6765774
    Abstract: A high-impedance-insertion system suppresses load-produced electromagnetic noise from interfering into a power source by coupling the load to the power source through a switch. If the power source is an AC power source, the switch couples to the power source through a storage element and a rectifier, such that the switch is OFF (in the high impedance state) when the rectifier is reversed biased (or in a low impedance state). If the power source is a DC power source, the switch couples to the power source through a storage element and a second switch, such that the switch is OFF (in the high impedance state) when the second switch is ON (in the low impedance state).
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: July 20, 2004
    Assignee: iWatt, Inc.
    Inventors: Mark D. Telefus, Anatoly Shteynberg
  • Patent number: 6765775
    Abstract: A submarine branching unit is disclosed that includes a termination for each of at least three line cables and a termination to sea ground. A relay is positioned between each pair of cable terminations. When current flows between two of the cables, the intermediary relay will become energized and cause a contact to connect the third cable to the sea-ground termination. To avoid dangerous surges in current to sea ground when a relay trips, a current limiter is placed in series with the sea ground termination.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: July 20, 2004
    Assignee: Pirelli Cavi E Sistemi S.p.A.
    Inventor: Alberto Pirovano
  • Patent number: 6765776
    Abstract: Electrical power distribution circuits for motor vehicles incorporate a switching element for controlling the energization of the circuits. Current metering elements associated with each switching element indicate the current drawn by the respective electrical circuits. A microcontroller is provided which provides an activation signal for the switching elements, often in accord with a pulse width modulated duty cycle. The microcontroller implements a circuit protective algorithm which takes as inputs the indication of current drawn by a particular electrical circuit and the duty cycle. An equivalent D.C. current is estimated for determining a heat index for a hypothetical fuse suitable for protecting the circuit. When the heat index exceeds the rating for the fuse the fuse melts.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: July 20, 2004
    Assignee: International Truck Intellectual Property Company, LLC
    Inventor: H. Edward Kelwaski
  • Patent number: 6765777
    Abstract: Overvoltage-protection device, applicable in particular to the low-voltage mains, comprising, between the two lines (1, 2) of the mains, a gas-discharge arrestor (3), a varistor (4) and a thermal-fuse element (5) task with ensuring the thermal disconnection of the device . It includes, in parallel with the varistor (4), a resistor (7) causing, after the short-circuiting of the gas-discharge arrestor (3), the heating of the thermal-fuse element (5) so as to trigger the thermal disconnection of the device.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: July 20, 2004
    Assignee: CITEL
    Inventor: Michel Cantagrel
  • Patent number: 6765778
    Abstract: An integrated circuit capacitor (60) uses multiple electrically conductive stacks (63-68, 70) to optimize capacitance density. A second stack (70) is a first nearest neighbor to a first stack (66). A third stack (65) is a second nearest neighbor to the first stack. Each of the three stacks defines vertices of an isosceles triangle (20) formed in a plane substantially perpendicular to the three stacks. The isosceles triangle does not have a ninety degree angle. The isosceles triangle may also be implemented as an equilateral triangle.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: July 20, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yang Du, Ertugrul Demircan
  • Patent number: 6765779
    Abstract: An EMI feedthrough filter terminal assembly includes a feedthrough filter capacitor having first and second sets of electrode plates, a passageway having a first termination surface conductively coupling the first set of electrode plates, and a second termination surface exteriorly coupling the second set of electrode plates. A conductive ferrule disposed adjacent to the capacitor includes a conductive pad of an oxide resistant biostable material on a surface thereof conductively coupled to the second termination surface. A conductive terminal pin extends through the passageway in conductive relation with the first set of electrode plates, and through the ferrule in non-conductive relation. An insulator is fixed to the ferrule for conductively isolating the terminal pin from the ferrule. A hermetic seal is disposed between the insulator and the ferrule. A second conductive pad may be conductively attached to the terminal pin and to the first termination surface independently of the lead wire.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: July 20, 2004
    Assignee: Greatbatch-Sierra, Inc.
    Inventors: Robert A. Stevenson, Jason Woods, Christine A. Frysz, Richard L. Brendel, Haitong Zeng
  • Patent number: 6765780
    Abstract: An EMI feedthrough filter terminal assembly includes a capacitor having first and second sets of electrode plates, a first passageway having a first termination surface coupling the first set of electrode plates, a second passageway having a second termination surface coupling the second set of electrode plates, and a third termination surface exteriorly coupling the second set of electrode plates. A ferrule is adjacent to the capacitor and includes an oxide resistant biostable conductive pad, i.e., a noble metal pad, on a surface thereof coupled to the third termination surface. A conductive terminal pin extends through the first passageway in conductive relation with the first set of electrode plates. A conductive ground lead extends through the second passageway in conductive relation with the second set of electrode plates. An insulator is fixed to the ferrule for supporting the terminal pin in conductive isolation from the ferrule.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: July 20, 2004
    Assignee: Greatbatch-Sierra, Inc.
    Inventors: Richard L. Brendel, Robert A. Stevenson, Christine A. Frysz, Haitong Zeng
  • Patent number: 6765781
    Abstract: A multilayer capacitor having a dielectric body formed by stacking dielectric sheets. At the outside of the dielectric body are arranged a pair of a first terminal electrode and a second terminal electrode insulated from each other and is arranged at least one first linkage electrode insulated from the first terminal electrode and the second terminal electrode. A first internal electrode is stacked inside the dielectric body via dielectric sheets and is connected to the first terminal electrode. A second internal electrode to be connected to the second terminal electrode is further stacked inside the dielectric body via dielectric sheets. A first polarity conductor to be connected to the first internal electrode through an external first linkage electrode is further stacked inside the dielectric body via dielectric sheets.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: July 20, 2004
    Assignee: TDK Corporation
    Inventor: Masaaki Togashi
  • Patent number: 6765782
    Abstract: A capacitor includes a capacitive element, which is formed by a plurality of metallic electrodes or films and has contact terminals, and a thermo shrinkable cover applied directly on the capacitive element. A method for manufacturing the capacitor includes a step where a thermo shrinkable tube is applied directly on the capacitive element and in a following step the thermo shrinkable tube is heated to shrink it onto the capacitor element to from the cover.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: July 20, 2004
    Assignee: EPCOS do Brazil LTDA
    Inventor: Gilvan Schabbach
  • Patent number: 6765783
    Abstract: This invention provides compositions of the formula Cu3Ta3MO12 wherein M is Al, Ga, Fe, Cr, Sc or mixtures thereof. These compositions have high dielectric constant and low loss over a frequency range of from 1 kHz to 1 MHz.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: July 20, 2004
    Assignee: E.I. du Pont de Nemours and Company
    Inventor: Munirpallam A. Subramanian
  • Patent number: 6765784
    Abstract: A solid electrolytic capacitor has an anode terminal and a cathode terminal for external electrical connection that are formed on one surface of a plate-like or foil-like anode member, and a cathode conductor layer formed such that it covers the area of the one surface of the anode member except for the portion where the anode terminal is secured. A first metal plate or metal foil functioning as the cathode terminal is closely joined to the one surface of the cathode conductor layer so as to cover the one surface of the cathode conductor layer. A second metal plate or metal foil is closely joined to the other surface of the cathode conductor layer so as to cover the other main surface of the cathode conductor layer. The first metal plate or metal foil and the second metal plate or metal foil function to intercept the ventilation between the anode member and the outside.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 20, 2004
    Assignee: NEC Tokin Corporation
    Inventors: Kazumasa Ohya, Satoshi Arai, Takayuki Inoi, Yoshihiko Saiki
  • Patent number: 6765785
    Abstract: The polymer electrolyte composite, for driving an electrolytic capacitor, according to the present invention is a composite body including an electrolyte and an acrylic polymer containing a copolymer of acrylic derivative. The electrolyte includes a polar solvent and a solute including at least one of inorganic acids, organic acids and salts of such acids. The copolymer of acrylic derivative is a polymer of: a first monomer of at least one of a group of monofunctional monomers of acrylic derivatives each having at least one hydroxyl group at a terminal thereof and a polymerizable unsaturated double bond; and a second monomer of at least one of a group of multifunctional monomers of acrylic derivatives each having plural polymerizable unsaturated double bonds. The polymer electrolyte composite has a high ionic conductivity at room temperature together with a high heat resistance, and does not react with electrode foils such as aluminum, and moreover is superior in the easiness of manufacturing and long life.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazumitsu Honda, Nario Niibo, Yuichiro Tsubaki, Junji Ozaki
  • Patent number: 6765786
    Abstract: A niobium powder is provided for producing a niobium capacitor enhanced in the thermal stability of oxide films on niobium, with less leak current and less deterioration of leak current after application of thermal loads. The niobium powder contains form 0.005 to 0.10 mass % of hydrogen and from 0.002 to 5 mass % of sulfur and, further preferably, one or both of magnesium and aluminum in an amount from 0.002 to 1 mass % in total. The specific surface area of the powder is 1 to 10 m2/g and the average particle diameter of the secondary particles is 10 to 200 &mgr;m.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: July 20, 2004
    Assignee: Kawatetsu Mining Co., Ltd.
    Inventors: Tadasu Kirihara, Nobuyuki Sato, Osamu Ebato, Kan Saito
  • Patent number: 6765787
    Abstract: An exemplary device and method for providing electric service are disclosed. The exemplary method for providing construction power during the construction of a facility and providing permanent power at the facility thereafter, includes installing an electric service device of the present invention at a construction site that, when energized, is operable to provide metered construction power through an electrical outlet at the device during construction of the facility and to provide metered permanent power at the facility thereafter. The method includes obtaining inspection approval of the installation of the device, and locking the device to provide metered construction power when energized. The method further includes installing a meter in the device to measure energy consumption of metered construction power and metered permanent power, and energizing the device to provide metered construction power at the construction site.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Basic Resources Inc.
    Inventors: Max Hartwell Beasley, III, Alfred L. Mayfield
  • Patent number: 6765788
    Abstract: An apparatus and a method for integrating personal computer and electronic device functions. An integrated keyboard, personal computer host, and keyboard encoder in turn integrate hardware, operating system, and application programs to provide personal computer and electronic device functions at the same time.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: July 20, 2004
    Assignee: Mitac Technology Corp.
    Inventor: Chia-Chuan Wu
  • Patent number: 6765789
    Abstract: An expansion module of a personal digital assistant is described. The expansion module provides an easy expansion environment and interface for the personal digital assistant. The expansion module has a connecting interface, a network device, a storage device, a power module, and an input/output interface. The connecting interface transmits information between the personal digital assistant and the expansion module. The network device provides a network connecting environment. The storage device provides a larger storage capacity for the personal digital assistant. The power cord provides an external power source and recharge function. The input/output interface connects more external devices. The expansion module further has a monitor, a keyboard, and a mouse so that the personal digital assistant inserted in the expansion module is like a personal computer. The expansion module further has a processor to control the expansion module and transform data to fit each input/output interface requirement.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: July 20, 2004
    Assignee: Quanta Computer Inc.
    Inventor: Yu-Chun Yang
  • Patent number: 6765790
    Abstract: A notebook computer with a metal frame. The notebook computer comprises a housing, a metal frame, and a main board. The housing defines a plurality of first openings. The metal frame defines a plurality of second openings and a groove. Parts of the second openings correspond to the first openings. The main board is disposed on the metal frame, and includes a cable located in the groove of the metal frame.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: July 20, 2004
    Assignee: Quanta Computer, Inc.
    Inventors: Siu-Ming Lam, Cheng-Che Chen
  • Patent number: 6765791
    Abstract: A front input/output module is provided. The front input/output module, as disclosed in this invention, is adapted to a computer, provided with a chassis and a motherboard. The front input/output module comprises a tray, a printed circuit board and at least one interface device. The tray is detachably disposed inside the chassis. The printed circuit board is disposed on the tray and electrically connected with the motherboard. The interface device, having a connector, is disposed on the tray and electrically connected with the printed circuit board. The connector is exposed when the tray is disposed inside the chassis.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: July 20, 2004
    Assignees: Wistron Corporation, Acer Incorporated
    Inventors: Harold Syring, Alan Kyle
  • Patent number: 6765792
    Abstract: A docking station that accepts a portable computing device is disclosed. The docking station comprises a first surface that supports a bottom surface of the portable computing device. The first surface includes a means for restricting the movement of the portable computing device. The docking station additionally includes a body or a trunk that interfaces the portable computing device with an external device. The docking station additionally includes a hinge which joins the first surface to the body or trunk, in which the hinge permits the portable computing device to be rotated between a horizontal and a vertical orientation as well as various acute angles.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: July 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Memphis Zhihong Yin, Glen A Oross
  • Patent number: 6765793
    Abstract: The present invention relates to a ruggedized enclosure for housing and protecting electronics circuits. The enclosure utilizes a top compartment for housing the circuit and a cooling assembly rigidly coupled to the top compartment. The cooling assembly utilizes a passive radiator to form a rigid truss plate structure. The truss plate structure rigidifies the enclosure helping to protect the enclosure and circuit from destructive shock events and destructive vibration events. The cooling assembly further provides an efficient heat exchange for removing heat from the electronic circuit. A method for protecting an electronic circuit utilizing a rigid truss plate structure is also provided.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Themis Corporation
    Inventors: William E. Kehret, Dennis H. Smith
  • Patent number: 6765794
    Abstract: It is an exemplified object of the present invention to provide a heat sink, method of manufacturing the same, and electronic apparatus having the heat sink in which a fine and inexpensive adjustment upon placement and replacement may be made to exoergic components having various shapes and calorific values, and to placement space of various shapes and dimensions. The inventive heat sink comprises a housing, a cooling fin that is separably coupled with the housing, receives heal from the exoergic components, and dissipates heat form the exoergic components, and a cooling fan that forcefully cools the cooling fin and is connected with the housing, each element can be replaced alone.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: July 20, 2004
    Assignee: Fujitsu Limited
    Inventor: Koichi Inoue
  • Patent number: 6765795
    Abstract: A modular computing system that includes an enclosure with a rack. A plurality of modular bricks that each include heat-generating electronic components are mounted in the rack. A fan brick that includes at least one fan is also mounted in the rack. The fan brick exchanges air between each modular brick and the fan brick to cool the electronic components in each of the modular bricks.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: July 20, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Steve Modica
  • Patent number: 6765796
    Abstract: A cover attaches to a circuit board and has an inlet at one side for receiving forced air and plurality of openings on its top surface through which heat sinks mounted on the circuit board partially extend. Air is made to flow into the inlet and out the exhaust openings, thereby concentrating airflow in the vicinity of the circuit board's heat dissipative components.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: July 20, 2004
    Assignee: Teradyne, Inc.
    Inventors: Mark S. Hoffman, David C. Drahms
  • Patent number: 6765797
    Abstract: The present invention relates generally to apparatus and methods for the spreading and dissipation of thermal energy from heat-producing components. More particularly, it relates to a heat transfer apparatus and methods particularly useful in the electrical arts. One embodiment of a heat transfer apparatus include but not limited to, a spring-biased member comprising a first side member, a second side member, and a connecting member adapted for spring-biased removable attachment to a heat-producing device. Another embodiment of a heat transfer apparatus is a spring-biased carrier that attaches to a heat-producing device and which carries a member, such as a finned plate. Another embodiment of a heat transfer apparatus is a spring-biased member comprising fingers for conducting thermal energy to a structure. Another embodiment of a heat transfer apparatus is a spring-biased clip used to attach separate heat-spreading/dissipating members, such as a finned plate, against a heat-producing member.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Intel Corporation
    Inventors: Mark D. Summers, Karl H. Mauritz, Amber S. Bedi, William Handley, Carol Miller, Javier Leija, Daniel Dragoon
  • Patent number: 6765798
    Abstract: A thermal management device is for a electronic apparatus, and includes a thermally conductive member, and elastic and thermally conductive material. The member is for engagement with a heat sinking portion and for conducting thermal energy. The member has two legs that are deflectable relative to each other. The first leg is configured for location proximate to an electronic component and the second leg is configured to extend toward the heat sinking portion. The member has a connecting portion interconnecting the two legs such that thermal energy can travel between the legs, and such that a spacing is provided between the two legs. The elastic and thermally conductive material is located in the spacing between the legs such that the thermal energy can travel from the first leg through the material and to the second leg, and such that the two legs may deflect relative to each other.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: July 20, 2004
    Assignee: Curtiss-Wright Controls, Inc.
    Inventors: William Edward Ratliff, Jacob Leland Sealander
  • Patent number: 6765799
    Abstract: The present invention of a heat dissipating fin pieces interlocking mechanism includes a plurality of aluminum or copper fin pieces wherein the lower center protruding section is bent and folded into a base plate. Also located on center portion fin pieces is a plurality of venting openings; the center portion fin pieces extend on upper and lower ends into a plurality of locking elements where each is fitted with one or two claws. The claws are connected to the center portion fin piece by a perforated protruding section while the closer edge of the protruding section grows into a neck. The neck turns into a folding part with narrowed end. When a multitude of fin pieces are assembled, the narrowed end of folding part from the back fin piece penetrates through the corresponding perforations of the front fin piece locking elements then fold back flat into a secure interlocking position.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: July 20, 2004
    Inventor: Jin-Zong Huang
  • Patent number: 6765800
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 20, 2004
    Assignee: Rambus Inc.
    Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
  • Patent number: 6765801
    Abstract: A package includes a substrate having a pocket, an overflow reservoir around a periphery of the pocket, and a mating surface around a periphery of the overflow reservoir. An electronic component is mounted within the pocket. The pocket is over filled with a flowable material. A window or waveguide is mounted to the substrate. The overflow reservoir captures the flowable material that spills out of the pocket during mounting of the window or waveguide thus preventing contamination of the mating surface.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: July 20, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: Thomas P. Glenn, Roy Dale Hollaway
  • Patent number: 6765802
    Abstract: An audio sound quality enhancer which provides a transparent sound quality, using solid-state devices, which has previously been available only in vacuum tube audio systems. The invention comprises at least one solid-state component in the audio signal path of an audio circuit, and at least one heat source configured to heat the solid-state components. The invention increases the sound quality of solid-state audio systems by increasing the temperature of the semiconductor components involved in sound production. By intentionally heating the semiconductor components of an audio system above standard operating temperatures, the invention delivers sound quality levels normally only associated with vacuum tube sound systems.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: July 20, 2004
    Assignee: Ridley Engineering, Inc.
    Inventor: Ray B. Ridley
  • Patent number: 6765803
    Abstract: A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Larry D. Kinsman, Walter L. Moden
  • Patent number: 6765804
    Abstract: A circuit board arrangement facilitates a direct connection to a chassis mounted connector. The arrangement comprises a printed circuit board with a first signal conductor terminating at an edge of the printed circuit board. A second signal conductor is disposed adjacent to the first signal conductor and terminates at the edge. A conductive metallic spring clip has a relieved area and is formed to fit over the edge of said printed circuit board. The conductive metallic spring clip is positioned on the edge of said printed circuit board such that the relieved area straddles the first signal conductor and the conductive metallic spring clip grips the second signal conductor for coupling the second signal conductor to the chassis mounted connector.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Thomson Licensing S. A.
    Inventors: Don Richard Hudson, Barry Wynn Albright
  • Patent number: 6765805
    Abstract: A circuit component comprising a circuit board and a terminal for mounting the circuit board on a second circuit board. A length of the circuit board is 10 mm-80 mm, a difference in a coefficient of thermal expansion between the circuit board and the second circuit board is 0.2×10−5/° C. or greater. The terminal is made of an elastic material, and comprised of a first connection section, a second connection section and an elastic section disposed between the first and second connection sections, and the terminal separates the circuit board from the second circuit board by 0.3 mm-5 mm. In the circuit components of the present invention, deterioration in the conduction between the circuit board and the second circuit board due to heat cycles can be prevented. Thus, a circuit component having stable operating characteristics for a long period of time is obtained.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takumi Naruse, Kenichi Kozaki, Kazuhiro Eguchi, Katsumi Sasaki
  • Patent number: 6765806
    Abstract: The present invention is directed to a composition with electromagnetic compatibility (EMC) characteristics. In an aspect of the present invention, an adhesive suitable to provide a bond between components may include an adhering material suitable for holding a first surface and a second surface in contact. A plurality of items is disposed in the adhering material. The plurality of items has electromagnetic capability shielding characteristics.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Barry Caldwell
  • Patent number: 6765807
    Abstract: An apparatus is provided for reducing or eliminating a gap defined between adjacent components of an electronic system, thereby reducing electromagnetic interference generated by the electronic system. The apparatus includes a cam having a cam surface positionable adjacent a component of the electronic system. The cam is moveable to an actuated position in which the cam surface applies a force to the component. The apparatus further includes a support mountable to the electronic system. The support engages the cam and facilitates the movement of the cam. The movement of the cam with respect to the support and into the actuated position causes the cam surface to apply the force to the component, thereby reducing or eliminating a gap between the component and an adjacent component of the electronic system.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Unisys Corporation
    Inventors: Kenneth J. Neeld, Terry W. Louth
  • Patent number: 6765808
    Abstract: A power converter includes a transformer disposed between an input circuit and an output circuit. The transformer has primary and secondary windings coupled to the input and output circuit, respectively. Current passing through the input circuit is sensed and fed to a RC (Resistance-Capacitance) circuit which generates a signal proportional in magnitude to the output current sourcing out of the output circuit.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 20, 2004
    Assignee: Broadband Telcom Power, Inc.
    Inventors: Xiao Ping Jin, Jian Ping Fan
  • Patent number: 6765809
    Abstract: A power source including a transformer having a primary coil, a secondary coil, and a feedback coil; a resonance capacitor connected in parallel with the primary coil of the transformer in parallel, a switching unit having an input terminal which receives an input voltage input from the feedback coil of the transformer and which controls a current through the primary coil of the transformer according to the input voltage; and a current detection unit which detects the current in order to turn off the switching unit when the detected current is higher than a predetermined current. An output voltage stabilization circuit controls the input voltage at the input terminal of the switching unit, proportional to a voltage output by the secondary coil of the transformer.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: July 20, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chihiro Komori
  • Patent number: 6765810
    Abstract: A DC-DC power converter is presented. According to one embodiment, the converter includes first and second transformers, and a double-ended input circuit, including first and second primary switches, for generating an alternating voltage across the primary windings of the first and second transformers. The converter also includes a control circuit (such as, for example, a PWM control circuit) for controlling the primary switches such that the primary switches are simultaneously OFF for a first time period during a switching cycle of the converter. In addition, the converter includes first and second synchronous rectifiers. The first synchronous rectifier is coupled to the secondary winding of the first transformer and the second synchronous rectifier is coupled to the secondary winding of the second transformer.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: July 20, 2004
    Assignee: Artesyn Technologies, Inc.
    Inventor: Marty Perry
  • Patent number: 6765811
    Abstract: A new method in the design for an electronic power supply for suppressing signal interference in equipment of an electronic system due to ground current in a ground loop is provided. In a power supply comprising a transformer, a primary circuit, a secondary circuit, and ground conductors, the method is done by connecting the common signal references of secondary side to the ground conductors through a capacitor and an inductor connected in series. The added capacitor is to reject DC and low frequency noise and interference, and the added inductor is to reject high frequency noise and interference. Most noise and interference signals therefore cannot pass through the formed paths. As a result, the degree of signal interference problem is greatly reduced.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: July 20, 2004
    Assignee: Arima Computer Corporation
    Inventor: Chung-Hsing Chang
  • Patent number: 6765812
    Abstract: A memory module architecture that supports Flash and static memory devices in addition to dynamic memory devices. The module architecture of the present invention preferably redefines standard application of chip select signals on existing module architectures to provide requisite signaling to support Flash and static RAM devices. Use of serial presence detect signaling features of standard memory modules is also modified to provide desired identity and parameters of such an enhanced module. Extending the range of supported memory devices in an otherwise standard memory module reduces the need for special designs to accommodate different and evolving types of memory and is therefore particularly applicable to embedded systems where a variety of memory types are often utilized.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: July 20, 2004
    Assignee: Honeywell International Inc.
    Inventor: David R. Anderson
  • Patent number: 6765813
    Abstract: Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: July 20, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roy E. Scheuerlein, J. James Tringali, Colm P. Lysaght, Alper Ilkbahar, Christopher S. Moore, David R. Friedman
  • Patent number: 6765814
    Abstract: Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryuji Nishihara, Hiroyuki Sadakata
  • Patent number: 6765815
    Abstract: The present invention discloses a semiconductor memory device having a multilevel interconnection structure with no conventional limitation on the number of lines. The semiconductor memory device has a multilevel interconnection structure in which column selection lines extending in the Y direction and main word lines extending in the X direction are arranged in different layers. The layer including the column selection lines is disposed under the layer including the main word lines. In the structure, in sub-word driver areas intersecting the X direction, the main word lines are arranged in a top layer and sub-word selection lines are arranged in a layer lower than the top layer. The lower layer includes a pattern of islands. According to this interconnection structure, the number of islands can be reduced. Consequently, a plurality of power lines can be arranged between the adjacent main word lines in the sub-word driver areas.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: July 20, 2004
    Assignees: Elpida Memory, Inc., Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Fujisawa, Koji Arai, Chiaki Dono
  • Patent number: 6765816
    Abstract: Single-ended write circuitry (18) in storage circuit (19) includes transistor (35) which provides aid in transitioning latch node (51) from a logic state “1” to a logic state “0” when latch node (50) is being transitioned from a logic state “0” to a logic state “1”. Similarly, single-ended write circuitry (18) includes transistor (37) which provides aid in transitioning latch node (50) from a logic state “1” to a logic state “0” when latch node (51) is being transitioned from a logic state “0” to a logic state “1”. In some embodiments of the present invention, the effect of transistor (35) may be selectively applied to latch (16). A device, such as transistor (34), may be used to selectively negate the effect of transistor (35). In some embodiments of the present invention, the effect of transistor (37) may be selectively applied to latch (16).
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: July 20, 2004
    Assignee: Motorola, Inc.
    Inventor: Perry H. Pelley
  • Patent number: 6765817
    Abstract: A semiconductor memory which operates at low power supply voltage with lower power consumption without decreasing writes rate is provided. During data read, a virtual ground line VGj provided to correspond to a bit line pair BLj, /BLj of a read target memory cell 11ij is connected to a ground voltage GND through a transistor 31j. As a result, the bit line BLj (or /BLj) corresponding to “L” level is connected to the ground voltage GND through an acceleration circuit AC provided in the memory cell 11ij to thereby accelerate read rate. During data write, the virtual ground line VGj corresponding to the write target bit line pair BLj, /BLj is connected to a power supply voltage VDD through a transistor 33j. As a result, a current is prevented from flowing from the bit line BLj (or /BLj) at “H” level to the virtual ground line VGj and the write rate is not decreased.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: July 20, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takashi Takemura
  • Patent number: 6765818
    Abstract: Each memory cell of an SRAM has normally a pair of inverters cross-connected to each other, a pair of transistors connected to output ends of the inverters respectively, a word line connected to gates of the transistors, and a bit line and an inverted bit line connected to the transistors respectively. To produce a storage data fixing memory cell functioning as that of a ROM from one normal memory cell, an input end of one inverter is disconnected from the output end of the other inverter and is connected to a low electric potential terminal or is connected to a high electric potential terminal. Therefore, preset data can be stored in the storage data fixing memory cell without changing characteristics of the SRAM in the changing of the normal cell memory to the storage data fixing memory cell.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: July 20, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Teruaki Kanzaki, Takashi Utsumi
  • Patent number: 6765819
    Abstract: Magnetic memory devices are disclosed. In one embodiment, the device comprises a memory cell having an easy axis aligned along a first direction, the memory cell being configured so as to be most easily switched from one logic state to another when only receiving a magnetic field along the first direction, and a magnetic biasing element associated with the memory cell, the magnetic biasing element having a magnetic orientation aligned along a second direction different from the first direction.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: July 20, 2004
    Assignee: Hewlett-Packard Development Company, LP.
    Inventors: Manoj Bhattacharyya, Thomas C. Anthony, Frederick A. Perner, Steven C. Johnson
  • Patent number: 6765820
    Abstract: A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Yong Lu, Theodore Zhu, Romney R. Katti