Abstract: There are provided at least one wire, a magnetoresistive effect element having a storage layer whose magnetization direction varies according to a current magnetic field generated by causing a current to flow in the wire, and first yokes provided so as to be spaced from at least one pair of opposed side faces of the magnetoresistive effect element to form a magnetic circuit in cooperation with the magnetoresistive effect element when a current is caused to flow in the wire. Each of the first yokes has at least two soft magnetic layers which are stacked via a non-magnetic layer.

Abstract: A memory cell is formed by an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a first negative differential resistance element provided between the word line and the source of the FET; and a second negative differential resistance element provided between the source of the FET and a second power supply.

Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resistive memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.

Abstract: There is provided a magnetoresistance element in which a shape of a free ferromagnetic layer includes a first portion with a parallelogrammic contour, and second portions that protrude from a pair of opposite corners of the first portion respectively in a main direction parallel to a pair of opposite sides of the first portion, the shape is asymmetric with respect to a line that passes through a center of the first portion and is parallel to the main direction, and an axis of easy magnetization of the free ferromagnetic layer falls within a range defined by an acute angle that a first direction makes with a second direction, the first direction being substantially parallel to the main direction and the second direction being substantially parallel to the longest line segment that joins contours of the second portions.

Abstract: An EEPROM memory cell that includes two floating gate transistors. Each of the drain terminals of the transistors is coupled to a corresponding differential bit line. The source terminal of both transistors are coupled to a common current source or sink. Each of the control gate terminals are coupled to a corresponding word line, which may be the same as or different than the corresponding word line that the other control terminal is connected to. The floating gate transistor may be five-terminal devices that include an additional well terminal. In that case, a different set of bit lines is used to program the EEPROM memory cell as are used to read the EEPROM memory cell. While the drain terminals are coupled to the differential read bit lines, each of the well terminals is coupled to a corresponding differential program bit line.

Abstract: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

Abstract: In a method and system for detecting defective material surrounding a flash memory cell, stressing voltage is applied between a control gate and a well of the flash memory cell. A stress recovery process is then performed on the flash memory cell. Any short circuit, formed through the material between the control gate and at least one of drain and source bit line junctions of the flash memory cell, is detected. The material surrounding the flash memory cell may be an inter-level dielectric material. The present invention may be applied to an array of flash memory cells comprising a flash memory device during testing of the flash memory device before being shipped to the customer.

Abstract: A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative potential, when reading out data from the memory cell is disclosed.

Abstract: A memory element and a device having a processor and a memory element, the memory element being positioned outside of the processor and being connectible to a processor via address and/or data lines, the address and/or data lines are each configured in an LVDS structure having corresponding drivers and receivers, and the drivers and receivers each being integrated in the memory element or in the processor.

Abstract: A semiconductor memory device. One desired word line of a memory unit is turned on according to the row select signal, and a first delay circuit delays the column select signal a first determined time and outputs to a sense amplifier circuit. The sense amplifier circuit senses the desired word line, amplifies and outputs desired data to a latch circuit according to the column select signal. After that, the memory device can start to access the next data. Further, the delayed column select signal is also output to a second delay circuit to delay a second predetermined time as an output enable signal, and the latch circuit outputs the latched data according to the output enable signal.

Abstract: A semiconductor integrated circuit device includes a memory array, address buffer, address decoder, and controller. The memory array includes a memory cell array in which destructive read-out memory cells are integrated. The address buffer outputs an internal address signal corresponding to an input external address signal. The address decoder decodes the internal address signal and outputs a memory cell selection signal on the basis of the decode result. The controller parallel-executes wait processing of keeping the address buffer in a wait state until the lapse of a skew time after transition of the external address signal is detected, and decode processing until the memory cell selection signal changes from an invalid state to a valid state in response to output of the internal address signal.

Abstract: In each word line driver, an output node is precharged to a power supply voltage prior to a row select operation and disconnected from the power supply voltage in the row select operation. Further, each first node is connected to a corresponding second node selectively driven to a ground voltage according to a row address through a control switch that is turned on in the row select operation. In each shift switch, output nodes corresponding to word lines other than a defective word line and spare word lines are connected to a second node of a corresponding word line or a word line adjacent thereto through a plurality of transistor switches selectively turned on in accordance with shift control, respectively.

Abstract: An integrated circuit device includes first and second complementary data line pairs, e.g., global or local I/O data line pairs, disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween. An equalization transistor includes respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair.

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells.

Abstract: MRAM noise stabilizing and reducing apparatus and methods for MRAM sensing operations injects noise generated by activation of a word line (80, 82, 84, 86) into a sense line (128) and a reference line (130). Sense strings (20, 22, 24, 26) addressed by the word line (80, 82, 84, 86) are alternately coupled to the sense line (128) and the reference line (130). Cross coupling reduces the noise injected on the sense lines (128, 130). Cross coupling also balances the noise created by activation of the word line (80, 82, 84, 86) between the sense line (128) and reference line (130). A sense string (20, 22, 24, 26) not addressed by the word line (80, 82, 84, 86) provides a reference signal. A differential amplifier (132) includes circuitry to compare and store a difference between the sense line (128) and the reference line (130). The stored value can be further compared to a second value obtained by reversing the current on the word line (80, 82, 84, 86).

Abstract: In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal delay that is dependent on operating temperature is provided in a synchronization device for a semiconductor memory device. In this manner, the clock signal can be time-tuned in a particular reliable fashion.

Abstract: A memory device includes a substrate, at least a thin film superimposed on the substrate having a plurality of microholes formed in the thin film, with a first microhole having a zero depth designated as digital zero; and a second microhole having a specific depth (such as the microhole formed through the thickness of the thin film) designated as digital one; whereby upon scanning of the microholes by a focused electron beam, the physical property as responded in each microhole will be detected as a digital bit corresponding to the microhole, and the microhole, and the digital data of the memory device will be read or recorded in an easier and cost-saving way.

Abstract: A refresh array activating signal is activated in accordance with a refresh request and specific address bit(s) of a refresh address. Specific lower bit(s) of a refresh address counter is (are) utilized as the specific address bit(s) of the refresh address, and the specific address bit(s) is (are) utilized as upper bit(s) of the refresh address. Thus, in the self-refresh mode, refresh can be performed for a prescribed address region at uniform intervals, with a lengthened refresh interval, consuming less current. A semiconductor memory device is provided which allows current consumption to be distributed on a time basis and to be reduce in a self-refresh mode is provided.

Abstract: A refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same is provided. The refresh circuit includes a refresh pulse generating unit for receiving a clock signal to generate first and second refresh signals, a standby refresh signal generating unit for receiving the second refresh signal and a chip select signal to generate a standby refresh signal, the chip select signal representing an active state and a standby state of the semiconductor memory device, and a word-line pulse generating unit for receiving the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that generated at the active state resulting in a sufficient refresh time at each memory cell.

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract: A highly integrated semiconductor memory device capable of operating at high speed having a plurality of main word lines which extend along a first direction across memory blocks, and sub word lines disposed in each of the memory blocks and subordinate to each of the main word lines. Sub row decoders are provided corresponding to the memory blocks. Each of the sub row decoders has a plurality of sub word select signal lines extending along a second direction and selects one of the sub word lines. First and second signal supply sections, which supply sub word select signals to the sub word select signal lines disposed in the sub row decoders, are provided on either end in the first direction. A block select signal line extending in the sub row decoder along the second direction is connected with the second signal supply section. The second signal supply section generates the sub word select signal based on the potential of the block select signal line.

Abstract: A hole driver for driving a hole in a semiconductor memory device, including a first bank controller for generating a control signal for controlling a X-hole of a first bank in response to a row active signal and a precharge signal for the first bank, a second bank controller for generating a control signal for controlling a X-hole of a second bank in response to a row active signal and a precharge signal for the second bank, a block address enable means for generating a common block address enable signal in response to output signals of the first and the second bank control means and a common block address predecoder for predecoding block address signal for each bank in response to the common block address enable signal.

Abstract: A semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.

Abstract: Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

Abstract: The device comprises km memory cell array blocks arranged in the form of a matrix, divided by x block selecting signals and y block selecting signals, and including a plurality of divided word lines arranged horizontally; a plurality of bit lines for each of the km memory cell array blocks arranged vertically; a plurality of main word lines for a plurality of bit lines for each of the km memory cell array blocks arranged horizontally; km of xy address word lines above or below the km memory cell array blocks; a decoder for decoding a corresponding x block selecting signal among x block selecting signals generated by decoding the x block selecting address and y block selecting signals generated by decoding the y block address to select corresponding m of xy address word lines and for being arranged for each of m memory cell array blocks arranged horizontally among the km memory cell array blocks; km of divided y address lines arranged vertically from the km of xy address word lines to the km memory cell array

Abstract: An antenna apparatus for use in a wristwatch radio communication device equipped with, for example, a PHS is provided. The antenna apparatus includes a loop conductor and a feed. The loop conductor has a given length and connects electrically at one end to a ground plate installed in the wristwatch radio communication device. The feed is disposed between the other end of the loop conductor and the ground plate. This provides a higher horizontal pattern average gain both during conversation and waiting times of radio communication.

Abstract: On a disk-shaped substrate with pits and grooves, a first dielectric layer, a magnetic layer, and a second dielectric layer are formed. A data region used for recording/reproduction includes a plurality of tracks, and is divided into a plurality of segments. Each segment includes a pit region and a groove region. Recording/reproducing tracks are composed of the grooves. Magnetic anisotropy of a magnetic layer positioned on each of lands between the respective recording/reproducing tracks is reduced to a level lower than that of magnetic anisotropy of the magnetic layers positioned on the grooves, so that the recording/reproducing tracks are magnetically separated. On an inner side of an innermost recording/reproducing track and on an outer side of an outermost recording/reproducing track, at least one dummy track is provided, respectively.

Abstract: A repeatable runout compensator that allows a transducer of a servo system in a storage device employing rotating media to follow the eccentricity on the media is disclosed. In exemplary embodiments, the repeatable runout compensator utilizes error values generated by the servo system, which represent the radial and/or axial eccentricity of the media, to generate an output signal having a sinusoidal waveform that is approximately 180 degrees out of phase with the eccentricities and the harmonics of eccentricities on the media.

Abstract: A storage apparatus uses a light beam to reproduce information from a recording medium having an information region with a recording format which includes a header including position information and a recording field including a data field for recording data. The storage apparatus is provided with a light source for emitting the light beam, and a control section for controlling a power L2 of the light beam in a vicinity of a start of the recording field to become higher than a power L3 at the data field of the recording field.

Abstract: An optical disc apparatus including a system controller that receives a recording control command via an interface. A recording control block that receives a recording method command signal indicative of one of recording with verify and real time recording and recording data from the system controller. An optical head that modulates the power of laser beam using a recording pulse sent from the control block and records the recording data on an information recording medium. The recording data is recorded in the information recording medium according to the recording with verify and the real time recording using different recording power respectively, in which under the recording with verify, the recording power determined by recording compensation learning is used, and under the real time recording, the recording power higher than the recording power obtained by the recording compensation learning is used.

Abstract: An optical disc having a power calibration area for calibrating the power of a data recording laser beam. The power calibration area is provided at an inner peripheral part of the disc and has test areas and count areas. The test areas are provided to accomplish trial writing of data, and the count areas are provided to record data representing the use condition of the test areas. Data is recorded on the optical disc, while calibrating the data recording laser beam. The number of the test areas is increased in accordance with an increase in the recording density of the optical disc. The optical disc may be a double-density CD. In this case, the disc has 800 to 1200 test areas. The test areas have the smallest possible size, and the count areas are provided in the smallest possible number. Therefore, the disc can have sufficiently large data regions. Thus, the power of the data recording laser beam can be therefore adjusted many times.

Abstract: A device and method of string a disc-ID on a record carrier. The record carriercomprises tracks. Information is stored on the record carrier. A disc-ID that comprises I groups of disc-ID bits is stored on the record carrier in a scattered way. I comprises at least 1 group. At least one of the I groups of disc-ID bits comprises a plurality of disc-ID bits.

Abstract: An apparatus for writing and/or reading write protection data using a recording medium storing write protection information, and a write protection method and apparatus for protecting data recorded on a recordable and/or rewritable disc from unwanted overwriting or erasing. In order for write protection of a disc in a bare state that is usually used in a cartridge having a recognition switch for write-protection, such as a DVD-RAM, write protection information is recorded in a Lead-in area, a Lead-out area or a recording information area other than a user data area of the disc, and the data is protected from unwanted overwriting or erasing using the write protection information. Also, even though the write protection information stored on a disc does not match the state of a recognition switch of a case for write-protection, the data can be prevented from unwanted overwriting or erasing.

Abstract: The invention relates to methods and devices for forming marks and lands by applying a radiation beam (32) to a recording surface (301) of an optical record carrier (30). Recording strategies are proposed for recording information at high recording speeds. An intermediate power level (P1, P2) is introduced in between the bottom power level (P0) and the write power level (Pw), its value being dependent on the length of the preceding land (151, 152, 153). A raised write power level (PR1, PR2) is also proposed, its value being dependent on the length of the mark to be recorded (241, 242, 243).

Abstract: In a signal detection circuit for an optical disk, a comparator converts an analog HF signal into a digital HF signal by using a slice level. A dropout detection circuit detects a dropout of the digital HF signal. A charge-pump circuit feeds back a slice-level control voltage to the comparator based on a result of the detection by the dropout detection circuit. A voltage follower holds and outputs a voltage stored in the capacitor. A switch is turned OFF when a dropout signal has been detected, and outputs to the voltage follower the voltage that has been stored in the capacitor during an ON state of the switch. A second switch is turned ON when a dropout signal has been detected, and applies an output of the voltage follower to the comparator.

Abstract: A sample of an information signal is periodically generated in response to a sampling clock signal. A level relation between successive ones of the information-signal samples is detected. A peak-corresponding sample is detected among the information-signal samples in response to the detected level relation and in response to a prescribed level range containing a “0” level. A level represented by the detected peak-corresponding sample is outside the prescribed level range. Calculation is made regarding a level difference between information-signal samples immediately preceding and immediately following the detected peak-corresponding sample. A phase error signal is generated in response to the calculated level difference. The sampling clock signal is controlled in response to the phase error signal to lock the sampling clock signal in phase with the information signal.

Abstract: An optical recording and pickup head having a flat plate lens of a staircase type diffraction grating structure is compatible with a DVD and a CD-RW.

Abstract: The invention relates to an arrangement for reading an information carrier (2). The arrangement comprises a read head (4) for scanning the information carrier along a scanning path. The read head thus generates one or more electric signals (VA, VB, VC, VD) in response to a physical pattern recorded along the scanning path. The arrangement comprises one or more electrical conductors (6.2, 6.3, 6.4, 6.5, 6.6) for conveying these signals to a signal processing unit (8). The electrical conductors include one or more signal conductors (6.2, 6.3, 6.5, 6.6) and at least one reference conductor (6.4). The one or more signal conductors (6.2, 6.3, 6.5, 6.6) are coupled to the at least one reference conductor (6.4) via a resistive impedance (R1, R2, R3, R4) and a capacitive impedance (C), which are connected in series.

Abstract: A record and read apparatus, includes a head by which information is read from or written to a recording medium, a guide shaft guiding movements of the head, a base part supporting the guide shaft, a pressing member pressing the guide shaft, and a support member adjustably supporting an end part of the guide shaft against a pressing force of the pressing member so that the end part of the guide shaft has a designated height from the base part, wherein the guide shaft has a notch part and the pressing member comes in contact with the notch part so that the height of the guide shaft from the base part is adjustable.

Abstract: An optical disc and an optical disc drive for the optical disc are provided which are suitable for recording data with a high density. The optical disc D uses both lands and grooves as recording tracks. Each of the tracks consists of one address segment and forty five data segments. The address segment is wobbled at one side thereof. Each of the data segments is a DC groove. The address segment records an address information including a sync signal, frame address, track address and CRC, a tilt pattern and a clock mark. The clock mark is adapted to reflect laser beam in one amount before the mark and in another amount after the mark. The tilt pattern has a different track pitch from those in other areas. The data segments record data magneto-optically.

Abstract: A record carrier (1) is described comprising a servo track (4) indicating an information track (9) intended for recording information blocks represented by marks having lengths expressed in channel bits, which servo track (4) has a periodic variation of a physical parameter. The periodic variation is modulated for encoding record carrier information, such as addresses. The modulation is a bi-phase modulation in which a data bit of the record carrier information is encoded by a first predetermined number of variations of a first phase followed by the same number of variations of a second phase inverse to the first phase. A recording and/or playback device has a demodulator for retrieving data bits of the record carrier information from a first predetermined number of variations of a first phase followed by the same number of variations of a second phase inverse to the first phase.

Abstract: The invention relates to an ATM telecommunication switch for switching telecommunication connections, said telecommunication switch comprising incoming lines, outgoing lines, and a switching field for switching any connection from an incoming line to a desired outgoing line, said switching field comprising inputs for supplying connections to said switching field, and outputs for supplying connections out of said switching field. The telecommunication switch of the invention is characterized in that it comprises a pre-selector provided between said incoming lines and said inputs for connecting a desired incoming one of said telecommunication switch to a desired input of the switching field.

Abstract: A network system composed of a master network synchronization device and a slave network synchronization device. A master network synchronization device transmits hop count information. A slave network synchronization device receives the hop count information from an adjoining network synchronization device, determines a minimum hop count between the device itself and the master network synchronization device based on the hop count information, transmits the minimum hop count as the hop count information, and extracts a clock from the route from which the minimum hop count is received.

Abstract: A feedback-based adaptive network is described wherein at least a portion of the network elements report operating information relating to network conditions to a centralized data store. The information which is reported to the data store is analyzed by a policy engine which includes a plurality of application specific plug-in policies for analyzing selected information from the data store and for computing updated control information based upon the analysis of the information. The updated control information is fed back to selected network elements to thereby affect operation of the selected elements. Additionally the adaptive, feedback-based network of the present invention may include a network quality monitoring system for evaluating performance characteristics or other aspects of the network based upon predetermined standards or criteria.

Abstract: A television or other signal is received via main and duplicate feeds into respective buffers. Should the main feed suffer interruption or disturbance the output is switched at a switch over to the duplicate feed, but in a staged process. Upon initial detection of disturbances read-out from the main buffer is performed using locally generated timing signals in lieu of timing signals obtained from the incoming signal. If however the disturbance s persist the two buffers are synchronized and switchover performed.

Abstract: In a switch with multiple physical links to a destination, data is forwarded to the destination by distributing received data across the physical links. A flow hash is selected for the received data's data flow dependent on a destination address and source address included in the received data. The flow hash selects one of the physical links to the destination for a data flow but potentially a different physical link for a different data flow, thereby forwarding the received data by distributing the received data across the physical links while maintaining frame ordering within a data flow.

Abstract: An apparatus for avoiding head of line blocking in an ATM device includes a scheduler, at least one multicast queue, at least one unicast queue, a multicast session table, a multicast timer, and a problem PHY vector. The methods of the invention include alternate scheduling between multicast queue(s) and unicast queue(s). If a PHY device in a multicast session is inactive, it is skipped and the next PHY in the session is serviced. When the session has serviced all of the active PHYs and there remain only inactive PHYs in the session table, the session is ended. Preferably, a timer is started when only inactive PHYs remain in a session and the session is ended when the timer expires, if not sooner. Preferably, a problem PHY vector is maintained and updated at the end of each multicast session and when PHYs become active. The problem PHY vector includes a list of all of the presently inactive PHYs.

Abstract: A packet switching network, e.g., the Internet, employs bandwidth managers to provide guaranteed bandwidth reservations to paired forwarding and receiving agents interfacing with sending and receiving stations in the transfer of large data files therebetween. The forwarding agents obtain guaranteed reservations from the bandwidth manager for segments of the large data file which are transmitted to the receiving station in accordance with the respective reservations. The receiving agent reassembles the segments into the large data file for delivery to the receiving station. By segmenting the large data files, using guaranteed bandwidth reservations on different links or multiple networks, the transmission of large data files through packet switching networks is accomplished without adversely impacting the service requirements of other network users.

Abstract: A method of dynamically controlling congestion in a wireless communication system. The method generally comprises the steps of: (a) the medium access control layer detecting congestion; (b) the medium access control layer communicating a control message with the data link control layer indicating a congested state; (c) in the congested state, the data link layer placing frames received from a higher layer into a data link layer queue and suspending frame transmission to the medium access control layer; and (d) upon receipt of a control message indicating an uncongested state, the data link control layer sending frames to the medium access control layer.

Abstract: In a wireless communications system, a data link layer and a medium access control layer are connected to each other by data and control paths, where the data path is operable to exchange frames between the data link layer and the medium access control layer and the control path is operable to exchange control messages between the data link layer and the medium access control layer. The data link layer includes a queue for storing frames received from the medium access control layer and the medium access control layer includes a queue for storing frames received from the data link layer. The data link layer is adapted to pass new data frames from a higher layer relative to the data link layer into the data link layer queue and to suspend a retransmission timer upon a congestion message received from the medium access control layer, the congestion message being responsive to a level of stored frames in the medium access control queue.