Abstract: The invention relates to a new RNA polymerase isolated from a Nervous Necrosis Virus.

Abstract: A ferroelectric element having a high Pr and a low Ec and having a good withstand voltage, which is in the form of a thin film using a ferroelectric layer containing insulating particles, is provided. The ferroelectric layer containing the insulating particles is effective to suppress leakage current caused through grain boundaries of crystals, and hence to exhibit a high Pr and a low Ec and a good withstand voltage. The ferroelectric element has a structure in which such a ferroelectric layer in the form of a thin film is sandwiched between electrodes. By incorporating the ferroelectric element in a field effect transistor structure, it is possible to realize a highly integrated semiconductor device for detecting reading or writing.

Abstract: A method of repairing a light-emitting device capable of performing high quality image display even if pinholes are formed when forming an organic compound layer is provided. Device contamination can be prevented during repair. By applying a reverse bias voltage to an organic light emitting element during fixed periods of time, the electric current flowing in the EL element during application of the reverse bias voltage is reduced. Further, by forming a cathode so as to contain as little as possible of the high mobility ions Li and Na, contamination of the device when the reverse bias is applied can be prevented. It is preferable to use AlMg and MgAg for this type of cathode.

Abstract: A method of manufacturing semiconductor device in the method of manufacturing wafer level semiconductor device that can search the defective products from the marking information even when sealing resin is formed on the wafer and a semiconductor device manufactured with the same method. A method of manufacturing wafer level semiconductor comprises a process to seal with a resin material the surface of wafer having the front surface and rear surface and forming a plurality of semiconductor chips on the front surface, a first marking process for marking the position information corresponding to each chip to the region of each chip at the rear surface of the wafer, a process for performing the electrical test to each chip, a second marking process for marking the result of the electrical test to the region of each chip at the rear surface of the wafer and a dicing process for dicing the wafer to each chip.

Abstract: A method including operating an ion implanted to implanting ions in a semiconductor wafer at a first ion dose level; performing a first thermal wave measurement to obtain the first thermal wave value; placing the semiconductor wafer in a rapid thermal annealing furnace and operating the furnace to rapidly heat the semiconductor wafer at a first rate for a first time period and so that the wafer is heated with intent of achieving a wafer temperature of 500° C.; performing a second thermal wave measurement to obtain a second thermal wave value; comparing the difference between the first thermal wave value and the second thermal wave value to a target range of 376.5-382.5 and rejecting the wafer as being outside of an acceptable specification if the difference is outside of the target range.

Abstract: A method of efficiently testing optical chips while still on the wafer is presented. One or more gutters for each chip on the wafer is provided, and either (1) a test signal is applied to the gutter to generate a response from the chip; or (2) a test signal is applied to the chip to generate a response from the gutter, where the gutter is in optical communication with the chip, and can reflect light incident or outgoing light at substantially a ninety degree angle.

Abstract: The method for fabricating a semiconductor includes the steps of: (1) growing a first semiconductor layer made of AlxGa1−xN (0≦x≦1) on a substrate at a temperature higher than room temperature; and (2) growing a second semiconductor layer made of AluGavInwN (0<u≦1, 0≦v≦1, 0≦w≦1, u+v+w=1) over the first semiconductor layer. In the step (1), the mole fraction x of Al of the first semiconductor layer is set so that the lattice constant of the first semiconductor layer at room temperature substantially matches with the lattice constant of the second semiconductor layer in the bulk state after thermal shrinkage or thermal expansion.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, in an inter-layer insulation film disposed on the insolation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: An electro-optical device having high operation performance and reliability, and a manufacturing method thereof. A TFT structure which is strong agains hot carrier injection is realized by disposing a Lov region 207 in an n-channel TFT 203 which forms a driver circuit. Further, Loff regions 217 to 220 and offset region are disposed in an n-channel TFT 304 which forms a pixel section, and a TFT structure of low OFF current value is realized. Further, by reducing the n-type impurity element contained in Loff regions 217 to 220 to approximately 1×1016 to 5×1018 atoms/cm3, further reduction of OFF current can be performed.

Abstract: A method for forming a pixel-defining layer on an OLED panel comprises the following steps: (A) providing a substrate; (B) forming a plurality of first electrodes in parallel stripes on the substrate; (C) coating a layer of non-photosensitive polyimide or polyimide precursor compositions on the substrate; (D) first prebaking said substrate; (E) coating a layer of photoresist compositions on the layer of non-photosensitive polyimide or polyimide precursor compositions; (F) second prebaking the substrate; (G) forming patterns of the photoresist by exposing the substrate to masked radiaion and developing the photoresist; (H) etching the layer of said non-photosensitive polyimide or polyimide precursor compositions to form patterned polyimide or polyimide precursor compositions; (I) releasing or stripping the patterned layer of the photoresist compositions; and (J) baking the substrate with patterned non-photosensitive polyimide or polyimide precursor compositions to form the pixel-defining layer.

Abstract: In the light emitting device having, a light emitting layer portion and a current spreading layer, respectively composed of a Group III-V compound semiconductor, formed on a single crystal substrate, the light emitting layer portion is formed on the single crystal substrate by the metal organic vapor-phase epitaxy process, and on such light emitting layer portion the current spreading layer is formed by the hydride vapor-phase epitaxy process. A high-concentration doped layer is also formed in a surficial area including the main surface on the electrode forming side of the current spreading layer, so as to have a carrier concentration of p-type dopant higher than that in the residual portion of the current spreading layer.

Abstract: In one embodiment a micro device is formed by depositing a sacrificial layer over a metallic electrode, forming a moveable structure over the sacrificial layer, and then etching the sacrificial layer with a noble gas fluoride. Because the metallic electrode is comprised of a metallic material that also serves as an etch stop in the sacrificial layer etch, charge does not appreciably build up in the metallic electrode. This helps stabilize the driving characteristic of the moveable structure. In one embodiment, the moveable structure is a ribbon in a light modulator.

Abstract: An accelerometer chip (202) has a molded thermoplastic cap (210) applied on one surface to provide a cavity into which the cantilevered mass (204) of the accelerometer may move. An array of caps is applied to a wafer of accelerometer chips (202) before singulation of the wafer.

Abstract: A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the etch mask layers, where through-holes are formed completely through the etch mask layers only where the first and second trenches intersect. The first and second trenches are made by the formation and subsequent removal of very thin vertical layers of material. The width dimensions of the trenches, and therefore of the through-holes, are sub-lithographic because they are dictated by the thickness of the thin vertical layers of material, and not by conventional photo lithographic processes used to form those vertical layers of material. The sub-lithographic through-holes are then used to etch sub-lithographic sized contact holes in underlying semiconductor materials.

Abstract: A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end.

Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.

Abstract: A method for forming a wafer package includes forming a die structure, wherein the die structure includes a first wafer, a device mounted on the first wafer, a second wafer mounted atop the first wafer with a first seal ring around the device and a second seal ring around a via contact. The method further includes forming a trench in the second wafer around the first seal ring, filling the trench and the via contact with a sealing agent, patterning a topside of the second wafer to removed the excessive sealing agent and to expose a contact pad of the via contact, and singulating a die around the first seal ring.

Abstract: A semiconductor device includes, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed, and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the first chip top surface is fixed on the die pad bottom surface, the second chip bottom surface is fixed on the die pad top surface.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located.

Abstract: A method for separating dies on a wafer includes etching channels around the dies on a first side of the wafer, mounting the first side of the wafer to a quartz plate with an UV adhesive, and grinding a second side of the wafer until the channels are exposed on the second side of the wafer. At this point, the dies are separated but held together by the UV adhesive on the quartz plate. The method further includes mounting a second side of the wafer to a tack tape, exposing UV radiation through the quartz plate to the UV adhesive. At this point, the UV adhesive looses its adhesion so the dies are held together by the tack tape. The method further includes dismounting the quartz plate from the first side of the wafer and picking up the individual dies from the tack tape.

Abstract: An apparatus and method for preventing damage to tape attachment semiconductor assemblies due to encapsulation filler particles causing damage to a semiconductor die active surface and/or to a corresponding semiconductor substrate surface by providing an adhesive tape which extends across areas of contact between the semiconductor die active surface and the semiconductor substrate. The present invention also includes extending the adhesive tape beyond the areas of contact between the semiconductor die active surface and the semiconductor substrate to provide a visible surface of visual inspection of proper adhesive tape placement.

Abstract: A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the electrically connected state in series, using conductors 330, 320, and 310, and contacts 351 and 352. The circuit 300 is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

Abstract: An exemplar method for making a resistive memory element generally includes providing a generally plateau-shaped insulating structure, the insulating structure having a first side wall, a second side wall and a central region disposed between the side walls, depositing a first conductive material on the insulating structure, removing the first conductive material from the central region of the insulating structure to form a first conductor on the first side wall of the insulating structure and a second conductor on the second side wall of the insulating structure, depositing anti-fuse material on the first conductive material and on the central region of the insulating structure, and depositing a second conductive material on the anti-fuse material.

Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to included at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.

Abstract: A driver circuit integration type (monolithic type) active matrix display device having high performance is formed by using thin film transistors (TFT). While a nickel element is added t an amorphous silicon film 203, a head treatment is carried out to thereby crystallize the amorphous silicon film. Further, by carrying out a heat treatment in an oxidizing atmosphere containing a halogen element, a thermal oxidation film 209 is formed. At this time, cyrstallinity is improved and gettering of the nickel element proceeds. TFTs are formed by using the thus obtained crystalline silicon film, and various circuits are constituted by using the TFTs, so that a data driver circuit capable of driving the active matrix circuit having the dot number of fifty thousands to three millions can be obtained.

Abstract: A small semiconductor display device of low power consumption and with high definition/high resolution/high image quality is provided. The semiconductor display device according to the present invention comprises a pixel matrix circuit, a data line driver circuit and scanning line driver circuits, and these components are formed on the same substrate using a polycrystalline TFT. The fabricating method of the device which includes a process for promoting crystallization by a catalytic element and a process for gettering the catalytic element provides the semiconductor display device with high definition/high resolution/high image quality while it is small in size.

Abstract: A method of fabricating poly crystalline silicon type thin film transistor is disclosed. In the method, before the step of re-crystallization of amorphous silicon to form polycrystalline silicon active pattern, a step for injecting predetermined amount of oxygen atom into the surface part of the amorphous silicon layer. By this addition of step, the surface part of the silicon layer is to be oxidized and the crystal defect in the interface between the gate insulating layer and poly crystalline silicon layer can be cured and the mobility of charge carrier can be improved in the channel of the thin film transistor.

Abstract: Metal silcides form low resistance contacts on semiconductor devices such as transistors. Conventional formation of semiconductor devices with metal silicide contacts requires multiple high temperature annealing steps, which can result in crystal damage from dislocations and increased leakage currents. A single, lower temperature annealing step is employed in the invention to produce semiconductor devices with the source/drain regions formed in amorphous regions of a semiconductor substrate and nickel silicide contacts over the source/drain regions. The amorphization of the source/drain regions allows a lower temperature anneal to be performed, and the use of nickel silicide permits a single anneal to be used to both activate the dopants and form the nickel silicide contacts.

Abstract: A laser annealing mask is provided with cross-hatched sub-resolution aperture patterns. The mask comprises a first section with aperture patterns for transmitting approximately 100% of incident light, and at least one section with cross-hatched sub-resolution aperture patterns for diffracting incident light. In one aspect, a second mask section with cross-hatched sub-resolution aperture patterns has an area adjacent a vertical edge and a third mask section with cross-hatched sub-resolution aperture patterns adjacent the opposite vertical edge, with the first mask section being located between the second and third mask sections. The section with cross-hatched sub-resolution aperture patterns transmits approximately 40% to 70%, and preferably 50% to 60% of incident light energy density. In some aspects, the section with cross-hatched sub-resolution aperture patterns includes a plurality of different cross-hatched aperture patterns.

Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel layer. A first ohmic contact is provided on the barrier layer-to provide a source electrode and a second ohmic contact is also provided on the barrier layer and is spaced apart from the source electrode to provide a drain electrode. A GaN-based cap segment is provided on the barrier layer between the source electrode and the drain electrode. The GaN-based cap segment has a first sidewall adjacent and spaced apart from the source electrode and may have a second sidewall adjacent and spaced apart from the drain electrode. A non-ohmic contact is provided on the GaN-based cap segment to provide a gate contact. The gate contact has a first sidewall which is substantially aligned with the first sidewall of the GaN-based cap segment.

Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.

Abstract: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Abstract: Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist is formed so as to cover a low voltage operation region, a second LDD implantation process of implanting an impurity ion by using the resist as a mask, is performed over a silicon oxide film thereby to form an impurity diffusion region in the surface of a semiconductor substrate in a high voltage operation region. After this step, the silicon oxide film in the high voltage operation region contains the impurity during the second LDD implantation process whereas the silicon oxide film in a low voltage operation region contains no impurity.

Abstract: The present invention provides a method of manufacturing an electronic device provided with metal regions, that are mutually separated by air spaces. In the method a first isolating layer, a seed layer and a second isolating layer are provided before applying metal regions. The seed layer and the second isolating layer are only removed after the provision of the metal regions. The method can be advantageously applied for the manufacture of a multilevel interconnect structure and for the manufacture of micro-electromechanical elements.

Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.

Abstract: A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location.

Abstract: An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip, and a second conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip. The first and second conductive layers provide addressing and data retrieval between the memory portion and the periphery portion.

Abstract: The invention includes a method of making a programmable memory device. At least one floating gate layer is formed over a semiconductor substrate. A dielectric material is formed over the at least one floating gate layer, and a mass consisting essentially of W is formed over the dielectric material. The mass has a pair of opposing sidewalls. A first layer is formed over the mass and along the sidewalls of the mass, and a second layer is formed over the first layer. The second layer extends over the mass and along the sidewalls of the mass, and has a different composition than the first layer. After the second layer is formed, the first and second layers are anisotropically etched to form sidewall spacers extending along the sidewalls of the mass.

Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.

Abstract: A double diffused MOS (DMOS) transistor structure is provided that uses a trench trough suitable for high-density integration with mixed signal analog and digital circuit applications. The DMOS device can be added to any advanced CMOS process-using shallow trench isolation by adding additional process steps for trench trough formation, a trench implant and a P-body implant. The trench trough and trench implant provide a novel method of forming a drain extension for a high-voltage DMOS device.

Abstract: A method of forming a select line in a NAND type flash memory device is disclosed. In the select line having a stack structure of the floating gate, the dielectric film and the control gate, the control gate is patterned so that a first projection is formed at the edge of the control gate, and the floating gate is formed by means of the self-aligned etch process. At this time, the floating gate is patterned so that a second projection the one end of which overlaps the first projection is formed at the edge of the floating gate. Next, the first and second projections are electrically connected using the contact plugs and the metal line, whereby a voltage is simultaneously applied to the control gate of a low resistance and the floating gate of a high resistance.

Abstract: A method of fabricating trench power MOSFET is described. A first etching step is performed on a substrate to form a plurality of trenches and the substrate has a first doped region and a second doped region and serves as a drain region. A gate oxide layer and a polysilicon layer are then sequentially formed on the second doped region to create a gate region. Subsequent performance of a second etching step utilizes a mask layer to overlap the polysilicon layer. A portion of the second doped region is exposed and the exposed portion defines a base region. The polysilicon layer is etched to expose the gate oxide layer and the base region is simultaneously etched to remove a portion of the second doped region to expose the first doped region for forming an aligned source region. A contact region in the source region is finally formed to fabricate the trench power MOSFET.

Abstract: Disclosed is a method of improving smoothness on a surface of a gate dielectric composed of a high dielectric film made of metal oxide. A dielectric film with a high permittivity made of metal oxide such as a TiO2 film or a ZrO2 film having an amorphous structure is deposited over a silicon substrate by the plasma enhanced chemical vapor deposition method, and the film is used as a gate dielectric. Since the gate dielectric has good surface smoothness, simultaneous reductions of both the film thickness of a gate dielectric and the gate leakage current can be achieved. In addition, it is also possible to reduce the variation in the characteristics of the devices.