Abstract: A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1-x) of silicon, wherein x is greater than about 0.2. A method of forming the disposal spacer includes providing a device structure and forming a layer of germanium-silicon alloy on the device structure. The layer is then etched to form the disposable spacer. The device structure may include a substrate and a gate structure with the disposable spacers formed at sidewalls thereof. Further, the device structure may include a substrate having an oxidation mask formed thereon with the disposable spacers formed relative to sidewalls of the oxidation mask. In addition, the method includes removing the disposable spacer by oxidizing the spacer to form volatile GexSiyO. Any unvolatilized GexSiyO may be removed using water.

Abstract: In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.

Abstract: The present disclosure provides a method and system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. The method includes defining an electrode on a substrate, forming a spacer adjacent to at least one sidewall of the electrode, and performing a processing operation on the substrate. The processing operation, which can be an ion implantation process, can use the spacer as a mask, and as a result can create a layer, such as a polymer, on the spacer. The spacer can then be removed by applying a first dry etch process to remove the layer on the spacer and a second wet etch process to remove the spacer. The first dry etch utilizes a fluorine-contained plasma, such as one that uses a CF4, CHF3, CH2F2, or CH3F etchant. A third wet etch process can be used to remove an oxide layer underlying the spacer.

Abstract: A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e.g., for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.

Abstract: A method of producing a hetero-junction bipolar transistor includes: laminating semiconductor layers that are to be a subcollector layer, a collector layer, a base layer, an emitter layer and an emitter cap layer successively on one surface of a semi-insulating substrate; and forming an electrode layer on the emitter cap layer. The method also includes adjusting the shape of the emitter cap layer to be a predetermined shape by wet etching; and removing end portions of the electrode layer so that the edges of the electrode layer are substantially aligned to the edges of the top face of the emitter cap layer. Furthermore, the method includes removing a surface oxidized layer formed on the emitter layer. Thus, defective etching of the emitter layer including an element P of group V is resolved, and a hetero-junction bipolar transistor having predetermined properties can be produced stably.

Abstract: A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced width is achieved without the need of using advanced lithographic tools and/or advanced photomasks.

Abstract: A trench capacitor is formed with an insulation collar. After the formation of the trench, firstly an insulating layer is deposited, from which layer the insulation collar will be subsequently formed. Afterward, the trench is partly filled with a sacrificial filling material and a thin patterning layer is deposited thereon. Spacers are formed from that layer and cover the insulating layer in the upper region of the trench. Afterward, the sacrificial filling material and the insulating layer are completely removed in the lower region of the trench. As a result, the insulation collar is produced in the upper region of the trench.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: A method for fabricating a semiconductor device is disclosed. A spacer is formed on the sidewall of the contact hole in which a storage node contact plug is buried. An etch barrier film and an insulating film are sequentially formed after the formation of the storage node contact plug. The insulating film and the etch barrier film are sequentially etched to form an opening part. Then a storage node is formed within the opening part which has been formed by an etching. Then prominences are formed on the surface of the storage node.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

Abstract: A method for depositing a dielectric in a trench on a semiconductor substrate is provided. The dielectric is deposited by using an HDP-CVD system and performing a deposition of first and second layers of dielectric material. A first inert gas is utilized during the deposition of the first layer, and a second inert gas is utilized during the deposition of the second layer. Generally, a purge step is performed between the deposition of the first and second layers. The resulting dielectric layers are substantially free of voids and have low particle counts. Structures utilizing the filled trenches are also disclosed.

Abstract: The present invention makes it possible to transfer thin film devices such as integrated semiconductor and optical components from a first substrate onto a second substrate through a thermal process at high temperature, without degradation of device performance. Other devices can be fabricated thereafter on the other side of the second substrate. Since the semiconductor and optical components can be transferred onto the second substrate in a single-step thermal process, in comparison with prior art the number of transfer substrates needed in the fabrication process can be effectively reduced, thus simplifying the fabrication process and realizing cost reduction.

Abstract: A method of fabricating a semiconductor device on a semiconductor wafer includes: adhering a carrier plate on an upper surface of the semiconductor wafer via a double-faced protective tape; and thereafter grinding an undersurface of the semiconductor wafer, which includes a circuit pattern formed on the upper surface, to reduce the thickness of the semiconductor wafer.

Abstract: A thick wafer is diced by partially dicing a first side to form a first dice, flipping the wafer so that the first side is now in contact with a dicing tape, and dicing a second side. The dicing of the second side may be achieved by aligning a dicing tool to the first dice and/or alignment marks on the wafer. The thick wafer may be a composite wafer including two or more wafers bonded together. These two wafers may be different thicknesses and/or different materials.

Abstract: Techniques for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices.

Abstract: Bumps electrically connected to elements are formed on the main surface of a wafer on which the elements are formed and grooves with depths which do not reach the back surface of the wafer are formed in the wafer on the main surface side thereof along dicing lines or chip dividing lines of the wafer. The bump forming surface of the wafer is coated with a seal member and a back side grinding process for the wafer is performed to make the wafer thin, and at the same time, divide the wafer into individual chips. One of the chips which are discretely divided by performing the back side grinding process is picked up, the bumps of the picked-up chip are bonded and mounted to and on a base board, and at the same time, the seal member is melted for sealing.

Abstract: A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer.

Abstract: A method of controlling the resistivity of gallium nitride is disclosed. The method incorporates an MBE system and utilizes solid source gallium, gaseous source nitrogen and solid source Buckminster Fullerene C60 as a carbon dopant for the GaN film. A desired, predetermined GaN film resistivity can be created during the growth process by selecting the temperature of the effusion cell containing the C60 within a predetermined range so as to impart the desired resistivity in the GaN film.

Abstract: A method of forming a doped polycrystalline silicon gate in a Metal Oxide Semiconductor (MOS) device. The method includes forming first an insulation layer on a top surface of a crystalline silicon substrate. Next, an amorphous silicon layer is formed on top of and in contact with the insulation layer and then a dopant is introduced in a top surface layer of the amorphous silicon layer. The top surface of the amorphous silicon layer is irradiated with a laser beam and the heat of the radiation causes the top surface layer to melt and initiates explosive recrystallization (XRC) of the amorphous silicon layer. The XRC process transforms the amorphous silicon layer into a polycrystalline silicon gate and distributes the dopant homogeneously throughout the polycrystalline gate.

Abstract: A method of forming at least one aluminum/copper clad interconnect comprising the following steps. A substrate is provided having an overlying patterned dielectric layer. The patterned dielectric layer having at least one lower opening. The at least one lower opening is lined with a first barrier layer. At least one planarized copper portion is formed within the at least one first barrier layer lined lower opening. A patterned layer is formed over the at least one planarized copper portion and the patterned dielectric layer. The patterned layer has at least one upper opening exposing at least a portion of the at least one planarized copper portion. The at least one upper opening is lined with a second barrier layer. At least one aluminum portion is formed within the at least one second barrier layer lined opening to form the at least one aluminum/copper clad interconnect.

Abstract: A method for replacing a microelectronic spring contact bonded to a terminal of a substrate is disclosed. The method includes removing the microelectronic spring contact from the terminal, such as by cutting the microelectronic spring contact in two adjacent to the terminal. Then, a bonding material, such as a solder paste, is applied to the terminal and a replacement spring contact is positioned on the bonding material. The bonding material is then cured to fix the replacement spring contact in place. The replacement spring contact includes a base configured to fit on or over any protruding material left on the terminal, and at least one resilient cantilever arm extending from the base. In an embodiment of the invention, the base includes at least two legs extending from the base in a direction opposite to the cantilever arm. In an alternative embodiment, the base of the replacement spring contact has a flat bottom, or one or more recesses to receive protrusions on the terminal.

Abstract: An interconnect structure for microelectronic devices includes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.

Abstract: A method of forming a buried wiring comprising the steps of: (A) forming a wiring and a first insulating layer filled between the wirings on a substratum, (B) immersing the first insulating layer in a fluid which can dissolve the first insulating layer, to dissolve the first insulating layer into the fluid, (C) substituting, for the fluid, a raw material solution containing a raw material for forming a second insulating layer, without bringing the wiring into contact with a gas, and (D) filling a second insulating layer formed by gelation in the raw material solution at least between the wirings, and then, drying off the raw material solution, thereby to form the second insulating layer at least between the wirings.

Abstract: A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole—dipole interaction occurs between the first insulating layer and the buffer layer.

Abstract: A substrate is prepared whose surface has a partial area exposing an insulating material containing fluorine and at least a partial area in the other area exposing a conductive material containing copper as a main composition. The surface of the substrate is exposed to hydrogen plasma to clean the surface. A first insulating film made of insulating material is formed on the cleaned surface. It is possible to form a lamination structure having a fluorine-doped interlayer insulating film hard to be peeled off.

Abstract: A semiconductor device having a multi-layer interconnection structure including bottom interconnects and top interconnects including a first top interconnect having a maximum thickness and a second top interconnect having a thickness thinner than that of the first top interconnect. Thereby, optimization of the parasitic capacitance and the parasitic resistance depending on the demand on the circuit operation and the interconnect length can be attained.

Abstract: Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.

Abstract: The present invention discloses a method for forming a multi-layer metal line of a semiconductor device, including the steps of: (a) forming a first insulating film having a low dielectric constant on a semiconductor substrate having a lower metal line thereon; (b) forming and planarizing a first oxide film on the first insulating film; (c) etching back the first oxide film and the first insulating film until a predetermined thickness of first insulating film remains on the lower metal line; (d) forming and planarizing a second insulating film having a low dielectric constant on the entire surface of the resulting structure; (e) forming a second oxide film on the second insulating film; (f) selectively etching the second oxide film and the first and the second insulating films to form a via contact hole exposing the lower metal line; (g) forming an adhesive film/diffusion barrier film on the entire surface of the resulting structure; and (i) forming a contact plug filling the via contact hole, and forming an

Abstract: A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables.

Abstract: A method of manufacturing a semiconductor device including forming an insulator layer on an integrated circuit, forming a barrier layer having a first titanium film and a titanium nitride film on the insulator layer, heat-treating the barrier layer to release nitrogen gas from the titanium nitride film, forming a second titanium film on the barrier layer, and forming an aluminum film used as a wired metal on the second titanium film.

Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: A multilayered copper structure has been provided for improving the adhesion of copper to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The multilayered copper structure comprises a thin high-resistive copper layer to provide improved adhesion to the underlying diffusion barrier layer, and a low-resistive copper layer to carry the electrical current with minimum electrical resistance. The invention also provides a method to form the multilayered copper structure.

Abstract: A recess is formed in an insulating film, and then a conductive film is deposited over the insulating film so as to fill the recess. Thereafter, a heat treatment is performed on the conductive film. Subsequently, the conductive film is partly removed both before and after the step of performing the heat treatment.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming an insulating film on a conductive pattern formed on a substrate; forming a resist pattern on the insulating film; performing etching to the insulating film using the resist pattern as a mask to form in the insulating film an opening at which part of the surface of the conductive pattern is exposed; forming an antioxidant layer on the part of surface of the conductive pattern exposed while removing the resist pattern; and depositing a conductive film on the conductive pattern from which the antioxidant layer has been removed.

Abstract: A method for protecting a silicon semiconductor wafer backside surface for removing polymer containing residues from a wafer process surface including providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas.

Abstract: It is an object of the present invention to provide a polishing method, with which a surface of high flatness can be obtained without fail at a high removal rate and in a stable manner. The polishing method is to polish a surface to be polished of an object to be polished by using a polishing pad while existing an aqueous chemical mechanical polishing solution containing an oxidizing agent such as hydrogen peroxide between polishing surface of the polishing pad equipped with a polishing part that contains abrasive, and the surface to be polished to be polished of the object to be polished. The aqueous chemical mechanical polishing solution may be contained a heterocyclic compound, a multivalent metal ion, an organic acid and the like. Also, the aqueous chemical mechanical solution may be contained no abrasive.

Abstract: A method for reducing preferential chemical mechanical polishing (CMP) of a silicon oxide filled shallow trench isolation (STI) feature during an STI formation process including providing a semiconductor wafer having a process surface including active areas for forming semiconductor devices thereon; forming a silicon oxynitride layer over the process surface for photolithographically patterning STI trenches around the active areas; photolithographically patterning STI trenches around the active areas for anisotropic etching; anisotropically etching the STI trenches extending through the silicon oxynitride layer into the semiconductor wafer; depositing a silicon oxide layer over the silicon oxynitride layer to include filling the STI trenches; and, performing a CMP process to remove the silicon oxide layer overlying the silicon oxynitride layer to reveal an upper surface of the silicon oxynitride layer.

Abstract: In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.

Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers.

Abstract: After forming a groove in a surface portion of a substrate, a deposited film is formed on the substrate so as to fill the groove. The deposited film is subjected to a first stage of chemical mechanical polishing with a relatively high rotation speed and a relatively low pressure, so as to eliminate an initial level difference formed in the deposited film due to the groove. After eliminating the initial level difference, the deposited film is subjected to a second stage of the chemical mechanical polishing with a relatively low rotation speed and a relatively high pressure, so as to remove a portion of the deposited film present outside the groove.

Abstract: A new method is provided for the etch of ultra-small patterns in a silicon based surface. Under the first embodiment, a hardmask layer over a substrate and a layer of ARC over the hardmask layer are successively patterned. The patterned layer of ARC is removed, the remaining patterned hardmask layer is used as a mask for etching the substrate. Under the second embodiment, a first hardmask layer over a substrate, a second hardmask layer over the first hardmask layer and a layer of ARC over the second hardmask layer are successively patterned. The patterned layer of ARC and the second hardmask layer are removed, the remaining first patterned hardmask layer is used as a mask for etching the substrate.

Abstract: In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates.

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 &mgr;m and having a platinum profile equal to or greater than about 85°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the platinum electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising chlorine, argon and a gas selected from the group consisting of BCl3, HBr, and mixtures thereof. A semiconductor device having a substrate and a plurality of platinum electrodes supported by the substrate. The platinum electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 &mgr;m and a platinum profile equal to or greater than about 85°.

Abstract: A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.

Abstract: Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Abstract: A method for fabricating a semiconductor device comprises forming a material layer on a wafer having a plurality of independent pattering regions, and patterning the material layer to form a material pattern. The material layer is patterned such that the material patterns have different line widths in a plurality of the independent patterning regions. Pattering the material layer comprises a plurality of photolithographic processes or a plurality of etching processes, which are separately applied to each of the patterning regions. The photolithographic processes are preferably applied to each of the independent pattering regions using different reticles. The reticles have different line widths and circuit patterns of the same design. The etching processes are preferably applied to each of the independent pattering regions using different etch recipes.

Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.

Abstract: A method for forming porous silicon oxide film, comprising the following steps. A CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon oxide film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.