Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A TFT liquid crystal display device is disclosed, which includes two substrates and a liquid crystal layer provided in between the substrates, one substrate having a surface providing with a plurality of data signal lines, a plurality of scan lines, a plurality of pixel electrodes, and a plurality of functional components having source electrode, gate electrodes and drain electrodes. Moreover, the projection of one of the signal electrode and the drain electrode on the gate electrode having at least one bridging zone and one conducting zone. The width of the bridging zone in the direction in parallel to one side of the gate electrode is smaller than the width of the conducting zone in the direction in parallel to the side of the gate electrode.

Abstract: A semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a semiconductor element in which the semiconductor region serves as an active region; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, located over the entire interface between the rest of the semiconductor region and the insulating layer, and having side surfaces that reach the side oxide film.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.

Abstract: A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate leakage currents in the device, thereby mitigating total dose radiation effects. A method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, has the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.

Abstract: A semiconductor device a bleeder resistance circuit having conductors, an insulating film disposed on the conductors, and thin film resistors each overlying a respective one of the conductors with the insulating film disposed therebetween. Each of the thin film resistors contains p-type impurities and has a thickness in the range of 10 to 2000 angstroms. Each of the conductors is electrically connected to and has the same electric potential as a respective one of the thin film resistors.

Abstract: An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

Abstract: An aspect the present invention is to provide a semiconductor device including at least one MISFET structure having an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region, an element region formed on the surface region of the semiconductor substrate to surround the element isolation region, a gate insulating film formed to cover at least the surface of the element region, a contact region formed on the element isolation region, and at least four gate electrodes connected to the contact region and formed on the surface of the element region via the gate insulating film to extend to at least outside the element region.

Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.

Abstract: P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.

Abstract: A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures.

Abstract: A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the buried bit lines and between the gates, a plurality of word lines each disposed over a row of gates perpendicular to the buried bit lines, and a coding layer between the word lines and the gates.

Abstract: In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and on the gate electrode using a relatively high voltage. A gate insulating film is etched using the barrier anodic oxide as a mask. The porous anodic oxide is selectively etched after etching barrier anodic oxide, to obtain a region of an active layer on which the gate insulating film is formed and the other region of the active layer on which the gate insulating film is not formed. An element including at least one of oxygen, nitrogen and carbon is introduced into the region of the active layer at high concentration in comparison with a concentration of the other region of the active layer. Further, N- or P-type impurity is introduced into the active layer.

Abstract: A method of fabricating a semiconductor device is disclosed. A wafer substrate is provided. A first silicon oxide layer is formed over the wafer substrate. A nitride layer is formed over the first silicon oxide layer using a low temperature deposition process. A second silicon oxide layer is formed over the nitride layer. The low temperature process can form a nitride layer for an oxide-nitride-oxide (ONO) dielectric structure at about a temperature of 700° C. By such a process, an ONO dielectric structure can be formed using a low temperature deposition process, which can reduce the thickness of the ONO dielectric structure.

Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

Abstract: Proposed are a device, a magnetic-field sensor and a current sensor, the device having the feature that provision is made for a first magnetic-field sensing means, for a second magnetic-field sensing means, and for a third magnetic-field sensing means, a first output variable of the first magnetic-field sensing means being provided as a first input variable, a second output variable of the first magnetic-field sensing means being provided as a second input variable, the first input variable being provided as input variable for the second magnetic-field sensing means, and the second input variable being provided as input variable for the third magnetic-field sensing means.

Abstract: A crystalline substrate based device includes a crystalline substrate having formed thereon a microstructure, and a transparent packaging layer which is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the packaging layer. The microstructure receives light via the transparent packaging layer.

Abstract: A semiconductor optical component is disclosed which includes a semiconductor material confinement layer containing acceptor dopants such that the doping is p-type doping. The confinement layer is deposited on another semiconductor layer and defines a plane parallel to the other semiconductor layer. Furthermore, the p-type doping concentration of the confinement layer has at least one gradient significantly different from zero in one direction in the plane. A method of fabricating the component is also disclosed.

Abstract: A light-receiving element, comprises an absorption layer formed on a semiconductor substrate, a window layer formed on the absorption layer, a first electrode formed on the window layer, a second electrode formed on the window layer and electrically connected to the first electrode, and a diffusion region which is formed in the absorption layer and the window layer and is formed between the first electrode and the substrate and between the second electrode and the substrate.

Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle &thgr; is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

Abstract: A method of manufacturing a high-gain, high-frequency device, such as a phased-array antenna, which uses such a switch having movable parts as a micromachine switch. The high-frequency device comprises a dielectric substrate on which are formed a plurality of waveguides for carrying high-frequency signals, a phase control layer, and dielectric spacers arranged between the phase control layer and another layer to provide space in which a switch formed in the phase control layer is enclosed.

Abstract: Trenches for defining chip areas are formed on the surface of a semiconductor substrate so that outlines of side walls of each of the trenches have recesses or protrusions. Then, a sputtering film is so formed as to be continuous in an area bridging the surface of each of the chip areas and the inside surface of each of the trenches, and the semiconductor substrate is diced along lines outside the trenches.

Abstract: A memory cell for a three-dimensional intergrated circuit memory is disclosed. The cell includes a very highly doped semiconductor regions with a doping level of 1020 atoms cm−3 or higher. An antifuse region is disposed between the heavily doped region and a more lightly doped region.

Abstract: A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.

Abstract: A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

Abstract: A semiconductor device has a plurality of capacitors. The semiconductor device includes a first capacitor arranged on a substrate and including first upper and lower electrode layers between which a first capacitor insulation film is interposed, and a second capacitor arranged on the substrate and including second upper and lower electrode layers between which a second capacitor insulation film is interposed, the second upper and lower electrode layers having a same structure as that of the first upper and lower electrode layers, and the second capacitor having a per-unit-area capacity different from that of the first capacitor.

Abstract: According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further comprises an electrode of the upper MIM capacitor situated over the shared electrode. The electrode of the upper MIM capacitor is coupled to the electrode of the lower MIM capacitor through vias and a second interconnect metal layer. In one embodiment, the electrode of the upper MIM capacitor can be divided into two or more segments to allow additional paths for connectivity to reduce the resistance of an electrode of the composite MIM capacitor. In other embodiments, a method for fabricating various embodiments of the composite MIM capacitor is disclosed.

Abstract: A thin-film resistor includes a resistive element with a predetermined length and width deposited on a substrate. An insulator layer is patterned so as to cover all of the resistive element except the ends in the width direction and is tapered. Electrodes are connected to respective ends of the resistive element via a plating base layer. The electrodes have a reduced resistance. The thin-film resistor can exhibit high accuracy and a small range of variation of the resistance.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: The invention relates to a trench bipolar transistor structure, having a base 7, emitter 9 and collector 4, the latter being divided into a higher doped region 3 and a lower doped drift region 5. An insulated gate 11 is provided to deplete the drift region 5 when the transistor is switched off. The gate 11 and/or doping levels in the drift region 5 are arranged to provide a substantially uniform electric field in the drift region in this state, to minimise breakdown. In particular, the gate 11 may be seminsulating and a voltage applied along the gate between connections 21,23.

Abstract: The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second leakage current, which is coupled to a current-mirror circuit. The output of the current-mirror circuit is configured to provide a cancellation effect on the first leakage current. The current-mirror circuit and vertical PNP may be configured such that the first leakage current is cancelled in a judicious amount, whereby the effects of leakage current and flare-out in the vertical PNP transistor are minimized or cancelled. The cancellation technique is applicable to temperature sensor circuits, thermal voltage generators, and bandgap circuits.

Abstract: A transistor and method for making the same are disclosed. The transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement. The emitter layer is etched to form a mesa on an etched surface, the mesa having a top surface that includes a portion of the emitter layer and an emitter contact and sides joining the top surface with the etched surface. First and second protective layers are then deposited over the emitter contact and etched surface and the portions of these layers that overlie the etched surface are removed. The first protective layer is then preferentially etched thereby undercutting a portion of the first protective layer on the sides of the mesa and creating an overhanging portion of the second protective layer that is utilized to align the deposition of the base contacts.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: An ESD protection structure for use with bipolar or BiCMOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event. This immunity is achieved by employing a heat sink region adjacent to a polysilicon emitter within a distance of less than 2 microns. Such a heat sink region provides temporal heat capacity to locally dissipate the heat generated during an ESD event. Bipolar transistor-based ESD protection structures according to the present invention include a semiconductor substrate and a bipolar transistor in and on the semiconductor. The bipolar transistor includes a base region, a collection region and a polysilicon emitter. The bipolar transistor-based ESD protection structures also include a heat sink region disposed above the semiconductor substrate adjacent to the polysilicon emitter.

Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads. A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.

Abstract: A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.

Abstract: A semiconductor device having a semiconductor chip, a wiring board joined to one surface of the semiconductor chip and electrically connected to the semiconductor chip, and a warp preventing board joined to the other surface of the semiconductor chip and composed of the same material as that of the wiring board. An external connection member for surface mounting may be arranged on a surface, facing away from the semiconductor chip, of the wiring board.

Abstract: Embodiments of the invention include an integrated circuit package and methods for its construction. An integrated circuit package of the invention includes a die attach pad and a plurality of lead pads. An integrated circuit die is mounted with the front side of the die attach pad and electrically connected to the plurality of lead pads. Additionally, the backside of the die attach pad includes a pattern of mesas formed thereon. Each of the mesas is configured such that they have a top surface area that is substantially the same size as the surface area of the lead pads. A contact layer of reflowable material is formed on the top surface of the mesas and the lead pads, forming an integrated circuit package with an improved contact layer.

Abstract: A mounting for a package containing a semiconductor chip is disclosed, along with methods of making such a mounting. The mounting includes a substrate having a mounting surface with conductive traces thereon, and an aperture extending through the substrate. The package includes a base, such as a leadframe or a laminate sheet, and input/output terminals. A chip is on a first side of the base and is electrically connected (directly or indirectly) to the input/output terminals. A cap, which may be a molded encapsulant, is provided on the first side of the base over the chip. The package is mounted on the substrate so that the cap is in the aperture, and a peripheral portion of the first side of the base is over the mounting surface so as to support the package in the aperture and allow the input/output terminals of the package to be juxtaposed with to the circuit patterns of the mounting surface. Because the cap is within the aperture, a height of the package above the mounting surface is minimized.

Abstract: A semiconductor device assembly package includes a semiconductor device having components thereon which are generic to a variety of applications by manipulation of the pinout configuration. The lead frame includes redundant leads for connection to the semiconductor device, as desired. The semiconductor device may include redundant wire bond pads, each redundant pair including one pad on a lateral edge and one pad on a non-lateral edge of the die. In applications requiring less than all of the available leads, the pinout configuration of the leadframe is adjusted to use the extra space from unused NC leads and missing pins for providing wider, shorter leads with reduced inductance, and wider paddle arms for reduced bending and breakage.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate, thereby reducing resistance and inductance in the ground signal path and increasing the efficiency of the power package.

Abstract: A conductive mounting board provided in a package has a recessed portion and a projecting portion, and an insulating mounting board is disposed on the recessed portion. The insulating mounting board is disposed on the recessed portion. The insulating mounting board has an insulating board on the surface of which a wiring portion is disposed. A semiconductor laser, constituted by stacked semiconductor layers each being made from a compound semiconductor composed of a group III based nitride, is disposed on the insulating mounting board and the conductive mounting board. An n-side electrode of the semiconductor laser is in contact with the insulating mounting board and a p-side electrode thereof is in contact with the conductive mounting board. Heat generated in the semiconductor laser is radiated via the conductive mounting board, and short-circuit between the n-side electrode and the p-side electrode is prevented by the insulating mounting board.

Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is deposited in a packaging mold, and the packaging mold comprises a plurality of injection pins for pushing the packaging substrate out of the packaging mold. A first copper-mesh layer and a second copper-mesh layer of the packaging substrate are electrically connected to each other via position pins. A bottom side of the packaging substrate comprises a plurality of recesses in positions corresponding to positions of the injection pins. The recesses pass the second copper-mesh layer to electrically connect the injection pins to the second copper-mesh layer, and static electric charges are conducted to the injection pins via the second copper-mesh layer and away from the packaging substrate. It prevents dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.

Abstract: This invention provides a circuit mounting method and a circuit mounted board which can mount semiconductor elements at a high density. A recessed portion is formed in a board, a memory IC packaged in a chip size package method (CSP) is mounted in the recessed portion, and a memory IC packaged in a thin small outline package method (TSOP) is mounted on the board to cover the recessed portion.

Abstract: In the past, a power supply distance between a power source and an LSI package could not be shortened and power supply variations could easily produce an adverse effect. To reduce the power supply distance between the LSI and power supply module the power supply module is mounted on an upper surface of the LSI package. As a result, the power source noise can be reduced, the efficiency and response rate of the power source unit are high, and the generated electromagnetic field can be reduced. Moreover, since each LSI package has a power supply module required therefore, the number of required power source types (voltage types) on the substrate with the package mounted thereon can be decreased. As a result, the mounting efficiency can be increased and the substrate can be manufactured at a low cost.

Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

Abstract: A stacked multi-chip package includes a substrate, a first chip and a second chip. The first chip is fixed to the substrate, and is provided with a collar portion which opposes an upper face of the substrate in a state such that a gap is formed between the upper face of the substrate and the collar portion. The second chip is disposed in a region below the collar portion. The second chip is fixed to the substrate and does not make contact with the first chip.

Abstract: A stacked semiconductor device structure comprising: a plurality of semiconductor modules each of which includes a substrate and at least one semiconductor device mounted on the substrate; a stacking device for stacking the semiconductor modules on one another; and a surface mount device for surface mounting on a further substrate for a system appliance the semiconductor modules stacked on one another by the stacking device.