Abstract: Electromigration testing is accelerated in the batch fabrication of semiconductor integrated circuits by forming test structures during the metal deposition phase of the batch fabrication process. Test metal lines can be formed on steps etched in a silicon oxide insulating layer with the vertical walls of the steps being greater than twice the thickness of the deposited metal whereby metal is not deposited on the side walls. Alternatively, test lines in the deposit metal layer can be formed by laser ablation or by ultrasound erosion. In another embodiment, electromigration tests are performed directly on the deposit metal layer through use of spaced elongated electrical contacts placed on the deposited metal layer surface. The elongated contacts can be wires of known diameter and length, or the elongated contacts can comprise a plurality of point contacts.

Abstract: A novel method and system for fabricating integrated circuit devices is disclosed herein. In one embodiment, the method comprises determining at least one electrical performance characteristic of a plurality of semiconductor devices formed above at least one semiconducting substrate, providing the determined electrical performance characteristics to a controller that determines, based upon the determined electrical characteristics, across-substrate variations in an exposure dose of a stepper exposure process to be performed on at least one subsequently processed substrate, and performing the stepper exposure process comprised of the across-substrate variations in exposure dose on the subsequently processed substrates.

Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.

Abstract: The invention provides a quick turn around time system (QTAT) for locating an optimal arrangement of work orders within a wafer fabrication facility providing: a real time dispatching system having a software rule database; and at least one piece of fabrication equipment having an internal buffer in communication with the software rule database, wherein the real time dispatching system and the at least one piece of fabrication equipment cooperate to optimally prioritize a work order disposed within the internal buffer of the at least one piece of fabrication equipment. A load port reservation system for in-line processing and a plurality of batch editing functions for controlling batch formation is provided. Additionally provided are two alternative methods of using the QTAT to optimally prioritize work orders within the at least one piece of fabrication equipment's internal buffer.

Abstract: The present invention describes a structure for and a method of forming a first set and a second set of features in a substrate; covering the first and second set of features with a material; forming a third set of features in the material and removing the material to expose the first set of features, leaving the second set of features embedded below the material; measuring post-etch overlay between the first set and the third set of features; and measuring post-develop overlay between the second set and the third set of features.

Abstract: Photoresist reflow for an enhanced process window for non-dense contacts is disclosed. A corrective bias is determined for application to each of a number of contacts at different pitches, to achieve a substantially identical critical dimension for each contact. The corrective bias is determined based on a first and a second critical dimension for each contact, where the first critical dimension is before photoresist reflow, and potentially inclusive of optical proximity effects, and the second critical dimension is after photoresist reflow. A photomask is then constructed for a semiconductor design that incorporates the corrective bias that has been determined for the contacts of the design. Lithographical processing of the semiconductor design on a semiconductor wafer using thus photomask, and subsequent photoresist reflow, thus achieves a substantially identical critical dimension for each of the contacts of the semiconductor design.

Abstract: A method of manufacturing a semiconductor device, comprises: forming a semiconductor element in a semiconductor active region, and calculating the generation rate of electron hole pairs generated due to impact ionization caused in the semiconductor element; calculating a volume integral of the generation rate at least in an area where the impact ionization is caused; evaluating time-dependent degradations of electrical characteristics of the semiconductor element on the basis of the volume integral; and manufacturing a semiconductor device on the basis of the evaluation.

Abstract: The present invention provides a nano-structure which can be applied to various high-function devices. The nano-structure includes an anodically oxidized layer having a plurality of kinds of pores.

Abstract: An OLED device having pillars with cross section that is wider on the top. The pillars structure a conductive layer during deposition into distinct portions located between the pillars and on the top of the pillars. In one embodiment, the grooves between the pillars extend outside the electrode region to prevent shorting of adjacent electrodes.

Abstract: The nitride-based semiconductor laser device 10 has a stacked structure comprising a first contacting layer 14, a first cladding layer 16, an active layer 20, a second cladding layer 24, a second contacting layer 26 and a second electrode 30 which are consecutively stacked, the second cladding layer 24 comprises a lower layer 24A and an upper layer 24B, the first cladding layer 14, the active layer 20 and the lower layer 24A of the second cladding layer have a mesa structure, the upper layer 24B of the second cladding layer and the second contacting layer 26 have a ridge structure, an insulating layer 40 covering at least part of each of both side surfaces of the upper layer 24B of the second cladding layer is formed on the portions of the lower layer 24A of the second cladding layer which portions correspond to the top surface of the mesa structure, and further, a metal layer 42 having substantially the same width as the mesa structure is formed on the top surface of the insulating layer 40 and the top surfa

Abstract: The present invention relates to a manufacturing method of a thin-film structural body which is formed by using a semiconductor processing technique, and an object thereof is to provide a manufacturing method of a thin-film structural body, capable of reducing a stress difference exerted between a sacrifice film and a substrate upon thermal shrinkage. In order to achieve this object, a sacrifice film (51), which is formed on a substrate (1), is formed by using a PSG film in which the concentration of phosphorus is set to a value which is greater than 3 mol %, and also smaller than 4 mol %. After a thin-film layer (53) has been formed thereon and after the thin-film layer (53) has been patterned, the sacrifice film (51) is removed by an etching process.

Abstract: A method for measuring temperature T over a wide range by exploiting a tunnel junction, in which the tunnel junction includes two metallic conductors and a thin insulating layer between the conductors. The resistance R of the insulating layer is measured over the linear section of the voltage-current curve and the temperature T is determined from the equation: 1 R = 1 R 0 ⁢ ( 1 + ( T T 0 ) 2 ) , in which R0 is a previously calibrated constant and T0 is a material constant.

Abstract: One or more deep-array implants under the photosensitive region of a semiconductor substrate are conducted to improve optical cross-talk between pixel cells. According to an embodiment of the present invention, one or more deep-array implants of a first conductivity type are used to dope predefined regions of a well of a second conductivity type. This way, first conductivity type dopants from the one or more deep-array implants counterdope second conductivity type dopants from the predefined regions of the well. The dosage and energy of each deep-array implant may be optimized so that the collection of signal carriers by the photosensitive region and the photoresponse for different wavelengths are maximized.

Abstract: A process for producing a solid-state imaging device which includes the steps of forming a light-receiving portion of a pixel in a surface region on the substrate, forming above the light receiving portion an inter-layer dielectric having a depression in its surface, forming on the inter-layer dielectric a light transmitting film having in its surface a concave conforming to the depression, forming at the position that covers the concave on the light transmitting film a mask layer with a convexly curved surface, and etching the mask layer and the light transmitting film all together, thereby making the light transmitting film into a shape of convex lens with an upwardly curved surface.

Abstract: In a solid state image sensor, tranfer electrodes are formed by selectively etch-removing a single layer of conducting electrode material at a plurality of first regions which divide the single layer of conducting electrode material in a row direction for each one pixel. A patterned mask is formed to cover the first regions and the single layer of conducting electrode material but to expose the single layer of conducting electrode material at a second region above each of the photoelectric conversion sections, and the single layer of conducting electrode material is selectively etch-removed using the patterned mask as a mask. Thereafter, a first conductivity type impurity and a second conductivity type impurity are ion-implanted using the patterned mask and the single layer of conducting electrode material as a mask, to form the photoelectric conversion section at the second region.

Abstract: The present invention relates to an organic light emitting device (OLED) for producing electroluminescence having, in order, for example, an anode, a hole transporting layer (HTL), a blocking layer, an electron transporting layer (ETL), and a cathode. In the devices of the present invention, the hole transporting layer comprises a polymeric material, which material may be emissive or may be doped with an emissive dopant. The blocking layer and the electron transporting layer are small-molecule materials. The presence of a blocking layer confines the emission of light to the polymer layer, which may be a HTL or a separate emitting layer (EL). The devices of the present invention are suitable for use in single color, multi-color and full-color, passive or active matrix OLED displays.

Abstract: A high temperature thermal annealing process creates a low resistance contact between a metal material and an organic material of an organic semiconductor device, which improves the efficiency of carrier injection. The process forms ohmic contacts and Schottky contacts. Additionally, the process may cause metal ions or atoms to migrate or diffuse into the organic material, cause the organic material to crystallize, or both. The resulting organic semiconductor device has enhanced operating characteristics such as faster speeds of operation. Instead of using heat, the process may use other forms of energy, such as voltage, current, electromagnetic radiation energy for localized heating, infrared energy and ultraviolet energy. An example enhanced organic diode comprising aluminum, carbon C60, and copper is described, as well as example insulated gate field effect transistors.

Abstract: A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.

Abstract: A stacked dual-chip semiconductor packaging technology is proposed for the packaging of two semiconductor chips in one single package unit. The proposed dual-chip semiconductor package is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. By the proposed packaging technology, a first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip. Compared to the prior art, the proposed technology allows the packaging process to be implemented in a less complex and more cost-effective manner.

Abstract: A package structure and method for making devices of system-in-a-package (SiP). Substrates with integrated and assembled elements can be aligned and pre-bonded together, and fluidic encapsulating materials is applied to seal the rest opening of pre-bonded interface of substrates. Three dimensional and protruding microstructures, elements, and MFMS devices can be accommodated and protected inside a spatial space formed by the bonded substrates. By applying the technologies of flip-chip, chip-scale-packaging, and wafer-level-packaging in conjunction with present invention, then plural elements and devices can be packaged together and become a system device in wafer-level-system-in-a-package (WLSiP) format.

Abstract: In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

Abstract: A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a heat-radiating plate 22, and attaching the heat-radiating plate 20 to the semiconductor wafer. The assembled wafer and heat-radiating plate are diced into individual semiconductor integrated circuits having individual heat radiating plates attached thereto.

Abstract: A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.

Abstract: A low temperature cure adhesive material for affixing a solder mask to a die is described. The adhesive material is at least partially cured at temperatures below about 100° C. The low temperature curing lowers the thermal stresses on the adhesive, diminishes the possibility of voids being formed in the adhesive material, and increases the bond yield.

Abstract: This invention relates to a semiconductor package in which a silicon die is adhered to a substrate with an adhesive comprising a resin having the structure: in which Q is an oligomeric or polymeric group containing at least one carbon to carbon double bond, A is a hydrocarbyl group or an aromatic group, and L is a linking group resulting from the reaction of a functional group, excluding epoxy, on the precursor for the segment containing silane and a functional group, excluding epoxy, on the precursor for the segment containing the at least one carbon to carbon double bond.

Abstract: A microelectronic die comprises a first area, a second area and an under-layer of conductive material formed in the second area to interconnect components. A method of making a microelectronic die comprises forming a layer of insulative material on a substrate; forming at least one trench in the layer of insulative material; and forming at least one line of conductive material in each of the at least one trenches to transmit signals.

Abstract: A light-emitting semiconductor component having: a semiconductor element containing an active layer, electrical contacts for impressing a current into the active layer (heat being generated at the active layer and at the electrical contacts during operation), and a carrier with a large thermal capacity for absorbing the heat generated during operation. The rear side of the semiconductor element is electrically and thermally connected to the carrier by a conductive adhesive. Recesses, which accommodate a part of the conductive adhesive when the semiconductor element is connected to the carrier, are provided in the rear side of the semiconductor element.

Abstract: Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an upper surface of the lower structure so as to contact the lower support structures. An upper structure is provided over the nanotube ribbon. The upper structure includes upper support structures and an upper electrically conductive element. In some arrangements, the upper and lower electrically conductive elements are in vertical alignment, but in some arrangements they are not.

Abstract: In a Bi-CMOS ESD protection device, dual voltage capabilities are achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.

Abstract: The illumination energy of an excimer laser is measured and adjusted to always effect illumination at constant energy. A laser beam output from an optics is reflected by a mirror, and applied to a sample. A beam profiler is disposed behind the mirror to measure the energy of an illumination laser beam. An energy attenuating device disposed between another mirror and the optics is operated based on the measurement value so that the energy of the laser beam applied to the sample is kept constant.

Abstract: Methods for forming thin films of semiconductor devices, and more specifically, methods for forming thin films of semiconductor devices, wherein the semiconductor substrate is subjected to a thin film formation process in a thin film formation apparatus containing a chamber, a susceptor vertically movable in the chamber and a heater disposed within the susceptor, the method comprising a preheating process for stabilizing the internal temperature of the chamber by vertically moving the susceptor a predetermined number of times prior to the thin film formation process.

Abstract: An active matrix organic light emitting display (AM-OLED) and a method of forming the same. The AM-OLED has a plurality of pixel areas arranged in a matrix form. Each pixel area has at least two amorphous silicon TFTs, a display area and a light-shielding layer. The amorphous silicon TFT has an amorphous silicon layer serving as a channel region. The display area is formed by a transparent-conductive layer. The light-shielding layer covers at least the amorphous silicon layer of the amorphous silicon TFT and exposes the display area.

Abstract: A method for the manufacture of an insulated gate field effect semiconductor device comprised of a semiconductor substrate, a gate insulating layer member having at least an insulating layer, and a gate electrode. The insulating layer is formed of silicon or aluminum nitride on the semiconductor substrate or the gate electrode by a photo CVD process.

Abstract: A method of fabricating a thin film transistor includes forming an amorphous silicon layer as an active layer on a substrate, forming a gate insulating layer and a gate electrode on the amorphous silicon layer, doping impurities of a first conductive type in the amorphous silicon layer, forming a metal layer on the exposed portions of the amorphous silicon layer, and crystallizing the amorphous silicon layer by applying thermal treatment and electric field to the resultant substrate.

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.

Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractor metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.

Abstract: A new method to form split gate flash memory cells in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. Pairs of floating gates are formed overlying the substrate. Common source plugs are formed overlying the substrate and filling spaces between the floating gate pairs. An oxide layer is formed overlying the substrate, the floating gates, and the common source plugs. A conductor layer is deposited overlying the oxide layer. First dielectric spacers are formed on vertical surfaces of the conductor layer. The conductor layer is etched through where not covered by the first dielectric spacers to thereby form word line gates adjacent to the floating gates. Second dielectric spacers are formed on vertical surfaces of the word line gates and the first dielectric spacers to complete the split gate flash memory cells.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain nitrogen as a major component, a second insulating film is formed on the first insulating film, and an interlayer insulating film is formed on the second insulating film whose major component is different from a manor component of the second insulating film.

Abstract: An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one d

Abstract: An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the connection layer 19 and the bit line 300 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: A method of forming (and apparatus for forming) refractory metal oxide layers, such as tantalum pentoxide layers, on substrates by using vapor deposition processes with refractory metal precursor compounds and ethers.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.