Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The present invention includes the steps of: preparing a wafer having a first area and a second area, wherein the first area has lower topology than the second area; forming a target layer on the wafer; and patterning the target layer through a photolithography process so to form a number of first patterns in a line shape at the second area and to form a number of second patterns in a closed loop shape at the first area.

Abstract: The invention includes: forming a capacitor electrode over one region of a substrate; forming a capacitor dielectric layer proximate the electrode; forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer.

Abstract: A method for preventing bit line to bit line leakage in a memory cell is described. In this method, P-implantation is applied to suppress the leakage current induced by the damage, wherein the damage is caused by the etching step for the formation of spacers. The P-implantation step is performed after the etching step, and such a sequence centralizes the implanted ions to prevent them from decreasing the threshold voltage. On the other hand, the P-implantation step is performed after the bit line annealing step to prevent the implanted ions from being thermally diffused.

Abstract: A first polysilicon film, an ONO film, and a second polysilicon film are deposited on a substrate. After ions of an impurity have been implanted in the second polysilicon film, a silicon oxide is deposited on the substrate, followed by a heat treatment for activating the impurity. Patterning is thereafter performed on the silicon oxide film, the second polysilicon film, the ONO film and the first polysilicon film to from stack cell electrodes and an on-gate protective film. The on-gate protective film formed of a silicon oxide film is densified to have improved resistance to etching. Therefore the desired shape of the on-gate protective film is maintained. The film thickness of sidewalls on side surfaces of the stack cell electrodes is set with stability, so that the reduction in insulation withstand voltage between a contact and a control gate electrode is limited.

Abstract: A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

Abstract: A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.

Abstract: A semiconductor device of which the process is simplified so that the manufacturing cost can be reduced and, at the same time, which has a semiconductor element that can control a current of high voltage is provided. The semiconductor device includes first and second semiconductor elements and the first semiconductor element includes a lower electrode formed above a substrate, an intermediate insulating film formed on the lower electrode and an upper electrode formed on the insulating film. The second semiconductor element includes a gate insulating film, which is formed on the substrate and which includes the same layer as that of the intermediate insulating film, and a gate electrode formed on the gate insulating film.

Abstract: A process for a semiconductor device includes the following steps applied to a silicon substrate wherein a floating gate electrode having sidewalls is formed above the semiconductor substrate with a tunnel oxide film intervened and wherein active regions are arranged in places adjoining both sides of floating gate electrode, as seen from above, and arsenic is injected into said active regions as an impurity: the lamp annealing step of carrying out a heat treatment in the atmosphere of a first gas mixture which includes nitrogen and oxygen; and the oxygen film formation step of carrying out a heat treatment in the atmosphere of a second gas mixture which includes oxygen so as to form an oxide film on sidewalls of floating gate electrode after the lamp annealing step.

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration H-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: Disclosed are a transistor in the semiconductor device and method of fabricating the same. A gate oxide film is formed using a nitrification oxide film in a low voltage device region and a gate oxide film is formed to have a stack structure of a nitrification oxide film/oxide film/nitrification oxide film in a high voltage device region. An electrical thickness by an increased dielectric constant could be reduced even when a physical thickness of the gate oxide film is increased. The leakage current and diffusion and infiltration of a dopant into the gate oxide film or the channel region could be prevented. Furthermore, an electrical characteristic of the device could be improved by reducing the leakage current.

Abstract: One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the flash memory. The flash memory array comprises a plurality of flash memory cells which each have a source region and a drain region in the semiconductor substrate. A first portion of a first dielectric layer is formed over the flash memory array, and contact holes in the first dielectric layer are formed down to source regions of flash memory cells in the core region. A trench is then formed in the first dielectric layer and extends between the two contact holes. The contact holes and trench are then filled with a conductive material, thereby electrically coupling together the source regions of the two flash memory cells.

Abstract: A semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.

Abstract: The present invention discloses a method for fabricating a BiCMOS transistor, which improves the high frequency characteristics of a bipolar transistor by reducing base resistance and a parasitic capacitance between the base and collector.

Abstract: A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask layer. The photomask has a pattern thereon for forming the emitter. The pattern is defined by a first area R associated with the shape of the emitter to be formed, and a plurality of second areas T1 to T4. Each of the second areas T1 to T4 includes first and second sides S1 and S2 meeting each other to form an acute angle therebetween, and a third side S3 in contact with the first area R. In each of the second areas T1 to T4, one side S3 of the two sides meeting each other to form a right angle therebetween is in contact with one side of the area R, whereas the other side S1 is connected to another side of the first area R to form a line segment.

Abstract: A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow through the transistor, while the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.

Abstract: A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film, are formed on the sides of the gate electrodes respectively. After formation of a transistor having an LDD structure in the logic area, the silicon oxide film formed on the sides of the gate electrodes is removed by wet etching. Next, a silicon nitride film is formed on the whole surface of the semiconductor substrate, and an interlayer dielectric is formed on the silicon nitride film.

Abstract: In a method of manufacturing a capacitor, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form an upper electrode. Finally, the first conductive layer is patterned to form a lower electrode and a conductive pattern after the formation of the upper electrode.

Abstract: A capacitor is fabricated over a first layer having a first conductive plug formed on a substrate in a semiconductor memory. On the first layer, a silicon nitride film, a first capacitor oxide film, and a second oxide film are sequentially formed. The first and the second oxide films have different wet etch rates. Dry and wet etchings are sequentially performed to the first and second oxide films to form a second contact hole. The second contact hole is then etched. Thereafter, a silicon film and a filler film are sequentially formed on the resultant surface of the structure. A cylindrical storage node electrode is then formed by etching a predetermined portion of the filler film and the silicon film. After removing the remaining filler film and the oxide films, a Ta2O5 dielectric film covering the storage node electrode and a TiN film for an upper electrode are then sequentially formed.

Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.

Abstract: A method for intra-cell alignment of a substrate and mask comprises providing a substrate comprising an exposed photosensitive material, providing a phase-shift mask, and aligning the phase-shift mask to an intra-cell structure on the substrate.

Abstract: A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.

Abstract: A method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate such as silicon substrate is annealed in an ambient containing nitric oxide or nitrogen and oxygen to form a silicon oxynitride film on the shallow trench to serve as a barrier to prevent dopant source/drain outdiffusion. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: A method of forming a silicon oxide, shallow trench isolation (STI) region, featuring a silicon rich, silicon oxide layer used to protect the STI region from a subsequent wet etch procedure, has been developed. The method features depositing a silicon oxide layer via PECVD procedures, without RF bias, using a high silane to oxygen ratio, resulting in a silicon rich, silicon oxide layer, located surrounding the STI region. The low etch rate of the silicon rich, silicon oxide layer, protect the silicon oxide STI region from buffered hydrofluoric wet etch procedures, used for removal of a dioxide pad layer.

Abstract: Semiconductor devices and methods for manufacturing the same in which deterioration of the electrical characteristic is suppressed are described. One method for manufacturing a semiconductor device includes the steps of: forming a first polysilicon layer 32 on a gate dielectric layer 20; forming a silicon nitride layer 92 on the first polysilicon layer 32; forming a second polysilicon layer 94 on the silicon nitride layer 92; forming sidewall spacers; forming an insulation layer 60 that covers the second polysilicon layer 94; planarizing the insulation layer 60 until an upper surface of the second polysilicon layer 94 is exposed; removing the second polysilicon layer 94; removing the silicon nitride layer 92 to form a recessed section 80; and filling a metal layer 34 in the recessed section 80 to form a gate electrode 30 that includes at least the first polysilicon layer 32 and the metal layer 34.

Abstract: A production method of silicon which comprises the steps of bringing a silane into contact with a surface of a substrate so as to cause silicon to be deposited while the surface of the substrate is heated to and kept at a temperature lower than the melting point of the silicon, and raising the temperature of the surface of the substrate so as to cause a portion or all of the deposited silicon to melt and drop from the surface of the substrate and be recovered.

Abstract: A semiconductor substrate and an impurity solid that comprises of impurity to be introduced to a diode formation region are held in a vacuum chamber. Inert or reactive gas is introduced into the vacuum chamber to generate plasma composed of the inert or reactive gas. A first voltage allowing the impurity solid to serve as a cathode for the plasma is applied to the said impurity solid and the said impurity solid is sputtered by ions in the plasma, thereby mixing the impurity within the said impurity solid into the plasma. A second voltage allowing a semiconductor substrate to serve as a cathode for the plasma is applied to the said semiconductor substrate, thereby directly introducing the impurity within the plasma to the surface portion of the diode formation region of the said semiconductor substrate, generating a impurity layer.

Abstract: A method of forming a gate structure includes forming sequentially a pad layer and a first photoresist layer over a substrate. A cross-linked surface layer is formed on the surface of the first photoresist layer, followed by rounding the profile of the first photoresist layer, and removing the exposed pad layer to expose the substrate. A second photoresist layer is formed over the first photoresist layer, wherein a portion of the first photoresist layer and the exposed substrate are exposed by the second photoresist layer. Thereafter, a conductive layer is formed, wherein the conductive layer formed on the second photoresist layer is separated from the conductive layer formed on the first photoresist layer and the exposed substrate. The first and the second photoresist layers are removed while the conductive layer on the second photoresist layer is concurrently being striped. The remaining conductive layer serves as a gate structure.

Abstract: Single-electron transistors include first and second electrodes and an insulating layer between them on a substrate. The insulating layer has a thickness that defines a spacing between the first and second electrodes. At least one nanoparticle is provided on the insulating layer. Accordingly, a desired spacing between the first and second electrodes may be obtained without the need for high resolution photolithography. An electrically-gated single-electron transistor may be formed, wherein a gate electrode is provided on the at least nanoparticle opposite the insulating layer end. Alternatively, a chemically-gated single-electron transistor may be formed by providing an analyte-specific binding agent on a surface of the at least one nanoparticle. Arrays of single-electron transistors also may be formed on the substrate.

Abstract: The present invention provides a method and apparatus for an atomic layer deposition process. The apparatus includes a chamber adapted to receive a first precursor gas, at least one surface interior to the chamber, and an acoustic wave driver coupled to the at least one surface and adapted to drive acoustic waves along the interior surface.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: A high deposition rate sputter method is utilized to produce bulk, single-crystal, low-defect density Group III nitride materials suitable for microelectronic and optoelectronic devices and as substrates for subsequent epitaxy, and to produce highly oriented polycrystalline windows. A template material having an epitaxial-initiating growth surface is provided. A Group III metal target is sputtered in a plasma-enhanced environment using a sputtering apparatus comprising a non-thermionic electron/plasma injector assembly, thereby to producing a Group III metal source vapor. The Group III metal source vapor is combined with a nitrogen-containing gas to produce a reactant vapor species comprising Group III metal and nitrogen. The reactant vapor species is deposited on the growth surface to produce a single-crystal MIIIN layer thereon. The template material is removed, thereby providing a free-standing, single-crystal MIIIN article having a diameter of approximately 0.

Abstract: A method and structure for solderably coupling an electronic module (e.g. a ceramic or plastic ball grid array module) to a circuit board. A lead-free solder ball is soldered to the module without using a joining solder to effectuate the soldering. The solder ball comprises a tin-antimony alloy that includes about 3% to about 15% antimony by weight. The solder ball is soldered to the circuit board with a lead-free joiner solder. The joiner solder comprises a tin-silver-copper alloy that includes by weight about 95.5-96.0% tin, about 3.5-4.0% silver, and about 0.5-1.0% copper. The resultant solder connection between the module and the circuit board has a fatigue life of at least about 90% of a fatigue life of a reference structure. The reference structure has a 90Pb/10Sn solder ball joined to both the module and the circuit card by a 63Sn/37Pb joiner solder.

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

Abstract: A method to selectively cap a cooper BEOL terminal pad with a Cu/Sn/Au alloy. The method includes providing one or more Cu BEOL terminal pads and coating the pads with a Sn coating followed by coating the Sn with a Au coating. The coated pads are then annealed to form the Cu/Sn/Au capping alloy.

Abstract: A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion for the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.

Abstract: A semiconductor device includes a lower conductive member, an upper conductive member and a conductive wire. The one end of the conductive wire is electrically connected to a semiconductor chip. The lower conductive member is formed on a lead frame. The conductive wire is sandwiched between the lower conductive member and the upper conductive member located thereon and is electrically connected to the lead frame. A connecting portion of the conductive wire connected to the lead frame is sandwiched between the lower and upper conductive members so that the neck portion of the conductive wire can be protected from above.

Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.

Abstract: Disclosed is a method for forming an insulating layer, including coating a substrate with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight, and heating the coated film while irradiating the coated film with an electron beam.

Abstract: An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper interconnects 90.

Abstract: An anti-reflective coating material layer is provided that has a relatively high etch rate such that it can be removed simultaneously with the cleaning of a defined opening in a relatively short period of time without affecting the critical dimensions of the opening. A method of forming such a layer includes providing a substrate assembly surface and using a gas mixture of at least a silicon containing precursor, a nitrogen containing precursor, and an oxygen containing precursor. The layer is formed at a temperature in the range of about 50° C. to about 600° C. Generally, the anti-reflective coating material layer deposited is SixOyNz:H, where x is in the range of about 0.39 to about 0.65, y is in the range of about 0.02 to about 0.56, z is in the range of about 0.05 to about 0.33, and where the atomic percentage of hydrogen in the inorganic anti-reflective coating material layer is in the range of about 10 atomic percent to about 40 atomic percent.

Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.

Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

Abstract: A method of manufacturing a semiconductor device having a self-aligned contact includes providing a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region, forming a first insulating layer on the semiconductor substrate, forming a plurality of conductive patterns on the first insulating layer, forming sequentially second, third and fourth insulating layers over the entire surface of the semiconductor substrate, etching the fourth insulating layer to form spacers on sidewalls of the conductive patterns, forming sequentially fifth and sixth insulating layers over the entire surface of the semiconductor substrate; and etching the sixth insulating layer using a portion of the fifth insulating layer over the self-aligned contact region as an etch stopper, and etching the fifth insulating lever to form a self-aligned contact.

Abstract: A new method is provided for forming salicided surfaces to a FET device. Gate electrodes are formed including Ti/TiN salicided contact surface regions thereto. A thin layer of silicon oxide and a thick layer of photoresist are deposited. The layer of photoresist is polished, stopping on a top layer of BN of the gate electrode. The exposed layer of BN is removed. A thick layer of Ti/TiN is next deposited and annealed, forming TiSix after which unreacted Ti/TiN is removed. A high temperature anneal is applied to reduce the sheet resistance of the layer of TiSix. As an alternate approach to the above cited sequence the layer of photoresist can be replaced with a layer of boro-phosphate-silicate-glass (BPSG), the layer of BN can be replaced with a layer of silicon nitride.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: This invention provides a capacitor and a method for manufacturing of the same, which are adaptable to preventing a lower electrode from being oxidized at a following thermal process. The capacitor includes: a lower electrode; an oxidation barrier layer formed on the lower electrode, wherein the oxidation barrier layer is formed of at least double nitridation layers; a dielectric layer formed on the oxidation barrier layer; and an upper electrode formed on the dielectric layer.