Patents Issued in August 31, 2004
  • Patent number: 6784101
    Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: August 31, 2004
    Inventors: Bin Yu, David Wu
  • Patent number: 6784102
    Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: August 31, 2004
    Assignee: LSI Logic Corporation
    Inventors: Max M. Yeung, Tauman T. Lau, Anwar Ali
  • Patent number: 6784103
    Abstract: Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: August 31, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Tushar P. Merchant, Ramachandran Muralidhar
  • Patent number: 6784104
    Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Qing-Tang Jiang, Jiong-Ping Lu
  • Patent number: 6784105
    Abstract: A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: August 31, 2004
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation, United Microelectronics Co.
    Inventors: Chih-Chao Yang, Yun Wang, Larry Clevenger, Andrew Simon, Stephen Greco, Kaushik Chanda, Terry Spooner, Andy Cowley, Sunfei Fang
  • Patent number: 6784106
    Abstract: A method for drying a semiconductor substrate includes the steps of clearing the substrate by supplying a liquid into a processing bath of a chamber, injecting first dry gases onto a surface of the supplied liquid, draining the liquid from the processing bath so that the substrate is slowly exposed to the surface of the liquid, and injecting a second dry gas into the chamber and forcibly exhausting gas in the chamber.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: August 31, 2004
    Assignee: DNS Korea Co., Ltd
    Inventors: Jeong-Yong Bae, Chang-Ro Yoon, Pyeng-Jae Park
  • Patent number: 6784107
    Abstract: A method of planarizing a copper interconnect structure using an atomic layer removal (ALR) technique to planarize a copper layer. In one embodiment, the ALR process performs a plurality of cycles, each cycle having a period of forming a film of copper fluoride on the copper layer and a period of removing the film of copper fluoride. The ALR process is repeated until a barrier layer beneath the copper layer is then etched to expose a dielectric material. The remaining copper forms a conductive line that is substantially coplanar with the dielectric material.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: August 31, 2004
    Inventors: Hui Chen, Chun Yan, Wai-Fan Yau
  • Patent number: 6784108
    Abstract: Etch profile control with pulsed gas flow and its applications to etching such as anisotropic etching of high aspect ratio features and etching of self-aligned contact structures in various processes. Pulsing can be applied according to this invention to the flow rate of a gas such as an etchant gas, a gas that leads to the deposition of a protective layer, a gas that modifies the deposition of a protective layer, and a gas that modifies etching.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Donohoe, David S. Becker
  • Patent number: 6784109
    Abstract: Semiconductor devices having a wiring construction consisting of a conductive layer (a copper layer) and an insulating layer (a porous insulator layer with low dielectric constant) are fabricated. A method for forming wiring of semiconductor devices includes a first step for forming a first insulating material layer on a sample; a second step for forming a second insulating material layer with a dielectric constant less than 2.5; a third step for patterning the second insulating material layer by a plasma etching method; a fourth step for depositing a metal film on the second insulating material layer by a sputtering method; a fifth step for forming a copper layer on the metal film; and a sixth step for removing an unnecessary portion of the copper layer by Chemical Mechanical Polishing, wherein all the processes from the third to the fourth step are performed under process conditions.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 31, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Naoyuki Kofuji, Masaru Izawa
  • Patent number: 6784110
    Abstract: In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: August 31, 2004
    Inventors: Jianping Wen, Meihua Shen, Hung-Kwei Hu
  • Patent number: 6784111
    Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high aspect ratios can be etched.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Donohoe, Rich Stocks
  • Patent number: 6784112
    Abstract: A surface treatment method for thinning a silicon based substrate obtains a milky-dull color on an overall surface uniformly of the silicon based substrate. To be more specific, a surface opposite to a circuit-formed surface is mechanically polished, then the surface is etched using inert gas such as argon gas for producing plasma. This etching forms micro dimples uniformly on the surface. Next, the surface is further etched using fluorine based gas for producing plasma. This etching obtains a milky-dull color uniformly on the surface. As a result, printed marks on the surface can be read with ease, and pick-up errors in die-bonding can be reduced.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
  • Patent number: 6784113
    Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel elastomer or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conductive-filled gel elastomer is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: David R. Hembree
  • Patent number: 6784114
    Abstract: The present invention relates generally to a method of improving the performance of solid state devices, and specifically provides methods for passivating a semiconductor surfaces with a monolayer of passivating material.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: August 31, 2004
    Assignee: Board of Regents The University of Texas System
    Inventors: Meng Tao, Wiley P. Kirk
  • Patent number: 6784115
    Abstract: Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin in some regions, such as the cell region, and thicker in other regions (165), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: August 31, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Cheng-Tsung Ni, Jacson Liu, Chih-Sheng Chang, Hudy-Jong Wu
  • Patent number: 6784116
    Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: August 31, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
  • Patent number: 6784117
    Abstract: In a method for manufacturing a semiconductor device having a USG film 5 formed on a semiconductor substrate 1 in which an N+-type active region 2 and a P+-type active region 3 are formed, an oxide film 4 is formed on the semiconductor substrate 1 and the USG film 5 is formed on the oxide film 4. Because the influence of the characteristic difference of an underlying layer on the formation of the USG film 5 can be avoided due to the existence of the oxide film, the USG film 5 can be formed in a uniform thickness over regions including the semiconductor substrate 1, the P+-type active region 3 and the N+-type active region 2.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tomoyuki Irizumi
  • Patent number: 6784118
    Abstract: In order to vaporize an organic monomer at a high temperature and a high saturated vapor pressure in good efficiency and to grow an organic polymer film at a high rate in high vacuum by a plasma polymerization reaction of the resulting organic monomer gas, a liquid divinylsiloxanebisbenzocyclobutene (DVS-BCB) monomer is mixed with a carrier gas, and the mixture is then sprayed on a vaporization vacuum chamber held at a high temperature to form an aerosol made of liquid fine particles of the organic monomer, and a BCB monomer (organic monomer) is instantaneously vaporized via the aerosol to generate a BCB monomer gas (organic monomer gas). Consequently, the aerosol having a large specific surface area has a large vaporization area, and vaporization occurs by heating at a high temperature before a polymerization reaction occurs. Thus, 0.1 g/min or more of the BCB monomer gas can be formed at 200° C.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: August 31, 2004
    Assignee: NEC Corporation
    Inventors: Yoshihiro Hayashi, Jun Kawahara, Hirofumi Ono
  • Patent number: 6784119
    Abstract: A method for processing a substrate comprising depositing a dielectric layer comprising silicon, oxygen, and carbon on the substrate by chemical vapor deposition, wherein the dielectric layer has a carbon content of at least 1% by atomic weight and a dielectric constant of less than about 3, and depositing a silicon and carbon containing layer on the dielectric layer. The dielectric constant of a dielectric layer deposited by reaction of an organosilicon compound having three or more methyl groups is significantly reduced by further depositing an amorphous hydrogenated silicon carbide layer by reaction of an alkylsilane in a plasma of a relatively inert gas.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 31, 2004
    Assignee: Applied Materials Inc.
    Inventors: Frederic Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh, Wai-Fan Yau, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Lu
  • Patent number: 6784120
    Abstract: A method is provided for more efficient application of a polymeric coating (e.g., die coat) to a substrate (e.g., wafer) surface. One aspect of the method comprises applying an organic liquid (e.g., organic solvent) to the wafer and spinning it to coat the entire wafer surface prior to the application of die coat. This reduces surface tension on the wafer and reduces the amount of die coat required to achieve a high quality film.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: John T. Davlin, Douglas S. Schramm, Lorna M. Mitson
  • Patent number: 6784121
    Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Changming Jin, Richard Scott List, Joseph D. Luttmer
  • Patent number: 6784122
    Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer
  • Patent number: 6784123
    Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus, and depositing a siloxan polymer film by plasma polymerization at a temperature of −50° C.-100° C. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant such as 2.5.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: August 31, 2004
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Yoshinori Morisada, Yasuyoshi Hyodo, Seijiro Umemoto
  • Patent number: 6784124
    Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Don Carl Powell
  • Patent number: 6784125
    Abstract: The invention provides a thermoplastic elastomer nonwoven fabric roll that exhibits minimal longitudinal wrinkles and minimal delayed restoration when unrolled, and method and apparatus for producing the same. Thermoplastic elastomer filaments that have been melt-spun are piled on a belt conveyor thereby forming a sheet of nonwoven fabric, that is guided to a rotating roller disposed above the transportation zone of the belt conveyor and peeled off therefrom. Since minimal tension is applied to the nonwoven fabric during processing, the nonwoven fabric can be unrolled with little stretching by applying relatively little tension to the nonwoven fabric. By the method of this invention, a nonwoven fabric roll with unrolling tension of 0.25 g/cm/basis-weight or less can be formed.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: August 31, 2004
    Assignees: Kanebo, Ltd., Kanebo Gohsen, Ltd.
    Inventors: Yukio Yamakawa, Tadashi Furuya, Tsutomu Teshima, Yutaka Tanaka
  • Patent number: 6784126
    Abstract: A high pulp content nonwoven composite fabric is disclosed. The composite fabric contains 1) from more than about 0 to less than about 30 percent, by weight, of a nonwoven layer of conjugate spun filaments, the filaments containing at least one low-softening point component and at least one high-softening point component and having at least some exterior surfaces of the filaments composed of at least one low-softening point component; 2) more than about 70 percent, by weight, of pulp fibers; and 3) regions in which the low-softening point component at the exterior surfaces of the filaments is fused to at least a portion of the fibrous component. This high pulp content composite nonwoven fabric may be used as a heavy duty wiper or as a fluid distribution material, cover material, and/or absorbent material in an absorbent personal care product. Also disclosed is a method of making the high pulp content nonwoven composite fabric.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: August 31, 2004
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Cherie Hartman Everhart, Danial Owen Fischer
  • Patent number: 6784127
    Abstract: A polyurethane elastomer fiber non-woven fabric contains polyurethane elastomer fiber filaments melt-bonded with one another, and has a tensile elongation of 100% or more, a 50% elongation recovery of 75% or more and a tear strength per METSUKE of 5.5 gf or more. The non-woven fabric can be prepared by a method of providing a thermoplastic polyurethane elastomer having Shore hardness A of 92 or more, drying the elastomer to a water content of 150 ppm or less, and melt-spinning and, at the same time, spraying it together with a high speed gas stream so as to deposit and laminate the elastomer into a sheet form. A synthetic leather using the non-woven fabric is also provided. The non-woven fabric has not only an excellent elasticity but also high tear strength.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 31, 2004
    Assignees: Kanebo, Limited, Kanebo Gohsen, Limited
    Inventors: Yukio Yamakawa, Tadashi Furuya, Eiji Kawabata, Yutaka Tanaka
  • Patent number: 6784128
    Abstract: The present invention provides an optical glass for press molding, in particular, a low softening point glass which contains, in an oxide glass of phosphate type, a durability improving component in addition to glass forming components, and has a weight loss of at most 0.15 weight % in a durability test, and which is represented, in term of elements for making up the glass, by the following chemical composition (mol %): P2O5   32 to 40% Li2O   6 to 21% Na2O   8 to 31% K2O   4 to 22% Al2O3  7.4 to 16% ZnO   0 to 19.6% BaO   0 to 12% and Sum of Li2O + Na2O + K2O 35.1 to 49%.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Sumita Optical Glass, Inc.
    Inventors: Masaaki Otsuka, Yoshinori Yamamoto, Koichi Tsuchiya, Naruhito Sawanobori, Shinobu Nagahama
  • Patent number: 6784129
    Abstract: The ultraviolet/infrared absorbent low transmittance glass has a grayish green color shade, low visible light transmittance, low total solar energy transmittance, and low ultraviolet transmittance, and is suitable for a rear window of a vehicle and capable of protecting privacy. The glass is formed of a base glass including: 65 to 80 wt. % SiO2; 0 to 5 wt. % Al2O3; 0 to 10 wt. % MgO; 5 to 15 wt. % CaO, wherein a total amount of MgO and CaO is between 5 and 15 wt. %; 10 to 18 wt. % Na2O; 0 to 5 wt. % K2O, wherein a total amount of Na2O and K2O is between 10 and 20 wt. %; and 0 to 5 wt. % B2O3, and colorants including: more than 0.95 wt. % and less than 1.2 wt. % total iron oxide (T-Fe2O3) expressed as Fe2O3; 0.001 to 0.0180 wt. % CoO; and 0.003 to 0.2 wt. % NiO.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: August 31, 2004
    Assignee: Nippon Sheet Glass Co., Ltd.
    Inventors: Hiromitsu Seto, Yukihito Nagashima, Shigekazu Yoshii
  • Patent number: 6784130
    Abstract: Inorganic powder as a plasma display panel material comprises a powdery material containing glass powder. The powdery material has a moisture content adjusted to fall within a range between 0.1 and 2 mass %. The powdery material may include the glass powder alone or may further comprise ceramics powder in addition to the glass powder. The inorganic powder may be used as a paste or a green sheet.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: August 31, 2004
    Assignee: Nippon Electric Glass Co., Ltd.
    Inventors: Yoshiro Morita, Hiroyuki Oshita, Masahiko Ouji, Kazuo Hadano
  • Patent number: 6784131
    Abstract: The present invention provides a silicon nitride wear resistant member composed of silicon nitride sintered body containing 1-10 mass % of rare earth element in terms of oxide thereof as sintering agent, wherein a total oxygen content of the silicon nitride sintered body is 6 mass % or less, a porosity of the silicon nitride sintered body is 0.5 vol. % or less, and a maximum size of pore existing in grain boundary phase of the silicon nitride sintered body is 0.3 &mgr;m or less. According to the above structure of the present invention, there can be provided a silicon nitride wear resistant member and a method of manufacturing the member having a high strength and a toughness property, and particularly excellent in sliding characteristics.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michiyasu Komatsu, Hiroki Tonai, Hiroshi Komorita
  • Patent number: 6784132
    Abstract: A method of recovering halogen-containing materials from the cyclic catalyst regeneration operation of a catalytic hydrocarbon conversion process is disclosed. The method uses an arrangement of beds of adsorbent to maintain the halogen-containing materials within a circulating regeneration circuit.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: August 31, 2004
    Assignee: UOP LLC
    Inventor: Paul A. Sechrist
  • Patent number: 6784133
    Abstract: Disclosed is a preparation method of titanium catalyst for olefin polymerization, the method comprising (1) preparing magnesium compound solution by resolving non-deoxidative magnesium halide and IIIA group atom compound in a solvent mixture of cyclic ether, at least one alcohol, phosphorus compound and organosilane with or without hydrocarbon solvent; (2) reacting said magnesium compound solution with titanium compound, silicon compound, tin compound or mixture thereof to produce a support; and (3) reacting said support with titanium compound and electron donor to produce solid complex titanium catalyst, wherein the particle size and particle size distribution f said catalyst are regulated by controlling solubility of the reactants in said steps (2) and/or (3).
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: August 31, 2004
    Assignee: Samsung Atofina Co. Ltd.
    Inventors: Il Seop Kim, Moon Young Shin, Ki Su Ro
  • Patent number: 6784134
    Abstract: A catalyst suited for catalytic vapor-phase oxidation of isobutylene, t-butanol or propylene to produce respectively corresponding unsaturated aldehyde and unsaturated carboxylic acid is provided. Said catalyst consists of ring-formed shaped bodies composed of (i) a catalyst composition containing at least molybdenum and bismuth as the active ingredients and (ii) inorganic fibers. The catalyst excels in mechanical strength, can give the object products at high yield and shows little activity degradation with time.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: August 31, 2004
    Assignee: Nippon Shokubai Co., Ltd.
    Inventors: Hiroto Kasuga, Eiichi Shiraishi
  • Patent number: 6784135
    Abstract: A composition is provided that can be used, for example, in a fuel processor for a fuel cell system. The composition includes a first material such as a catalyst, and a second material such as a desiccant. The second material is capable of sorbing and desorbing a heat transfer material such as water, and is present in an amount sufficient to sorb an amount of the heat transfer material sufficient to remove a portion of the heat generated when the first material undergoes an exothermic reaction.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: August 31, 2004
    Assignee: Power Plug, Inc.
    Inventors: Anton Scholten, Peter F. M. T. Van Nisselrooy, Walter R. De Jongh, Jan Stokman
  • Patent number: 6784136
    Abstract: Disclosed is a heat-sensitive recording material comprising a support and a heat-sensitive recording layer formed on the support and containing a leuco dye and a developer, the developer being N-p-toluenesulfonyl-N′-3-(p-toluenesulfonyloxy)phenylurea, and the heat-sensitive recording layer containing (a) at least one fluoran-based leuco dye with a melting point of 190 to 230° C. and/or (b) at least one pigment selected from the group consisting of aluminum hydroxide, amorphous silica, kaolin and talc.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: August 31, 2004
    Assignee: Oji Paper Co., Ltd.
    Inventors: Nobuyuki Iwasaki, Koichi Ishida
  • Patent number: 6784137
    Abstract: 4-Aminopicolinic acids having aryl or heteroaryl substituents in the 6-position and their amine and acid derivatives are potent herbicides demonstrating a broad spectrum of weed control.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 31, 2004
    Assignee: Dow AgroSciences LLC
    Inventors: Terry William Balko, Ann Marie Buysse, Jeffrey Brian Epp, Stephen Craig Fields, Christian Thomas Lowe, Renee Joan Keese, John Sanders Richburg, III, James Melvin Ruiz, Monte Ray Weimer, Renard Antonio Green, Roger Eugene Gast, Kristy Bryan, Nicholas Martin Irvine, William Chi-Leung Lo, William Kirkland Brewster, Jeffery Dale Webster
  • Patent number: 6784138
    Abstract: A method for maximising critical current density (Jc) of high temperature superconducting cuprate materials (HTSC) which comprises controlling the doping state or hole concentration of the materials to be higher than the doping state or hole concentration of the material that provides a maximum superconducting transition temperature (Tc), and to lie at about a value where the normal-state pseudogap reduces to a minimum. Jc is maximised1 at hole concentration p≈0.19. HTSC compounds are also claimed.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 31, 2004
    Assignee: Industrial Research Limited
    Inventor: Jeffery Lewis Tallon
  • Patent number: 6784139
    Abstract: The present invention relates to epitaxial, electrically conducting and mechanically robust, cubic nitride buffer layers deposited epitaxially on biaxially textured substrates such as metal and alloys. The invention comprises of a biaxially textured substrate with epitaxial layers of nitrides. The invention also discloses a method to form such epitaxial layers using a high rate deposition method as well as without the use of forming gases. The invention further comprises epitaxial layers of oxides on the biaxially textured nitride layers. In some embodiments the article further comprises electromagnetic devices which may be super conducting properties.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: August 31, 2004
    Assignees: Applied Thin Films, Inc., UT-Battelle, LLC
    Inventors: Sambasivan Sankar, Amit Goyal, Scott A. Barnett, Ilwon Kim, Donald M. Kroeger
  • Patent number: 6784140
    Abstract: A method of treating a well including injecting a thermally stable, substantially water-free well-treating fluid into the well, wherein the well-treating fluid comprises a polymer, a glycol compound, and a salt is disclosed. In another embodiment, a thermally stable, substantially water-free well fluid including a polymer, a diol compound, and a salt is disclosed.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: August 31, 2004
    Assignee: M-I L.L.C.
    Inventors: David P. Kippie, William E. Foxenberg
  • Patent number: 6784141
    Abstract: The present invention relates to methods, aqueous treating fluids and friction pressure reducers for the treating fluids. A treating fluid of the invention comprises water and a non-toxic environmentally acceptable friction pressure reducer comprising a mixture of a copolymer of acrylamide and dimethylaminoethyl acrylate quaternized with benzyl chloride and a stabilizing and dispersing homopolymer of ethanaminium,N,N,N-trimethyl-2-[(1,oxo-2-prbpenyl)oxy]-chloride.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: August 31, 2004
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Karen L. King, David E. McMechan, Jiten Chatterji
  • Patent number: 6784142
    Abstract: An additive package comprising one or more borated dispersants, one or more EC-treated dispersants, and one or more phenolic antioxidants; a lubricating oil composition comprising said additive package; and a method of controlling bearing corrosion and valve train wear using said lubricating oil.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 31, 2004
    Assignees: Chevron Oronite Company LLC, Chevron Oronite Technology B.V.
    Inventors: Willem Van Dam, Peter Kleijwegt
  • Patent number: 6784143
    Abstract: The use, in a minor amount, of a detergent composition comprising one or more metal detergents which comprises metal salts of organic acids, wherein the detergent composition comprises more than 50 mole %, based on the moles of the metal salts of organic acids in the detergent composition, of: (I) a metal salt of an aromatic carboxylic acid, or (II) a metal salt of a phenol, or (III) both a metal salt of an aromatic carboxylic acid and a metal salt of a phenol, in a lubricating oil composition for improving the oxidation resistance of the lubricating oil composition, wherein the amount of phosphorus and sulfur in the oil composition is less than 0.09 mass % and at most 0.5 mass % respectively, based on the mass of the oil composition. It has also been found that a detergent composition comprising more than 50 mole % of a metal salt of an aromatic carboxylic acid improves the reduction in wear in an engine.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: August 31, 2004
    Assignee: Infineum International Ltd.
    Inventors: Christopher J. Locke, Mark G. Stevens, Peter Wrench, Stephen Arrowsmith, Rebecca C. Castle, Jane R. Galsworthy
  • Patent number: 6784144
    Abstract: The invention describes a silicone oil emulsion stabilized with soap. The soap is formed in situ from one or more fatty acids and a cation of a base during the emulsification process. The invention also provides a method of forming a soap stabilized oil-in-water emulsion including the steps of forming a first mixture comprising a silicone oil, a base, and initial water, combining the first mixture with a fatty acid component and emulsifying the resultant combination.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: August 31, 2004
    Assignee: Dow Corning Australia Pty. Ltd.
    Inventor: David James
  • Patent number: 6784145
    Abstract: The invention relates to an article containing (A) a water-insoluble substrate and (B) containing an aqueous phase and N-(3-chloroallyl)hexaminium chloride. According to one preferred embodiment of the invention, the composition also contains at least one C1-C4 alkyl para hydroxybenzoate and/or at least one ethylenediamine-tetraacetic acid salt. The article may especially constitute a wipe for cleansing and/or removing makeup from the facial and/or body skin, and also for removing makeup from the eyes. The wipe may be in the form of a moist or dry wipe.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 31, 2004
    Assignee: L'Oreal
    Inventors: Patricia Delambre, Philippe Touzan, Pascal Simon
  • Patent number: 6784146
    Abstract: The present invention is a deinking method and composition that uses at least 50% by weight based on the total weight of surfactants of non-ionic, C16 to C25 aliphatic, monohydric alcohol alkoxylates having 14 to 40 moles of ethylene oxide per mole of alcohol and 0 to 10 moles of propylene oxide per mole of alcohol. Using deinking compositions to deink wastepaper pulp wherein the surfactants primarily include the C16 to C18 aliphatic alcohol alkoxylates of the invention produces paper having excellent brightness and low effective residual ink concentrations. In addition, a low amount of sizing agents is used to produce paper having acceptable levels of water repellency.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: August 31, 2004
    Assignee: Kemira Chemicals, Inc.
    Inventors: Jing Luo, David D. Dreisbach, Michael Lease Hemenway
  • Patent number: 6784147
    Abstract: A drain cleaner with soy methyl ester (SME) CAS #66784-80-9 utilized at 92.8% by weight, the emulsifier system composed of combination of lauramide DEA and secondary alcohol ethoxylate CAS #'s 120-40-1 and 68131-40-8 utilized at 7% and a butylated hydroxytoluene CAS #128-37-1 used as an anti-oxidant at 0.2%.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 31, 2004
    Assignee: State Industrial Products
    Inventors: David John Smith, Joseph A. Tomaro, Tammy G. Westerman
  • Patent number: 6784148
    Abstract: The present invention is a non-corrosive, low-fuming oven cleaning composition that can be used easily on vertical oven surfaces. The present invention is a cleaning composition containing a tripolyphosphate and a thickening agent to promote in adherence to vertical surfaces.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: August 31, 2004
    Assignee: Kay Chemical, Inc
    Inventors: Tami Jo Tadrowski, Karen Odom Rigley
  • Patent number: 6784149
    Abstract: The invention relates to laundry detergents and cleaners comprising microdisperse, hydrophilic silicate-containing particles. The particle diameter of the particles is preferably 1 to 500 nm. The addition of the silicate-containing particles leads to improved soil release with a simultaneous reduction in the tendency for resoiling.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: August 31, 2004
    Assignee: Clariant GmbH
    Inventors: Harald Bauer, Günther Schimmel
  • Patent number: 6784150
    Abstract: Disclosed are compositions comprising 1,1,1,3,3-pentafluoropropane, 1,1,1,3,3-pentafluorobutane and water, said compositions are environmentally desirable for use as blowing agents for polymer foam, refrigerants, aerosol propellants, metered dose inhalers, heat transfer media, and gaseous dielectrics.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: August 31, 2004
    Assignee: Honeywell International Inc.
    Inventors: Mary C. Bogdan, Hang T. Pham, David J. Williams, Leslie Bement, Ronald Riegel, Rajiv R. Singh, Kane D. Cook, Gary M. Knopeck