Abstract: The semiconductor integrated circuit has a power-on resetting circuit for activating a reset signal which initializes an internal circuit, for a predetermined period after a power supply is switched on, and then inactivating the reset signal. The inactivation timing of the reset signal is changed by a timing changing circuit. Therefore, the inactivation timing which has deviated due to fluctuations in the manufacturing conditions of the semiconductor integrated circuit can be adjusted to a normal value. This consequently allows reliable initialization of the internal circuit. In general, a power-on resetting circuit utilizes the threshold voltage of transistors to generate the reset signal. Here, the inactivation timing depends on the threshold voltage of the transistors. Changing the inactivation timing corresponding to the threshold voltage of the transistors implemented makes it possible that the timing changing circuit optimally adjusts the inactivation timing of the reset signal.

Abstract: A POR circuit includes a signal generator which has a PMOS transistor and a first and second resistors connected in series. The PMOS transistor is controlled in accordance with a DPWD signal. A first signal obtained by dividing a voltage difference between the ground voltage and the supply voltage is output from a first node between the first and second resistors. The POR circuit also includes an edge generator which includes a third resistor and an NMOS transistor connected in series, and an inverter coupled to a second node between the third resistor and the NMOS transistor. The NMOS transistor is controlled in accordance with a voltage of the first signal output from the first node. When the NMOS transistor turns on, a second signal having an edge waveform is generated at the second node, the first inverter outputs a third signal which is a reversal of the second signal.

Abstract: The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The method includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.

Abstract: A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: A circuit and method are given, to realize a high voltage output driver within a closed regulator loop with slew rate control, insensitive against supply voltage variations. The high-voltage front-end, essentially a slope detector, is implemented as a combination of a voltage-current with a current-voltage transformer circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only two discrete or integrated extended drain MOS components at low cost.

Abstract: A clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device. The clock generator includes a clock input circuit receiving an external clock signal, a reference voltage signal and an option signal, and outputting first and second clock signals; a clock driver receiving the first clock signal and outputting an internal clock signal in response to the option signal; and a detector receiving the second clock signal and outputting the option signal in response to a control signal.

Abstract: Two or more pulse width modulation stages, each having progressively higher resolution, are utilized to allow the lower resolution stage or stages to operate at lower clock speeds. Later stages are operated at higher clock speeds and thus a smaller portion of the total pulse width modulation circuit utilizes the higher clock speed. Additionally, later stages operate over smaller time intervals in order to reduce usage of the later stages.

Abstract: A sequential pulse train generator. Each stage of the sequential pulse train generator includes a dynamic shift register circuit, level shifter, and buffer composed of inverters. The dynamic shift register circuits, allow the pulse generator to operate with a low-voltage clock signal so that power consumption in transmission of the clock signal is reduced.

Abstract: A variable circuit for constructing a desired counter by changing the circuit configuration of the connection status of a plurality of flipflops. The flipflops may be arranged in first and second rows, or stages, whereby the flipflops of the first and second rows are interconnected.

Abstract: In order to ensure safe and reliable time-delayed signal outputting with a simple redundant structure of a circuit arrangement, a common actuating element acts on two timers with associated A/D converters. In this case, the time delay which is predetermined by the actuating element and is relevant for the outputting of the switching signal is determined by forming the difference between a total resistance, detected by measurement, and a first resistance element, detected by measurement. This is followed by a comparison of the difference, which reflects second resistance elements that is determined by computation, with a second resistance element which is determined by measurement. The switching signal is then output with a time delay when there is a match between the second resistance element determined by measurement and that determined by computation.

Abstract: A digital phase control method phase shifts a predetermined number of clock signals having the same frequency and having different phases at high precision and at high resolution as a whole with its phase interval maintained to keep a predetermined interval. The digital phase control method comprises the steps of preparing fourteen first multi-phase clock signals having a fixed phase, of preparing sixteen second multi-phase clock signals, of phase locking a specific clock signal of the fourteen first multi-phase clock signals with a particular clock signal of the sixteen second multi-phase clock signals, and of changing a combination of the specific and the particular clock signals to be phase-locked to phase shift the second multi-phase clock signals. In addition, in order to generate the second multi-phase clock signals, a delay line comprising ring-shaped chained delay buffers may be used.

Abstract: A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.

Abstract: A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency for each task can be supplied such that the power consumption is reduced. A clock generation unit is provided for generating a clock with a constant frequency, with a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.

Abstract: An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

Abstract: An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit.

Abstract: A level shift circuit encompasses a first transmission circuit configured to transmit a leading edge of an input signal, a second transmission circuit configured to transmit a trailing edge of the input signal, and a composite circuit configured to generate an output signal by synthesizing the leading edge and the trailing edge.

Abstract: In a current switching circuit, a complementary circuit switches, in response to an input signal, a pair of current mirror circuits between a first state, enabling the first of the current mirror circuits, through a first current mirror current and disabling the second of the current mirror circuits, and a second state, disabling the first of the current mirror circuits and enabling the second of the current mirror circuits, through a second current, mirror current such that at least one of the first and second current mirror currents flows through a level shift circuit as a level shift current.

Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an output terminal, and a first current generator is connected between a voltage reference and the output terminal for providing a first charge current to a control terminal of the power element, which is connected to the output terminal. The driver circuit also includes a second current generator connected in parallel with the first current generator. The second current generator is connected between the voltage reference and the output terminal, and provides the control terminal with a second charge current dependent on a voltage present at the input terminal. The input terminal is connected to a conduction terminal of the power element.

Abstract: A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.

Abstract: The present invention is a high-voltage generation circuit configured to sequentially activate a plurality of high-voltage pump circuits to precisely pump a level of high voltage. In one embodiment, the high-voltage generation circuit includes a high-voltage level detection unit for outputting a high-voltage detected signal, a high-voltage pump control unit for generating a control signal responsive to a detected signal, an oscillator for generating a pulse signal for driving a plurality of high-voltage pumps, a sequential delay unit for sequentially delaying the pulse signal from the oscillator, and a plurality of high-voltage pumps for pumping the high voltage based on a delayed pulse signal and the control signal.

Abstract: A constant voltage generating circuit has a reference voltage generating circuit of which the output voltage is controlled to be a constant voltage when the output voltage has risen, with an increase in the input supply voltage, to reach a predetermined voltage and that outputs the constant voltage as a reference voltage, a first transistor that turns on when the output voltage reaches the predetermined voltage to control the constant voltage output from the reference voltage generating circuit, a second transistor that is so connected that, when the first transistor turns on, a current proportional to the current flowing through the first transistor flows through the second transistor, and a signal output circuit that detects the current flowing through the second transistor to output a detection signal indicating that the constant voltage is being output.

Abstract: A switched capacitor current reference circuit generates an almost constant reference current across the parameters of process, voltage and temperature. A reference voltage is generated within the circuit, which eliminates the need for an external reference voltage. The reference current is generated by applying the reference voltage across a resistor emulated with a pair of switched capacitor circuits.

Abstract: A method and structure for supply gating low power electronic components uses low threshold gating transistors. The low power components operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

Abstract: A fast-setting DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled control circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.

Abstract: A switched low pass filter (18) minimizes transients generated during filter switching events and eliminates active circuit random noise. The switched low pass filter (18) includes a filter input terminal (26) for receiving an input base band signal, and an RC circuit (R1, C1, S1, S2) for receiving the input base band signal and for passing only a filtered portion of the input base band signal depending on a wide, mid or narrow band mode of filter operation. The switched low pass filter (18) also includes a transient reduction circuit (34) in switchable communication with the RC circuit (R1, C1, S1, S2) for minimizing transients and switching events caused by transitioning to the mid and narrow band modes of filter operation.

Abstract: A differentail amplifier with input gate oxide breakdown avoidance amplifies a difference between two signals while maintaining voltage drops across transistor utilized in the differential amplifier to below a gate oxide breakdown level. A pull up structure added to a traditional differential amplifier allows the circuit to be utilized in IO pads of an integrated circuit and to be composed of thin oxide transistor normally only found in the core circuitry of the integrated circuit and. The pull up structure is composed of three thin oxide transistors, the first transistor is connected in series with the other two, and the other two connected in parallel with respect to each other.

Abstract: In a contactless IC card system, a modulating circuit manufactured in an IC form is operable at a high power efficiency. The demodulating apparatus is configured to include: first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal, a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal, gate means for gating at least the second output signal, calculation means for adding, or subtracting the first output signal and the second output signal; and control means for controlling the operation of the gate means in response to a logic level of input data.

Abstract: An amplifier distortion reduction system obtains a distortion signal from the amplifier output and feeds the distortion signal back to the input side of the amplifier to cancel with the distortion produced at the amplifier output. For example, a signal to be amplified by an amplifier is received on a main signal path. The amplifier produces an amplified output with a non-distortion spectrum and a distortion spectrum. A sample of the amplified output is produced from the main signal path and placed on a feedback path. On the feedback path, the distortion spectrum is obtained from the sample amplified output. The distortion spectrum is phase and/or amplitude adjusted to produce the distortion signal. The distortion signal is placed onto the main signal path at the input side of the amplifier with the signal to be amplified to destructively combine with the distortion produced from the amplifier in amplifying the signal to be amplified.

Abstract: The present invention discloses a new family of switching amplifier classes called “class E/F amplifiers.” These amplifiers are generally characterized by their use of the zero-voltage-switching (ZVS) phase correction technique to eliminate of the loss normally associated with the inherent capacitance of the switching device as utilized in class-E amplifiers, together with a load network for improved voltage and current wave-shaping by presenting class-F−1 impedances at selected overtones and class-E impedances at the remaining overtones. The present invention discloses a several topologies and specific circuit implementations for achieving such performance.

Abstract: A dynamically controlled amplifier circuit includes a first difference circuit having a first primary differential amplifier and a first crossover differential amplifier running in parallel with the first primary differential amplifier. A second difference circuit has a second primary differential amplifier and a second crossover differential amplifier running in parallel with the second primary differential amplifier. An input terminal is coupled to control electrodes of the first primary differential amplifier and to control electrodes of the second primary differential amplifier. An output terminal of the first primary differential amplifier is coupled to control electrodes of the second crossover differential amplifier, and an output terminal of the second primary differential amplifier is coupled to control electrodes of the first crossover differential amplifier.

Abstract: A new all digital transistor CMOS very high DC-gain amplifier (30) that uses an internal positive-feedback technique. This amplifier (30) does not require perfect matching of transistors (M2,M3) to achieve the very high DC gain. The DC gain has a very low sensitivity to the output voltage swing. An implementation of a sample and hold circuit (60) constructed using the amplifier (30) is also described. A special layout pattern (80) is used to cut the parasitic capacitance to enhance the amplifier speed.

Abstract: A high switching speed differential amplifier comprises a differential pair, a first and a second active loads, and a current source, in which the differential pair is composed of a pair of MOS transistors to receive a pair of differential signals from a first and a second inputs. The first active load is connected to an output of the first MOS transistor and includes a first and a second paths switched therebetween in response to the first input. The second active load is connected to an output of the second MOS transistor and includes a third and a fourth paths in response to the second input.

Abstract: An apparatus for indicating a difference between a first voltage and a second voltage includes: (a) an input unit for receiving the first voltage at a first locus and receiving the second voltage at a second locus; the input unit quanitifying the difference; (b) an output unit coupled with the input unit and cooperating with the input unit to generate an output signal for effecting the indicating; and (c) a signal treating unit coupled with the output unit, the first locus and the second locus, and employing at least one algorithmic relation with at least one of the first voltage and the second voltage to generate at least one bias current for effecting a substantially balanced response by said output section in said generating said output signal as said difference varies. The at least one drive current has nonnegative values as the difference ranges in value.

Abstract: A voltage multiplier circuit includes a voltage-to-current converter, a current multiplier, and load devices. The voltage-to-current converter receives a differential input voltage, and produces a differential current. The differential current is received by the current multiplier, which produces a scaled output current. The amount of scaling is provided by a digital control word. Load devices produce a differential output voltage from the scaled output current. Multiple voltage-to-current converters and current multipliers can be coupled in parallel so that the scaled output currents sum.

Abstract: An amplifier comprising a Low Noise Amplifier (LNA) to amplify a Radio Frequency (RF) signal. The LNA having a transconductance and including an input stage to receive the RF signal. The LNA again varying as a function of changes in conditions. A bias assembly to generate a bias current to bias the LNA input stage. The bias assembly configured to reduce variation of the LNA gain to changes in conditions.

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract: A system and method are disclosed for providing amplification to an input signal. The amplifier comprises an amplification stage configured to provide a gain to an input signal and to produce an amplified output, wherein the amplification stage includes an interface configured to receive a biasing voltage. The amplifier also comprises a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage, whereby the peak detection feedback network controls the gain of the amplifier.

Abstract: A low noise amplifier with switchable gain settings comprises a cascoded emitter coupled pair (T1, T2, T5, T6; T3, T4, T7, T8) having a current diverter (T9, T10) which reduces the gain to an intermediate level in response to a control signal on terminals (8, 9). Further control signals on terminals (5, 10, 11, 12, 13) reduce the gain to a low level by introducing emitter degeneration (R3). To compensate for the increase in input impedance caused by the introduction of emitter degeneration feedback loops (C1, R8; C2, R9) are connected between the diversion path and the amplifier inputs.

Abstract: A voltage amplifying circuit (100) that may have a selectable gain has been disclosed. Voltage amplifying circuit (100) may include a voltage amplifier (2) and a gain changing unit (7). A gain changing unit (2) may be capable of changing at least one of: a capacitance between a signal input terminal (6) and an input terminal of a voltage amplifier, the capacitance between an input terminal of a voltage amplifier and a ground (or reference potential), and a capacitance between an input and an output terminal (3) of a voltage amplifier. In this way, a gain from a signal input terminal (6) to an output terminal (3) of a voltage amplifier of a voltage amplifying circuit (100) may be changed.

Abstract: A high frequency amplifier in which a common emitter bipolar transistor is used, and in that a constant current source and a constant voltage source are switched to apply a DC bias to a base terminal of the bipolar transistor in accordance with a power level of a high frequency signal input to the bipolar transistor or a power level of a high frequency signal output therefrom, and a frequency mixer in that a DC bias is applied to a base of at least one of a bipolar transistor for the input of a high frequency signal and a bipolar transistor for the input of a local oscillation wave by using a configuration for applying the DC bias to a base of an amplifying bipolar transistor employed in the high frequency amplifier.

Abstract: Embodiments of the present invention provide an amplifier circuit and method that can be used to save power or reduce distortion in an electronic system, such as a wireless communication system. In one embodiment, the present invention includes an amplifier circuit comprising a transistor having a gate terminal, drain terminal, body terminal, and a load. An input signal has different signal envelopes during different time periods. A control signal coupled to the body terminal is used to change the voltage on the body terminal when the input receives different envelopes. Accordingly, the amplifier can be biased to use less power when lower envelopes are being received. Electronic systems, such as wireless communication systems, can realize advantageous performance enhancements by utilizing the amplifier and other techniques employed by embodiments of the present invention.

Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.

Abstract: A circuit and method for correcting thermal deviations of one or more output signals from an amplifier utilizes Early effect-compensated correcting signals to reduce the thermal deviations of the output signals. The correcting signals are derived from temperature-dependent signals, which correspond to the thermal deviations of the output signal. The temperature-dependent signals, however, include errors due to Early effect. The Early effect errors are compensated in the correcting signals by introducing reverse Early effect errors into the correcting signals. Consequently, the compensating signals can be used to more effectively correct the thermal deviations of the output signals.

Abstract: An amplifier circuit and fabrication method including a bias input node, an RF input node, an RF output node, and a plurality of amplifier cells. Each cell has a plurality of discrete emitter contacts of a first conductivity type, a plurality of discrete base contacts of a second conductivity type and grouped in two or more groups, at least one collector contact of the first conductivity type connected to the RF output node, and a base capacitor for each group having two electrodes: an input electrode coupled to the RF input node and an output electrode coupled to a group of discrete base contacts. There is also a base resistor for each group having an input coupled to the bias input node and an output coupled to a group of discrete base contacts. An emitter resistor is coupled to each discrete emitter contact to provide more effective base ballasting and thermal stability than with a cascode arrangement of HBT transistors.

Abstract: A radio frequency (RF) power amplifying system. The power amplifying system includes a power controller and power amplifiers comprising power transistors and bias circuitry. The bias circuitry provides current to the base of the one or more power transistors in such as manner as to automatically maintain the power transistors in substantially linear operation throughout the variation in voltage as supplied by the power controller.

Abstract: According to some embodiments, a circuit includes a limiting amplifier, the limiting amplifier including an output node. The circuit also includes an active inductor coupled to the output node, and may exhibit a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.

Abstract: A transimpedance amplifier selectively activates DC compensation to optimize a signal-to-noise ratio for an optical receiver. The optical receiver includes a photodiode that converts a light signal to an electrical current signal, and the transimpedance amplifier converts the electrical current signal to a pair of differential voltage signals for further processing. The electrical current signal is provided to the transimpedance amplifier by connecting a cathode of the photodiode to a first input amplifier via a DC blocking capacitor and by directly connecting an anode of the photodiode to a second input amplifier. The transimpedance amplifier includes a DC correction circuit that generates a correction current when an output of the first input amplifier exceeds a predefined threshold. The correction current is added to an input of the second input amplifier to adjust a DC offset at an output of the second input amplifier.

Abstract: A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.

Abstract: A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.

Abstract: The invention relates to a method for modulating an output voltage of a transmitter circuit comprising a voltage controlled oscillator, a digital/analog converter and an antenna circuit, the method comprising the method comprising sending an output signal of sufficient power from the voltage controlled oscillator directly to the antenna circuit and directly modulating a frequency of the output signal of the voltage controlled oscillator. The invention furthermore relates to a transmitter circuit comprising a voltage controlled oscillator having a tank circuit, a digital/analog converter and an antenna circuit, wherein the voltage controlled oscillator is adapted to send an output signal of sufficient power directly to the antenna circuit and wherein the digital/analog converter is arranged to modulate an output frequency of the voltage controlled oscillator.