Abstract: In a signal reproduction block of a DVD reproduction apparatus, an output signal line for outputting a characteristic information signal representing a characteristic of a filter incorporated in the signal reproduction block to the outside is additionally provided on the output side of an A/D converter. In this way, it is possible to prevent an analog data signal from deteriorating during a data signal reproduction process due to a parasitic effect of the output signal line. Moreover, the filter characteristic information signal is output through the output signal line after it is convened to a digital signal by the A/D convener, thereby avoiding the deterioration the characteristic information signal and thus improving the measurement precision.

Abstract: A method is provided of setting grids and/or markers on a screen of a display unit of a measuring apparatus. First, a mode of the apparatus is changed into a mode of setting the grids and/or the markers. Then, the grid and/or the marker serving as a reference is set. Then, a plurality of grids and/or markers are set, each of which provides an arbitrary interval with respect to the grid and/or the marker serving as reference.

Abstract: A router for funneling a plurality of conductors is disclosed. The router includes a routing unit and a plurality of conductor paths. The conductor paths are directed through the routing unit and are adapted to receive the conductors. The routing unit and the plurality of conductor paths are formed by a three-dimensional fabrication process.

Abstract: A handling apparatus includes a main unit, a holder configured to hold an object, a retainer configured to retain the holder so as to allow the holder to displace with respect to the main unit, and a latch unit configured to selectively bring the holder into a latched state, in which the displacement of the holder with respect to the main unit is restrained, or an unlatched state, in which the displacement of the holder with respect to the main unit is not restrained.

Abstract: A signal generator for an internal combustion engine for obtaining precise information on a rotational direction of the engine when the engine runs at extremely low speed, comprising: a rotor having a first series of reluctor corresponding to a cylinder of the engine, and a second series of reluctor having a predetermined phase relationship relative to the first series of reluctor; and a first sensor and a second sensor that detect the first series of reluctor and the second series of reluctor, respectively of the rotor to generate pulses, wherein a positional relationship between the first and the second series of reluctors, and a positional relationship between the first and the second sensors are set so that a difference occurs in a phase relationship between an output pulse of the first sensor and that of the second sensor in forward rotation and in reverse rotation of the engine.

Abstract: The ring magnet speed and direction sensing scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a pair of bridges placed on the same semiconductor chip are provided for sensing the passing of north/south transition points on a ring magnet. In accordance with an exemplary embodiment, the bridge contains a first group of runners that are perpendicular to a second group of runners. The bridges are placed to cause the signal from one bridge to slightly follow the signal from the other bridge. Placement of the bridges on the same chip enables highly accurate readings.

Abstract: A transmitter assembly includes a sandwich made up of a three axis transmitter, driven by a transmitter driver, mounted on a permeable attenuator with a spacer interposed between the transmitter and the attenuator. The attenuator is mounted on top of a conductive plate. A compensation coil is provided and driven by a compensation coil driver that energizes the compensation coil to optimize compensation for magnetic field edge effects. A number of individual compensation coils may be arranged about the periphery of the conductive plate or permeable attenuator. The individual compensation coils in the modification may be activated in tandem or individually to compensate for non-uniform magnetic edge fields caused by he non-symmetrical configuration of, for example, three transmitter coils or, for example, a square permeable attenuator rather than a circular permeable attenuator.

Abstract: A rotation detecting apparatus including a drive gear rotatably supported by a case having a cover and capable of rotating cooperatively with an object to be detected, driven gears and brought in mesh with the drive gear and capable of rotating cooperatively therewith, magnets and provided at rotational center portions of the driven gears and having plane portions formed with N poles and S poles, a circuit board arranged at the case and capable of connecting to outside, magnetic reluctance elements attached to the circuit board and being opposed to the plane portions of the magnets and an electronic circuit part for converting an output signal of the magnetic reluctance element into a rotational angle signal, wherein the driven gears and are interposed by the case and the cover and a constant distance is maintained between the plane portion and the magnetic reluctance element.

Abstract: An apparatus for the nondestructive measurements of materials. Eddy current sensing arrays are described which provide a capability for high resolution imaging of test materials and also a high probabilitity of detection for defects. These arrays incorporate layouts for the sensing elements which take advantage of microfabrication manufacturing capabilities for creating essentially identical sensor arrays, aligning sensing elements in proximity to the drive elements, and laying out conductive pathways that promote cancellation of undesired magnetic flux.

Abstract: A self-adjusting assembly and method are disclosed. In the disclosed embodiments, a support assembly for supporting a device comprises a pair of support members for supporting the device. One of the members is adapted to help support the device from a ground, and another of the members is adapted to provide lateral support for the device and to permit free longitudinal movement of the device as it expands or contracts due to temperature variations.

Abstract: Generalized series-based image reconstruction as used in dynamic imaging for high-speed imaging with limited k-space coverage for each time frame. Further, in acquiring low resolution data for a plurality of image frames, a full k-space data set is generated for each time frame with the measured low-resolution data and high spatial frequency data generated by the GS model constructed based on the high-resolution image(s). The algorithms of the invention have computational complexity of O(N log N) and arc capable of producing high-resolution dynamic images with a small number of Fourier transform samples.

Abstract: A MRI array coil for imaging a patient having a head, and a torso, includes a base; a left handle extending from the base; a left head coil array attached to the left handle for proximity to the head; a right handle extending from the base; and a right head coil array mounted on the right handle for proximity to the head.

Abstract: A probe serving for detecting the structure of a dielectric medium. The probe includes at least one transmitter/receiver antenna located near a dielectric boundary surface that defines a dielectric medium, and a signal processor for receiving signals from the antenna and generating data representative of the structure of the dielectric medium. Between the antenna and the face is inserted a cushion of a material having a dielectric number higher than that of the air. In one embodiment, the probe is adapted to inspect if there is a void in the soil around a dielectric pipe, for example a sewer pipe. In this case, the probe is guided inside the pipe with the antennas located on a shaft mounted on the probe with the same axis as the axis of the pipe. Due to the presence of the cushion, an optimally good connection between the antennas and the face defining the dielectric medium is obtained.

Abstract: A system and method for estimating the remaining life of a light bulb, which includes a device for determining cold filament resistance of the light bulb while the light bulb is in a non-operating mode, a comparison device for comparing the cold filament resistance of the light bulb to a reference near an end of its life filament resistance, and a device for displaying an indication of a life expectancy for the light bulb. The system may be integrated into a vehicle or may be portable.

Abstract: An apparatus for testing an electrical device which includes fuses has a resilient, compressive, insulating base amounted to the underside of a thermal head. A plurality of conductive elements are mounted to the base in parallel relation. A number of these conductive elements are caused to be brought into contact with and bridge a fuse of the device when the thermal head is brought in dose proximity to the device. The conductive elements cause the fuse to be bridged, so that connection is provided between one side of the fuse and the other.

Abstract: An electrical voltage arrangement to be provided with selectively different electrical input variables, for example in the form of a unidirectional voltage, a bidirectional voltage or a unidirectional current, can be converted into an impressed electrical output voltage. At the same time, there is to be a predefined relationship between the input variable and the output voltage. The circuit arrangement contains a first arithmetic circuit which converts a voltage fed to it into a first impressed voltage, and a second arithmetic circuit which converts an input voltage fed to it into a second impressed voltage. The voltage which is present at the input terminals of the circuit arrangenent is fed to the first arithmetic circuit. The voltage which drops across a resistor which can be connected to the input terminals of the circuit arrangement is fed to the second arithmetic circuit.

Abstract: A dual-chambered anechoic chamber used in conjunction with spatial averaging for making transmission measurements of electromagnetic devices. The anechoic chamber includes a first tapered chamber with a first aperture, a second tapered chamber with a second aperture opposed to the first aperture, an alignment apparatus for aligning the two chambers and, if necessary, for positioning a test device between the apertures, and a positioning mechanism for mounting and determining the position of a transmitter antenna. A receiver antenna in the second chamber receives test signals transmitted from the transmitter antenna. At selected transmitter antenna positions, measurements are taken at different frequencies. For each transmitter position, a measurement is made with the test device positioned between the apertures, and another without the test device. When all desired measurements have been made, the measurement data are spatially averaged; i.e.

Abstract: A Moisture and Density Detector (MDD) that provides a method and apparatus to determine the moisture content and/or density of any dielectric material for various purposes. This device is very useful in detecting the moisture content (MC) of wood and wood-based materials, such as that of lumber in a dry kiln prior to, during and/or following drying. The MDD passes a radio frequency signal between opposed or adjacent capacitance electrodes and measures the signal strength and phase shift of the signal. The addition of phase shift and multiple frequencies improves the accuracy of the results.

Abstract: A method and apparatus for detecting areas of differential density in logs, cants, timbers, poles or trees comprises applying a signal to one or more pairs of electrodes and measuring the magnitude and phase shift of the voltage, current or impedance at an output electrode. Electrodes may be arranged in a circumferential or opposed configuration depending on scanned product shape, and may be stationary or move freely but are preferably in direct contact with wood surface. Wire brush electrodes are used in some embodiments. Measurements are taken in both directions between an electrode pair. Multiple frequencies may be employed. Different electrode sizes may be used for different measurements.

Abstract: A condition sensor for a fabric treating apparatus, such as a clothes dryer. A condition sensor is connected to a base wherein the condition sensor is operative to sense a condition such as moisture content for a multi-layered load placed within the dryer. The condition sensor comprises at least one support connected to the base wherein the at least one support has at least one extension attached thereto. A pair of capacitance sensors are attached to the at least one extension with the pair of capacitance sensors being arranged to build up charge through the condition sensor based on the moisture of the load content positioned in the dryer. A circuit is arranged to receive, read and generate signals in response to the charge of the capacitance sensors.

Abstract: A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

Abstract: A test fixture adapter for a printed circuit assembly tester is presented. The test fixture adapter implements the universal portions of the tester-to-fixture interface and allows mounting of a customized fixture interface printed circuit board thereon. The fixture interface printed circuit board and the fixture itself are completely separate. The adapter may be reused from one board design to the next, requiring only that a customized fixture interface printed circuit board and a customized fixture be redesigned and manufactured.

Abstract: A method and structure to establish and maintain an electrical connection between electrical contacts. A bladder is placed within a fixture and pressurized. The pressurized bladder applies a force that will establish and maintain an electrical connection between a first contact pad and a second contact pad.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: A wafer test apparatus for bringing the contact areas of the integrated circuits to be tested into electrical connection with the test contacts as uniformly as possible and therefore with relatively low necessary contact pressures. The test apparatus has a chuck for holding a wafer having at least one integrated circuit with a group of contact areas which define a wafer surface profile. A test head is configured opposite the chuck and has a performance board, on which a probe card with contacts for making contact with the contact areas of the integrated circuit is configured. Areas of the contacts, of the probe card, which are intended to come into contact with the contact areas define a test surface profile. Actuators are configured on the probe card for aligning the test surface profile in parallel with the wafer surface profile and for changing the distance between the performance board and the contacts in a direction substantially orthogonal to the wafer surface profile.

Abstract: A probe tower for an automatic test system includes an insulative retainer for holding an array of differential probe assemblies. Each differential probe assembly is an elongated structure having first and second ends and first and second coaxial portions. Each coaxial portion includes an outer conductor and a pair of annular insulators positioned therein for holding a center conductor. First and second contact pins extend from the center conductor at the first and second ends, respectively. First and second ground pins, which are electrically connected to the outer conductors of the first and second coaxial portions, extend from the first and second ends for conveying ground connections.

Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.

Abstract: A semiconductor integrated circuit testing system for testing electric characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer in the lump includes a wafer tray for holding the semiconductor wafer and an interconnect substrate facing the semiconductor wafer held on the wafer tray and having interconnect layers to which a testing voltage is externally input. A ring-shaped sealing member is provided between the wafer tray and the interconnect substrate so as to form a sealed space together with the wafer tray and the interconnect substrate. An elastic sheet is held on the interconnect substrate at the periphery thereof. A plurality of probe terminals electrically connected to the interconnect layers are provided on the elastic sheet in positions respectively corresponding to external electrodes of the plural semiconductor integrated circuit devices.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current profile is recorded. A comparison of current profiles obtained for the two types of structures may indicate the presence and/or extent of STI corner effects. More specifically, a steeper slope for a normalized current versus time plot for an STI edge intensive structure (500) compared to a slope of a normalized plot of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness is observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

Abstract: The circuit configuration allows selective transmission of information items to a chip of a wafer during chip fabrication, and an apparatus having a needle card. During the test procedure of chips of a wafer which are tested in parallel, the problem can arise that, by way of example, an individual chip has a repairable defect or an incorrectly set voltage. Since a plurality of chips, for example memory modules, are tested simultaneously by a measuring device, it is not readily possible to transmit targeted information items to the individual chip. An external memory is thus assigned to each contact array on a needle card. In that memory, the individual information items are buffer-stored and transmitted to the individual chip. This affords the advantage that specific defective chips can be repaired in a simple manner without additional, costly control devices being necessary.

Abstract: In a testing board (300C), one end of each of a plurality of first wirings (310) and one end of each of a plurality of second wirings (320) are connected to a common point (340). The other end of each of the second wirings (320) is connected to a terminal (12a-12f) of a semiconductor device (10) under test. The second wirings (320) have almost the same length. Signals outputted from drivers of a tester pin (130) to the first wirings (310) are composed at the common point (340), and the composite wave is inputted to the terminal (12a-12f) through each of the second wirings (320). A relay (350) is provided at a midpoint of each of the second wirings (320) and is controlled such that the signals can be inputted to, for example, the terminal (12b) from the driver of the tester pin (130) through one of third wirings (330).

Abstract: A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Abstract: When a test pattern is output that shows that a program has shifted to a subroutine, a subroutine stay time measuring circuit starts counting a count value that shows a program stay time in the subroutine, and outputs return instruction data when the count value reaches a predetermined value. A sequence control circuit controls a program counter value so that the program returns to a call originating routine when the sequence control circuit receives the return instruction data and also when a test pattern that shows that the program returns from the subroutine to the call originating routine is output.

Abstract: A diagnostic device for drive circuits has first and second relays each with a movable contact for switching between a normally closed and open contact, a motor are connected to the contacts, first and second resistance voltage dividing circuits connected between the contacts and a reference potential point, a switching circuit connected between two the closed contacts and the reference potential point, and a diagnostic section. The diagnostic section diagnoses a state of supply of drive power to the motor based on voltage-division outputs of the first and second resistance voltage dividing circuits. A bias voltage is supplied to a connection point between the normally closed contacts and the switching circuit. An additional resistance voltage dividing circuit is connected between the connection point and the reference potential pointy. The connection between the motor and a circuit driving the motor based on a voltage-division output of the additional voltage dividing circuit.

Abstract: According to some embodiments, provided are a first signal line, the first signal line coupled to a first repeater, the first repeater to convert a first signal from a received signal level to an output signal level, the first repeater to convert from a first signal level to a second signal level slower than from the second signal level to the first signal level, and a second signal line adjacent to the first signal line, the second signal line coupled to a second repeater adjacent to the first repeater, the second repeater to convert a second signal from a second received signal level to a second output signal level, the second repeater to convert from the first signal level to the second signal level slower than from the second signal level to the first signal level, wherein the received signal level is substantially equivalent to the second output signal level and wherein the second received signal level is substantially equivalent to the output signal level.

Abstract: A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

Abstract: Disclosed is an input/output (IO) device having a power supply node, an input node for receiving an input data signal, and an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal. The IO device also includes a pull-up driver coupled to the power supply node and the output node, wherein the pull-up driver comprises an impedance at the output node which is constant for all voltages at the output node. Additionally, the IO device may have a circuit coupled to the input node, the pull-up driver, and the output node. This circuit is configured to generate a signal that is provided to the pull-up driver. The signal generated by the circuit varies as a function of the voltage at the output node.

Abstract: An integrated circuit can be operated in at least three different organization forms that can be set externally. A connection pad receives an external signal for stipulating one of the organization forms. An input of a control circuit for setting one of the organization forms is connected to the connection pad. Depending on the signal on the connection pad, the control circuit can generate at least three different states at the output to identify the respective organization forms. When the signal state has been read and the corresponding organization form has been activated, the control circuit is disconnected from a voltage supply for the integrated circuit. The inventive circuit allows the number of connection pads for stipulating the organization form to be kept low.

Abstract: Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on values stored in configuration memory cells, but also under the control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator, enabling the implementation of an 8-to-1 multiplexer using only a single function generator. Another embodiment applies the concept of mixed memory cell and user control of a multiplexer to the general interconnect structure of an FPGA.

Abstract: An I/O buffer circuit is disclosed which includes protection circuitry to allow the I/O buffer circuit to tolerate multiple voltages. Further, the buffer circuit is adapted to have little to no leakage current. The buffer circuit includes an output portion that consists of a PMOS transistor in series with two NMOS transistors. Further, the PMOS transistor is controlled by a protection circuit that is operative to prevent leakage current.

Abstract: A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.

Abstract: A domino circuit topology that includes a dynamic circuit, logic circuit, and static circuit. The domino circuit includes a dynamic circuit, logic circuit, and static circuit coupled through a central node. The dynamic circuit includes a pre-charge circuit and a keeper circuit for pre-charging the central node and keeping the central node at its current voltage level. The static circuit provides a static output for the domino circuit. The logic circuit provides logical functions for input signals. In addition, the domino circuit can include an isolation transistor coupled between the central node and the logic circuit.

Abstract: Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: A sense amplifier having improved common mode rejection has a differential input and a differential output. A first level shifting transconductance circuit is connected to receive the differential input. A gain and compensation circuit is connected to the level shifting transconductance circuit, and a buffer is connected to the gain and compensation circuit. The differential output of the sense amplifier is taken at an output of the buffer. A feedback network is connected between the output of the buffer and an input of the gain and compensation circuit. The feedback network includes a divider circuit connected to the output of the buffer and a second level shifting transconductance circuit connected between the divider circuit and the input of the gain and compensation circuit. The first and second level shifting transconductance circuits are preferably matched to one another for distortion cancellation.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: An input buffer circuit has a pass gate circuit coupled to an input. A pseudo-differential amplifier is coupled to the pass gate circuit. A level shifter is coupled to the pseudo-differential amplifier.

Abstract: A CMOS buffer circuit includes (1) a first CMOS inverter having a first p-channel MOSFET, which has a first threshold value that becomes smaller as the temperature rises and which is rendered ON when a digital signal exceeds the first threshold value, and a first n-channel MOSFET, having a second threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the first p-channel MOSFET, when a digital signal exceeds the second threshold value; and (2) a second CMOS inverter having a second p-channel MOSFET, which has a third threshold value that becomes smaller as the temperature rises and which is rendered ON when the first inverted signal exceeds the third threshold value, and a second n-channel MOSFET, having a fourth threshold value that becomes smaller as the temperature rises, that is rendered ON, complementary to the second p-channel MOSFET, when the first inverted signal exceeds the fourth threshold value.

Abstract: The present invention provides a Driver circuit having dynamically adjusting output current and limiting input current function. This present invention dynamically adjusts the output current provided by the driver unit to reduce this output current in real time. A protection circuit is also provided to limit the input current supplied to the driver unit. This present invention avoids overdriving the driver unit.

Abstract: In order to reduce slew rate and minimize delay skew, the invention adds a pull-down booster circuit connected to the gate of the driving transistor and/or a pull-up booster circuit connected the gate of the driving transistor. The pull-down booster circuit is adapted to dynamically pull-down the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from a first voltage (e.g., a logical “0”) to a second voltage (e.g., a logical “1”). The pull-up booster circuit is adapted to dynamically pull-up the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from the second voltage to the first voltage.