Abstract: Communication from a processor in a computer system to a remote input/output (I/O) unit in an expansion drawer using a Peripheral Component Interface (PCI) protocol is optimized to improve system performance. An InfiniBand (IB) protocol link is used to couple the I/O unit to the computer system. In one case the computer system uses a PCI to IB bridge to couple from the processor to a corresponding IB to PCI bridge in the expansion drawer which couples to the I/O unit using a PCI link. Intelligence is added to the PCI to IB bridge to optimize communication by assigning selected PCI command sequences to optimized Macro IB commands. The IB to PCI link has like intelligence to receive and convert the Macro IB commands to the corresponding selected PCI command sequences. Optimization is accomplished by either a learning routine or by a logic state machine that generate the optimized Macro commands.

Abstract: A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units.

Abstract: There is provided an information recording/recording device that can easily modify the respective reproduction control programs and other programs of plural disk drive units simply by mounting an information recording medium in one disk drive unit. One disk drive unit uses predetermined recording information of a mounted information recording medium to rewrite a program stored in a nonvolatile memory of the one disk drive unit, and transfers a program to another disk drive unit over an interface bus to instruct program rewriting. According to the rewriting instruction from the one disk drive unit, the other disk drive unit rewrites a program stored in a nonvolatile memory thereof. If the information recording medium is reproduced in one disk drive unit, program information can be transferred to a different disk drive unit.

Abstract: A dirty memory for a computer system is configured hierarchically. This provides for more rapid identification of pages of memory that have been dirtied and require attention. For example for the reintegration of an equivalent memory state to the memories of respective processing sets in a fault tolerant computer following a lockstep error. The dirty memory includes at least two levels. A lower level includes groups of dirty indicators, each dirty indicator being settable to a given state indicative that a page of memory associated therewith has been dirtied. At least one higher level includes dirty group indicators settable to a predetermined state indicative that a group of the lower level associated therewith has at least one dirty indicator in a state indicative that a page of memory associated therewith has been dirtied. There can be more that two layers. Logic controls the operation of the hierarchical dirty memory.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device performs memory access operations using mode data that can be stored in a non-volatile mode register. The mode data can be copied into a volatile mode register. Both the non-volatile and volatile mode register can be edited during operation.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device in one embodiment can comprise control circuitry to perform an initialization operation on the synchronous memory, and a status register having at least one data bit that can be programmed to indicate if the initialization is being performed. A method of operating a memory system includes initiating an initialization operation on a memory device, and monitoring a memory status register to determine when the initialization operation is completed.

Abstract: A method and apparatus for servicing massive interrupts in random access memory (RAM) are provided, comprising receiving a massive interrupt signal, and reading at least one unit interrupt register in a first RAM area in response to the massive interrupt signal. A set unit interrupt bit corresponds to an address in a second RAM area. Interrupt status registers are read at the corresponding address in the second RAM area in response to the set unit interrupt bit. A set interrupt status bit corresponds to an address in a third RAM area. Interrupt cause bits are read at the corresponding address in the third RAM area in response to the set interrupt status bit, and detailed information is obtained about the interrupt. The interrupt is serviced in accordance with the detailed information.

Abstract: A mass storage system. Two or more dissimilar non-volatile storage mediums have the appearance to an operating system of a single device. In an embodiment, the storage mediums are located within a hard disk drive. In a further embodiment, the non-volatile storage medium is block oriented.

Abstract: Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. Redundancy information corresponding to each segment also is distributed randomly over the storage units. The redundancy information for a segment may be a copy of the segment, such that each segment is stored on at least two storage units. The redundancy information also may be based on two or more segments. This random distribution of segments of data and corresponding redundancy information improves both scalability and reliability. When a storage unit fails, its load is distributed evenly over to remaining storage units and its lost data may be recovered because of the redundancy information.

Abstract: A system and method for caching multiple versions of a data item (e.g., web page, portion of a web page, data table, data object) and determining which of the multiple versions is most responsive to a particular request. A request is received and an initial cache lookup is done with a data identifier (e.g., URL, URI) extracted from the request. If the lookup is unsuccessful (i.e., nothing is returned), the request is passed to an origin server (e.g., web server, data server). If the lookup is successful, it may provide or identify the desired data item (if one version of the data item is served for all requests) or a policy to be applied to determine which version to serve. The cache applies the policy, which identifies the additional parameters, cookies or other information to be considered, and a second lookup is done with the additional information.

Abstract: A data processing apparatus has a main memory that contains memory locations with mutually different access latencies. Information from the main memory is cached in a cache memory. When cache replacement is needed selection of a cache replacement location depends on differences in the access latencies of the main memory locations for which replaceable cache locations are in use. When an access latency of a main memory location cached in the replaceable cache memory location is relatively smaller than an access latency of other main memory locations cached in other replaceable cache memory locations, the cached data for that main memory location is replaced by preference over data for the other main memory locations, because of its smaller latency.

Abstract: Provided is a method, system, and program for destaging data from a first computer readable medium to a second computer readable medium. A list of entries indicating data blocks in the first computer readable medium is scanned. For each entry scanned, a determination is made as to whether the data block indicated in the scanned entry satisfies a criteria. If the data block indicated in the scanned entry satisfies the criteria, then a destage operation is called to destage the data block in the scanned entry from the first computer readable medium to the second computer readable medium. If the called destage operation is not initiated, then the scanned entry is removed from the cache list. The removed scanned entry is added to one destage wait list. During one destage operation, data blocks indicated in entries in the destage wait list are destaged.

Abstract: A data processing system (20) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache (38). When attempting to be backward compatible with previously written code, sometimes performing this instruction can result in attempting to prefetch redundant data by prefetching the same data twice. In order to prevent this, the parameters of the instruction are analyzed to determine if such redundant data will be prefetched. If so, then the parameters are altered to avoid prefetching redundant data. In some of the possibilities for the parameters of the instruction, the altering of the parameters requires significant circuitry so that an alternative approach is used. This alternative but slower approach, which can be used in the same system with the first approach, detects if the line of the cache that is currently being requested is the same as the previous request. If so, the current request is not executed.

Abstract: A system and method for verifying cache coherency in a multi-node, NUMA system includes a transaction modification unit configured to receive event traces generated by a simulation tool. The modification unit modifies transactions that are propagated to another node in the NUMA system and thus result in two bus transactions, a home node transaction (HNT) and a foreign node transaction (FNT). More specifically, the modification unit merges a FNT and its corresponding HNT into a single merge transaction (MT) under a prescribed set of merging rules. The MT has properties of the both the FNT and the HNT. The FNT and HNT are deleted from the event trace and replaced by their corresponding MT to create a modified event trace that is suitable for coherency checking by a single system coherency checker.

Abstract: A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received.

Abstract: A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.

Abstract: A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA_Write With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations.

Abstract: A dirty memory that includes dirty indicators settable to indicate dirtied pages of memory is provided with control logic operable automatically to interrogate the dirty memory to identify dirty indicators that are set. Implementing the control of the dirty RAM in hardware or firmware enables interrogation of the dirty RAM to identify set dirty indicators in a rapid and reliable manner. The control logic can advantageously be operable to interrogate the dirty memory word-by-word to determine words including a set bit. A comparator can be provided for comparing bits of a word to a predetermined value to determine where a dirty indicator is set. The comparison could be performed serially for bits within a word, but it is advantageously done in parallel for the bits of the word. For example, by using associative memory, the interrogation of the dirty memory could be effected associatively in parallel to determine words including a word with a set bit.

Abstract: A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of the system that share the cache line, and is encoded into a fixed length field having a number of bits that is significantly less than the number of the entities. The share mask is utilized for maintaining coherency among shared data in the system. Before a request to access a location of a memory is granted, the share mask is used to identify each entity or a group of entities that share the particular location, and an invalidate message is sent to each of the identified entity or group of entities. The alias signature in the directory tag is compared with an alias signature computed from the memory access request to prevent data corruptions that may occur due to incorrect memory aliasing.

Abstract: A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of classification and handling of address conflicts within a system to minimize the impact that address ordering places in a multiprocessor system with multiple memory control agents generating potentially conflicting addresses. A set of classification for each potential transaction conflict is provided against which decisions are provided which identifies the earliest point at which a subsequent transaction within the system may proceed to the same address identified by a previous transaction in the system. Classification of transactions are provided in several high level classes which define how such transactions within the system are handled based on the method disclosed.

Abstract: A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a memory interface, a program memory coupled to the memory interface, and a plurality of memory/processing units coupled to the memory interface and the program memory. Each of the memory/processing units includes a system memory and a processor coupled to the respective system memory. Instructions for the processors are transferred to the program memory and stored in the program memory responsive to a first set of addresses on the address bus of the mother-board. The processors then execute the instructions from the program memory, and may access the system memory during execution of the instructions. The system memory may also be accessed through the data bus of the mother-board responsive to a second set of addresses on the address bus of the mother-board.

Abstract: A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory module for storing data thereon. The memory module comprises a memory component having a first set of interface connections for providing access to a memory core of the memory component and a second set of interface connections for providing access to the memory core of the memory component. The memory module also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.

Abstract: A method and system for managing data in a data processing system are disclosed. Initially, data is stored in a first portion of the main memory of the system. Responsive to storing the data in the first portion of main memory, information is then stored in a second portion of the main memory. The information stored in the second portion of main memory is indicative of the data stored in the first portion. In an embodiment in which the data processing system is implemented as a multi-node system such as a NUMA system, the first portion of the main memory is in the main memory of a first node of system and the second portion of the main memory is in the main memory of a second node of the system. In one embodiment, storing information in the second portion of the main memory is achieved by storing a copy of the data in the second portion. If a fault in the first portion of the main memory is detected, the information in the second main memory portion is retrieved and stored to a persistent storage device.

Abstract: A method for maintaining a common resource shared by a plurality of entities, wherein the common resource contains a plurality of entries each of which is associated with one of the plurality of entities, includes the steps of determining an amount of the common resource occupied by entries associated with a given one of the plurality of entities; and removing a number of the associated entries from the common resource to reduce the occupied amount if the occupied amount exceeds a predetermined threshold.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

Abstract: Clients are connected via a LAN to backup apparatus including hard and tape drives, respectively primary and secondary backups. Each client schedules backup operations on a time basis since last backup, the amount of information generated since last backup, etc. Prior to a backup, each client sends to the backup apparatus a request including information representing the files to be backed up. The backup apparatus receives backup requests from the clients and accepts or rejects backup requests based on backup and network loading. The backup apparatus eliminates redundant files and indicates to the clients, prior to the file back up, that some files requested to be backed up are already stored and are not to be sent. The backup apparatus enables a client to restore any of its ‘lost’ data by copying it directly from the disk, without the need for backup administrator assistance.

Abstract: An image is received in response to a specification. The image represents information. In response to the received image, the information is installed onto a first portion of a computer-readable medium. The received image is stored on a second portion of the computer-readable medium so that, even after the information is installed onto the first portion, the stored received image is retained on the second portion for subsequently reinstalling the information onto the first portion.

Abstract: Improved systems and methods for storing data, wherein data stored on one or more disks of a first capacity is mirrored to one or more disks of a second, larger capacity. According to the invention, one or more disk drives of a first capacity may be coupled to create a virtual volume. One or more disks of a second, larger capacity are then used to provide a single larger volume or multiple larger volumes that serve as the mirroring drive or drives for the array of smaller drives. Data from the smaller drives is stacked in stripes sequentially across the larger drive(s). Alternately, data from the smaller drives may be striped in zones across the larger drive(s). In yet another embodiment, the asymmetric nature of the mirroring technique of the present invention can be used in reverse, wherein an array of smaller capacity drives serve as the mirror for one or more larger capacity drives.

Abstract: A virtual copy of data stored in a first memory is created in a second memory. Creating the virtual copy includes, in one embodiment, creating first and second tables in memory each one of which comprises a plurality of multibit entries. Each entry of the first table corresponds to a respective memory region of the first memory. Each entry of the second table corresponds to a respective memory region of the second memory. The first bit of the first and second tables indicates whether the corresponding memory region of the first and second memories, respectively, contains valid data. The second bit of the first and second tables indicates whether data in the corresponding memory region of the first and second memories, respectively, has been modified since the creation of the first and second tables, respectively.

Abstract: An apparatus is provided for providing security in a computer system. The apparatus comprises an address generator, a multi-level lookup table, and a cache. The address generator is adapted for producing an address associated with a memory location in the computer system. The multi-level lookup table is adapted for receiving at least a portion of said address and delivering security attributes stored therein associated with said address, wherein the security attributes are associated with each page of memory in the computer system. The cache is a high-speed memory that contains a subset of the information contained in the multi-level lookup table, and may be used to speed the overall retrieval of the requested security attributes when the requested information is present in the cache.

Abstract: A processing method for copying between storage device data regions and a memory system are provided to allow immediate access in a state of having completed copying in response to a copy instruction, even when actual data is being copied in a remote system, thus preventing a decrease in the performance of the access to the copy source during copying. Processes include copying data in a data region of a copy source to an intermediate media data region for each prescribed block unit in response to a copy instruction, as well as copying the data copied to the intermediate media data region to a copy destination data region. Processes also include interrupting copying and processing an access when there is an external access for a block of the copy source or the copy destination data region during the copy processing.

Abstract: In a storage system, a plurality of logical disks are constituted by combining a plurality of physical disks. A logical disk management unit converts input/output (I/O) requests addressed to the logical disks into I/O requests addressed to corresponding physical disks, and outputs the converted I/O requests. A physical disk management unit accesses the corresponding physical disks in accordance with the I/O requests which are output from the logical disk management unit and addressed to the physical disks. A logical disk relocation control unit relocates the logical disks so as to set the busy rates of the physical disks within a range between the first state in which the ratio of the busy rates of the physical disks is equal to the ratio of the I/O processing performance values of the physical disks, and the second state in which the busy rates of the physical disks are leveled. A data relocation method is also disclosed.

Abstract: A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Abstract: A method for enforcing a service discrimination policy in a storage system. The service discrimination policy enforcement method can include monitoring load metrics for physical resources required to access content stored within the storage system. A request to access the content stored within the storage system can be received. A corresponding guaranteed service level can be identified from the request. In consequence, a particular one of the physical resources can be selected to service the request based upon a determination that the selected physical resource can service the request while satisfying the guaranteed service level at a load indicated by the monitored load metrics.

Abstract: A processing of data in cooperation with a memory (MEM), for example an MPEG decoding, has the following characteristic features. A processor (P) generates a logic request (LRQ). The logic request (LRQ) defines at least one characteristic (CAR) common to a group of data (GRP). An addressing circuit (AGA) generates a physical request (PRQ) on the basis of the logic request (LRQ). The physical request (PRQ) defines memory (MEM) addresses (A) relating to the group of data (GRP). A memory interface (INT) effects a transfer (TRNSFR) of the group of data (GRP) between the memory (MEM) and the processor (P) on the basis of the physical request (PRQ). Thus, the processor need not know how and where the data to be processed or having been processed are stored in the memory. This facilitates the design of a data processing device and, particularly, a family of such devices.

Abstract: A method and apparatus for altering code to effectively hide main memory latency using software prefetching with non-faulting loads prefetches data from main memory into local cache memory at some point prior to the time when the data is requested by the CPU during code execution. The CPU then retrieves its requested data from local cache instead of directly seeing the memory latency. The non-faulting loads allow for safety and more flexibility in executing the prefetch operation earlier because they alleviate the concern of incurring a segmentation fault, particularly when dealing with linked data structures. Accordingly, the memory access latency that the CPU sees is essentially the cache memory access latency. Since this latency is much less than the memory latency resulting from a cache miss, the overall system performance is improved.

Abstract: Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.

Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal.

Abstract: A multiprocessor includes M banks storing a plurality of instructions; and N processors each having N instruction fetch stages, wherein each of the N processors processes one of the plurality of instructions in a pipelined manner, where N is an integer equal to or greater than 2, and M is an integer equal to or greater than N, wherein each of the N processors fetches one of the plurality of instructions at a different instruction fetch stage from instruction fetch stages used by other processors.

Abstract: A SIMD processor includes plural processor elements (PEs) each having a processing unit for data processing, a register for holding data to be processed or already processed by the processing unit, a data transfer bus interconnecting with other PEs, and a register controller for inputting a read or write signal to the register. Read and write processing steps in the processor are carried out by the register controller in response to the signals which are sent form the register controller and inputted into a register of specific processor elements responding to an addressing signal from an external interface. The processor is capable of transferring data directly to a specific processor element, thereby achieving higher speeds of data transfer and resultant data processing and makes flexible use of registers to thereby attain efficient data processing utilizing arbitrary combinations of the register depending on bit width of the data.

Abstract: A method for growing a secondary trace out of a cache of translations for a program during the program's execution in a dynamic translator, comprising the steps of: maintaining execution counts for translation heads that are executed from a code cache; when an execution count for one of said translation heads exceeds a threshold, designated as a hot translation head, beginning a mode of operation in which, as following code translations are executed from the code cache after the execution of the hot translation head, storing in a history buffer information identifying each of the following code translations in sequence; terminating the storing of information in the history buffer in relation to the hot translation head when a termination condition is met; and linking together the translation head and the sequence of following code translations identified in the history buffer to form a larger code translation.

Abstract: A microprocessor and associated method includes a plurality of resources for executing instructions, and an out-of-order instruction shelf for priority/age tracking of the instructions. The instruction shelf has an instruction pool with a plurality of slots therein for storing respective instructions, and an instruction age tracker for storing therein a matrix of rows and columns of logic states associated with relative ages of instructions. The logic states in a given column and row of the matrix are associated with a respective slot of the instruction pool. Also, the microprocessor includes an instructions scheduler for performing at least one logic function on each column of the matrix to determine an oldest instruction, for dispatching instructions to the plurality of resources based thereon, and for updating the matrix based upon dispatched instructions.

Abstract: A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the instructions are then unloaded from the replay queue for replay or re-execution. For a multi-threaded processor, a stall is detected in one of the threads. Instructions of the stalled thread are temporarily stored in a replay queue, except the oldest instruction of the stalled thread which is allowed to replay or re-execute. This allows other threads to have access to execution and replay resources. Eventually, the oldest instruction will execute and retire, which breaks or releases the stalled thread. The instructions stored in the replay queue are then unloaded from the replay queue.

Abstract: A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The second tag may equal the first tag if the branch delay slot is unconditional for that branch, and may equal a different tag if the branch delay slot is conditional for the branch. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages. If the tag in a pipeline stage matches the first tag, the instruction is not cancelled. If the tag mismatches, the instruction is cancelled.

Abstract: Network-based methods and systems are disclosed for configuring and building systems and providing systems integration for the test, automation and measurement environment. The methods include internet or intranet-based applications that configure and quote a system or system integration project in response to selection of system features, system components and/or system configurations by a network user. The methods may be implemented as part of a build-to-order internet application.

Abstract: A BIOS having a set of effectors to initialize harware within the system. The BIOS having a set of macros, each macro of the set of macros having a reference to an effector of the set of effectors, each macro of the set of macros having a set of arguments.

Abstract: A data processing system with bootcode support for communicating with a noncompliant external device has a motherboard, non-volatile memory connected to the motherboard, a volatile memory, processing resources, a communications port that utilizes a first communications protocol, and one or more buses interconnecting those components. Startup instructions obtained from the non-volatile memory load a device driver for the external device from the non-volatile memory into the volatile memory. However, unlike the communications port, the external device utilizes a second communications protocol. Diagnostic instructions then utilize the device driver to communicate with the external device via the communications port.

Abstract: A method for altering the start-up sequence of an operating system prior to loading the operating system is disclosed. The method allows changes to be made to the start-up sequence of processes and applications initiated by the operating system based upon the occurrence of a designated event during the BIOS boot sequence. In this manner, events occurring prior to operating system loading affect the operating system start-up sequence. Similarly, the illustrative embodiment of the present invention may, during the period of time the operating system is operating, write instructions which control the sequence of events taking place during the subsequent BIOS boot sequence.

Abstract: A method and apparatus for distributed group key management for multicast security. According to one aspect of the invention, a common multicast group includes a number of key servers, as well as clients of those key servers that are currently members. In addition, there exists a server group key that is shared by the key servers and not by their clients to form a server multicast group within the common multicast group. A first of the key servers encrypts a message using the server group key. The message instructs the key servers regarding one or more keys used for encrypted communication between entities in the common multicast group. The encrypted message is then multicast to the rest of the key servers.