Abstract: A system and method for securely transmitting, searching, and storing data. To ensure security on the client side of a communication network, the system and method double encrypt sensitive data and single encrypt non-sensitive data. The system and method also fuzzy searches for user information. Thus, it is possible to find the information for the user in a database knowing only a minimal amount of detail about that user. Privacy and security is provided without impeding performance or compromising any of the standard database search functionality. Capitalizing on the difference in privacy requirements between users, the number of keys required to access sensitive data is minimized by using a single key for each user (e.g., a patient) and two keys for other users (e.g., health care providers).

Abstract: Methods, systems and computer program products are provided which provide cryptographic services to an application by incorporating in the application an indication of at least one authorized cryptographic function for the application. The indication of at least one authorized cryptographic function for the application is communicated to a cryptographic library that supports a plurality of cryptographic functions. The at least one authorized cryptographic function corresponding to the indication of at least one authorized cryptographic function is then identified as a valid cryptographic function for the application.

Abstract: Disclosed is an arrangement for secure and controlled electronic distribution of documents from a server (102) to clients (101) across an electronic network (100), e.g., the Internet. A client requests (200) authentication from the server. The server validates (202) the request and sends (206) a validation and encryption data (129) to the client to establish a secure communications connection with the client. The client returns (210) a request for a document accompanied by the client ID (131) to the server. The server validates (212) the request and uses the client ID to set (216) permissions of the client for the document. The server then uses the encryption data to encrypt (220) the document and its permissions, and sends (224) the encrypted information to the client. The client acknowledges (230) receipt of the document, decrypts (228) it by using the encryption data, and enforces (232) the permissions on the document.

Abstract: A key establishment protocol between a pair of correspondents includes the generation by each correspondent of respective signatures. The signatures are derived from information that is private to the correspondent and information that is public. After exchange of signatures, the integrity of exchange messages can be verified by extracting the public information contained in the signature and comparing it with information used to generate the signature. A common session key may then be generated from the pubilc and private information of respective ones of the correspondents.

Abstract: Supplementary information related to original data is embedded in the original data without being lost or altered and without degrading the quality of the original data. A photographing condition or the like regarding photographing of the original image data is generated as the supplementary information by supplementary information generating means and stored in a database on a network by supplementary information storing means. Storage management information such as a URL address of where the supplementary information is stored is generated by storage management information generating means and embedded by embedding means in the original image data by using deep layer encryption. The original image data in which the storage management information has been embedded are recorded in a recording medium.

Abstract: Systems and methods are provided for protecting and managing electronic data signals that are registered in accordance with a predefined encoding scheme, while allowing access to unregistered data signals. In one embodiment a relatively hard-to-remove, easy-to-detect, strong watermark is inserted in a data signal. The data signal is divided into a sequence of blocks, and a digital signature for each block is embedded in the signal via a watermark. The data signal is then stored and distributed on, e.g., a compact disc, a DVD, or the like. When a user attempts to access or use a portion of the data signal, the signal is checked for the presence of a watermark containing the digital signature for the desired portion of the signal. If the watermark is found, the digital signature is extracted and used to verify the authenticity of the desired portion of the signal. If the signature-containing watermark is not found, the signal is checked for the presence of the strong watermark.

Abstract: Methods and systems for secured configuration data for a programmable device. One or more memory devices store configuration data that includes one or more configuration bitstreams and associated authentication tags for each configuration bitstream. Each authentication tag is created using the associated configuration bitstream. A programmable device operably connected to the one or more memory devices receives one of the configuration bitstreams. The programmable device uses the associated authentication tag of the configuration bitstream to verify that the configuration bitstream is authentic. The programmable device loads the configuration bitstream if the one of the configuration bitstream is authentic, or may discard it otherwise.

Abstract: A reprogrammable subscriber terminal of a subscription television service which can have the control program code of its control processor modified by downloading new program code from the headend. The control processor stores a boot program in an internal read only memory. Upon start up and resets, the boot program determines whether the control program should be changed from a command sent from the headend. The command, termed a parameters transactions, includes the number of expected download program code transactions required to complete the control code modification, the memory space areas where the code is to be loaded, and the channel over which the download program code transactions are to be transmitted. The channel is tuned and when the boot program receives all the download program code transactions accurately and stores them, the boot program will cause the control program to be restarted at a selected address of the new or modified control program code which has been downloaded.

Abstract: Apparati, computer-implemented methods, and computer-readable media for thwarting map-loaded module (8) attacks on a digital computer (1). Within the computer (1) is an intermediate location such as a registry (10) containing mappings from generic names (4) of map-loaded modules (8) to specific locations (5) of the map-loaded modules (8). Coupled to the intermediate location (10) is a monitor module (20) adapted to monitor attempts to replace existing mappings (5) of map-loaded modules (8) with replacement mappings (5). Coupled to the map-loaded modules (8) is a file system monitor;module (70) adapted to monitor attempts to insert new map-loaded modules (8) into the computer (1). Coupled to the monitor module (20) and to the file system monitor module (70) is a programmable control module (30) adapted to determine when a change in mapping constitutes a malicious code attack.

Abstract: Each subnet has an environment for executing the agent service program. When a request for service such as file system is made from the subnet B103 to the subnet A102 by a user, a client side agent created at the subnet B103 further creates a peer agent, and the peer agent is transmitted to the subnet A102 according to the communication condition such as a firewall 104 which is already being notified. A peer-to-peer session is configured between the agents.

Abstract: A system, method and computer program product are provided for updating security software on a client. Initially, a parameter indicating a difference between a security update file and a previous security update file is identified. Next, a security program is conditionally updated with the security update file based on the parameter.

Abstract: An intrusion detection system and method for detecting unauthorized or malicious use of network resources includes an intrusion detection analysis engine that instanciates one or more analysis objects to detect signatures associated with attacks on network vulnerabilities. As new network vulnerabilities are identified, new analysis objects can be dynamically interfaced on a runtime basis with the intrusion detection analysis engine to detect signatures associated with the new network vulnerabilities. A signature application programming interface supports communication between the intrusion detection analysis engine and the analysis objects. When the instance of an analysis object indicates that an associated signature exists in network data, the intrusion detection analysis engine can provide an alarm.

Abstract: Initially, profiles are customized by naming an assignment to individual users and identifiable groups of users. A profile is further assigned action groups that comprise one or more system actions. System actions provide the functionality needed for toolbar buttons and menu items. Using the system actions associated with the action groups, toolbar buttons and menus can then be configured for the profile. The profile determines the level of functionality downloaded with the application. When a request is received for an application, the user's profile is accessed for the action groups and system actions that provide functionality for the application. Only system actions associated with a profile to which the user is assigned are transferred to the requesting user. Alternatively, the user's group profile may be accessed for the action groups and system actions that provide functionality for the application.

Abstract: A method and apparatus for allowing a mobile station in a wireless network to perform network authentication in association with mobile packet data services. The packet data serving node (PDSN) does not authenticate the mobile station with an authentication server prior to sending a CHAP success message. Rather, a mobile station is authenticated via an authentication server after the PDSN receives an IPCP message indicating whether the mobile station desires to use Mobile IP in the current session. If the mobile station desires to use Mobile IP, the PDSN uses authentication techniques in accordance with Mobile IP protocols. In the preferred embodiment, if the mobile station does not desire to use Mobile IP, the PDSN authenticates the mobile station querying an authentication server with the buffered contents of a previously received CHAP challenge response.

Abstract: The system of the present invention generally allows a first user, the adult, to interact in the manner of a character facade with a second user, the child, via computer connections to a webserver. The webserver generally includes a processor with a memory/storage device that holds a character interaction program which supports a registration website and a character website. The processor operates with the program to receive a message from the child user, to notify the adult user of the received message via electronic mail, to receive a reply from the adult user, and to present the reply to the child user as though coming from a character rather than the adult user.

Abstract: A method for reducing unauthorized software use includes supplying a first code with the software. The first code enables the software on a computer for use by a user for an initial authorization period upon entry by the user. The user is required to contact the representative for retrieval of an additional code. The software is operable during a subsequent authorization period beyond the initial authorization period without further communication with the representative following entry of the additional code. The user provides registration information to the representative prior to retrieval of the additional code. The registration information is compared with previously provided registration information to determine if the user is authorized or unauthorized. The software is disabled following the initial authorization period if the user is unauthorized. The additional code is transferred to at least one of the software, the user, and the computer if the user is authorized.

Abstract: A method and apparatus for reducing power dissipation within a functional unit of a microprocessor includes a power sensing circuit for sensing power dissipation of the functional unit. A low power mode identifying circuit identifies when the measured power dissipation of the functional unit exceeds a predetermined amount or value. Upon such a condition, a low power mode circuit operates the functional unit in a low power mode thereby reducing its power dissipation. Operation of the functional unit in the low power mode continues until the power dissipation reaches a safe level. The functional unit internally determines power dissipation and selectively enters a low power mode to reduce power dissipation of the functional unit. Low power mode operation of the functional unit reduces power dissipation of the functional unit.

Abstract: A system and method for determining power supply requirements for a plurality of servers in an information network that includes a system management bus coupled to provide information on power being utilized by the servers during operation. The information from the system management bus is provided to program instructions that provide power usage values indicative of the power being utilized by the servers, determine the maximum value of the power usage values, and determine power supply requirements based on the maximum power usage. The power supply requirements include operating power and/or redundant power requirements. A warning signal is generated if adequate power is not available to the servers.

Abstract: A method and apparatus for a low power, multi-level GTL interface signaling FSB buffer with fast restoration of static bias are described. The buffer includes a dynamic bias circuit to clamp a pad voltage level to a termination voltage level Vtt in response to a rising signal transition at the pad. By pulling-down a node voltage from a static voltage level to a dynamic voltage level, the pad voltage level is prevented from overshooting Vtt. A static bias circuit is used to maintain the node voltage at the static voltage level. A dynamic resistance unit aids the static bias circuit in restoring the node voltage level to the static voltage level once the rising signal transition is complete. Consequently, a duration of the clamping of the pad voltage level is minimized and power for clamping the pad voltage level to Vtt is reduced.

Abstract: A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.

Abstract: A hand-held, PCMCIA cellular radio modem card is described which uses a non-standard power output level. The non-standard power output is defined as the maximum RF power attainable such that the current drawn by the power amplifier does not exceed 400 mA. This definition permits the use of the wireless modem inside hand-held computing devices without the use of an additional battery pack extension.

Abstract: A detection unit detects input-request signals or receive signals that correspond to the input-request signals that are sent and received between a specific data-processing apparatus and another apparatus. A judgment unit then determines whether the data-processing apparatus is performing a specific process, based on the status of the data-processing apparatus and detection results from the detection unit. A supply-control unit controls whether or not to supply a synchronization clock to the data-processing means according to judgment results from the judgment unit.

Abstract: An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: According to the teachings of the present invention there are provided a system and method for automatically supporting one or more registered products at a computing device, the computing device being enabled to communicate via a communication network to a support web server, the method comprising: downloading to the computing device a software agent; diagnosing malfunctions of the one or more products at the computing device and transmitting the malfunctions to said web server; communicating from the support web server to the software agent one or more solutions in response to receiving the malfunctions; and installing at least one of the one or more solutions thus transmitted at the computing device.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.

Abstract: A fault tolerant method transforms physically contiguous data in-place on a disk by partitioning the physically contiguous data into an empty region physically adjacent to data regions including a first data region and a last data region, the first and last data regions at opposing ends of the physically contiguous data regions. The physically contiguous data are transformed in an order beginning with the first data region and ending with the last data region. The transforming step perform first locking and reading the first data region, second, transforming the first data region, third, writing and unlocking the transformed first data region to the empty region, and fourth, declaring the first data region as the empty region while declaring the empty region as the first region. The first through fourth steps are repeated for each data region, until completion, to transform the physically contiguous data in-place on the disk.

Abstract: A fault tolerant memory system and method of operation thereof. The fault tolerant memory system includes a number of memory arrays including at least one spare memory array, wherein each of the memory arrays has an internal error detection circuit. In an advantageous embodiment, the internal error detection circuit includes an inverter, a register coupled to the inverter and a comparator for comparing the contents of the inverter and register. The comparator will generate an error signal to indicate a failed memory array in response to the contents of the inverter and register not being equal. The fault tolerant memory system also includes data correction logic that corrects data stored in a failed memory array and, in an advantageous embodiment, restores “corrupted” data in a failed array by reading the content of a row of cells in the failed memory array and generating a first complement of the content.

Abstract: A system and method are provided for recovering from the failure of a mirrored boot device (e.g., disk drive). One method is implemented for a computer system that mirrors two (or more) boot devices. If one of the devices fails, a set of compensating activities is performed, which may include removing the failed device from the list of devices from which the system may boot, deleting mirror state data from the device and removing the failed device from the mirroring scheme. After the failed device is repaired or replaced, a set of reintegrating activities is performed, which may include including the device in the mirroring scheme, restoring mirror state data to the device and adding the device to the list of boot devices. Even if the system includes only two mirrored boot devices and one of them fails, it can continue operation and can reboot successfully without using stale data.

Abstract: A method of verifying that defect management area (DMA) information is normally generated or updated upon reinitialization with certification in a disc recording and reproducing apparatus, and a test apparatus for performing the method. The method includes performing reinitialization with certification in a recording and reproducing apparatus using test reference information and a test disc with physical defects, generating test information from the defect management information which is generated after the reinitialization, comparing reference information expected from the test reference information and physical defects with the test information, and providing the result of verification of the test information. Accordingly, it can be easily understood whether the DMA generation or updating function is normally performed in the disc recording and reproducing apparatus in a mode of reinitialization with certification.

Abstract: A system for implementing a high-availability architecture comprising a first compact Peripheral Component Interconnect shelf, a second compact Peripheral Component Interconnect shelf, and a network. The first and second compact peripheral component interconnect shelf are redundant systems. The first compact peripheral component interconnect shelf comprises a first system utility card connected to a first compact core to network interface connected to a first compute platform connected to a first high speed pipe interface. The second compact peripheral component interconnect shelf comprises a second system utility card connected to a second compact core to network interface connected to a second compute platform connected to a second high speed pipe interface. The first and second compact peripheral component interconnect shelf are connected via Ethernet. The first and second compact core to network interface is connected to the network.

Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A system and technique restarts a data plane of an intermediate node, such as an aggregation router, of a computer network without changing the state of a control plane in the router. The aggregation router comprises a control plane that includes a supervisor processor configured to manage traffic forwarding operations of the node. To that end, the supervisor processor maintains a current state of the control plane pertaining to, e.g., routing protocols and interface states of line cards within the router. The aggregation router further comprises a data plane that includes hardware components, such as a forwarding engine, configured to perform forwarding operations for data forwarded by the router.

Abstract: A computer system factory download automated test process architecture includes an automated test system server (ATS Server), an automated test control center (ATCC) software program operable within the ATS Server for performing prescribed functions of a factory download automated test process, and an automated test machine (ATM) having a processor, a bootable device, and automated test machine client software, the bootable device for storing the ATM client software, and the processor for executing the ATM client software, in response to a prescribed boot, for controlling an operation of a prescribed download/test process of a respective ATM during the factory download automated test process, and for a respective ATM, the ATM client software for 1) retrieving installation files and test instructions from the ATCC, 2) passing control to the respective ATM upon a receipt of the installation files and test instructions for the ATM to perform at least one automated test according to the installation files and tes

Abstract: A system for testing an application running on a point-of-sale (POS) terminal comprises a host running on a personal computer connected to the POS terminal, and a target running on the POS terminal. The host sends simulated keystrokes, card swipes and the like to the target, which passes these to the application under test. The target can send information to the host regarding the POS terminal status, such as the screen display, so that the host can send the simulated keystrokes, etc., to the target on a need basis. The host can also receive other data and send instructions to the target, e.g. it can obtain available RAM space details, file details and system clock details, and can send instructions to restart the application.

Abstract: A system and method is provided for detecting defects in an embedded architecture or micro-processor based system. A look-up table, located with in a programmable logic device, is accessed to obtain a value for a particular byte of a predetermined data pattern. The predetermined data pattern is associated with data from a bus coupled to the programmable logic device. The accessed value of the predetermined data pattern is compared to data that is received by the programmable logic device from a memory coupled to the programmable logic device via the bus. An alarm mechanism, to indicate an improper data comparison, is triggered based upon the comparison of the predetermined data pattern and the data received from the memory.

Abstract: Aspects for soft error detection for a superscalar microprocessor are described. The aspects include a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data, and a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data. A detection system utilizes one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.

Abstract: A method for categorizing information regarding a failure in an application program module. The failure may be a crash, a set-up failure or an assert. For a crash, a name of an executable module where the crash occurred in the application program module, a version number of the executable module, a name of a module containing an instruction causing the crash, a version number of the module and an offset into the module with the crashing instruction are determined. This bucket information is then transmitted to a repository for storage in a database. The database may be examined to determine fixes for the bug that caused the crash.

Abstract: A test system includes a switch emulator, a network test device, and an interface converter. The switch emulator is configured for transmitting first network data on a first media independent interface based on a first interface clock, and the network test device configured for transmitting second network data on a second media independent interface based on a second interface clock. The interface converter, having inverted media independent interfaces, is configured for transferring the first and second network data between the first and second media independent interfaces, and supplying the first and second interface clocks based on an external clock generated by the switch emulator. Hence, network data can be passed between the switch emulator and the network test device according to network protocols, even if the switch emulator is operating at relatively slow speeds.

Abstract: The invention relates to a software system and method for configuring a software system for interaction with a hardware system. In this method, the software system (140) is executed on a host processor interconnected with the hardware system (103). A database (152) is accessed to obtain a description of a set of functional components present within the hardware system (103). A software representation (154) of the capabilities of each functional component is created by using the description of the set of functional components. Then, the software representation (154) is interrogated to determine a set of operational capabilities of the hardware system (103). The software system (140) is then operated in a manner that is responsive to the set of operational capabilities of the hardware system (103).

Abstract: Architecture and corresponding methods share resources and synchronize counters in high-speed network integrated circuits. The architecture has at least one counter group comprising several registers, each with two ports. One port receives networking events (e.g., receipt of an-error packet, transmission of a good packet, etc.) via a tri-state bus. The registers in each counter group use a shared hardware memory element, which adds the events for each counter group. The second port is available for asynchronous external read accesses via a second tri-state bus. The architecture synchronizes read requests with events such that read accesses occur during gaps in events. The registers are assigned to several mutually exclusive counter groups such that no two registers in the counter group increment in a basic clock cycle.

Abstract: A memory device redundant repair analysis method, recording medium and apparatus allowing a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules. It is possible to provide a memory device redundant repair analysis method, recording medium and apparatus that allow a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules by carrying out processing of finally merging a plurality of repair codes corresponding to respective rules obtained by applying a plurality of redundant repair analysis rules into one code.

Abstract: An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: A system and method facilitates simplified debugging of internal component scan testing. In an example embodiment, a TAP controlled internal scan test intermediate debugging system includes an intermediate TAP controller internal scan test system, design circuit blocks, a scan test chain primary input pin, a scan test chain final output pin. The components of the intermediate TAP controlled internal scan test debugging system cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals. The intermediate TAP controller internal scan test system transmits an indicated intermediate scan test chain signal off of the IC as a TAP test data out (TDO) signal. The intermediate TAP controller internal scan test system utilizes an internal scan observe register to store information indicating which intermediate internal scan test chain signal to forward as a TAP TDO signal.

Abstract: A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode.

Abstract: An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means.

Abstract: A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro (1) for receiving signals whose logic levels are fixed to “H” or “L” on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.

Abstract: A timing adjusting circuit is mounted on a semiconductor device. A reference signal TREFIN and signals TPa to TPx to be adjusted are supplied from a tester via transmission lines on a test jig. By gradually advancing phases of the signals TPa to TPx with respect to a trigger signal TRIG generated on the basis of the reference signal, the differences of transition timings of driver waveforms are held in a plurality of registers corresponding to the transmission lines. The data held by the plurality of registers is sent to the tester via a storage result outputting circuit. On the basis of the data, output timings of the driver waveforms can be adjusted by the tester with high accuracy.

Abstract: An interleaver structure for turbo codes with variable block size. The interleaver permutes symbols through multiplication by a parameter followed by modulus by the block size. A table of the multiplication parameter as a function of the block size permits adaptability to a wide range of block sizes without significant memory consumption.