Abstract: In input and output enabling power estimating apparatus and method for a secondary cell, an input enabling power (Pin) of the secondary cell is estimated on the basis of parameter estimated values (&thgr;) and an open-circuit voltage (Vo), and an output enabling power (Pout) of the secondary cell is estimated on the basis of the parameter estimated values and the open-circuit voltage (Vo), the parameters are integrally estimated from at least one of equations (1) and (2): 1 V = B ⁡ ( s ) A ⁡ ( s ) ⁢ • ⁢   ⁢ I + 1 C ⁡ ( s ) ⁢ • ⁢   ⁢ Vo , ⁢ wherein ⁢ ⁢ A ⁡ ( s ) = ∑ k = 0 n ⁢ a k ⁢ • ⁢   ⁢ s k , B ⁡ ( s ) = ∑ k = 0 n ⁢ b k ⁢ • ⁢   ⁢ s k , C ⁡ ( s ) = ∑ k = 0 n ⁢ c k ⁢ • ⁢   ⁢ s k , ( 1 )

Abstract: A rechargeable power supply (10) comprises at least one a rechargeable cell (12) connectable to a power source (14), a Zener diode (20) connected to the at least one cell (12), and a bipolar transistor or FET (22) for selectively disconnecting the Zener diode (20) from the cell (12) thereby to reduce any discharge of the cell (12) through the voltage protection means (20). The Zener diode (20) and the transistor (22) are connected together in series and jointly connected across the cell in parallel.

Abstract: An induction generator power supply comprises a prime mover, an induction generator operably connected to the prime mover and having a generator output, and a phase shift circuit, having a circuit input and a circuit output, the circuit input connected to the generator output. The power supply also comprises an AC to DC converter, having a converter input and a converter output, the converter input connected to the circuit output, and an energy reservoir having a reservoir input connected to the converter output.

Abstract: A switching regulator target voltage is adjusted to a first value corresponding to a pre-charge voltage that is present at a regulator output terminal. The switching regulator responds to a comparison signal resulting from a comparison of the target voltage and a feedback voltage. When the switching regulator is on, the target voltage is adjusted to a second value corresponding to a nominal regulator output voltage. In one embodiment, a synchronous switch is disabled when a lockout circuit receives a disable signal. The lockout circuit is unlocked when an enable signal is provided by a switching controller.

Abstract: An active current sharing circuit is disclosed that provides a plurality of paralleled buck converters each having a lossless inductor-based current sensing circuit for sensing the average current of the associated buck converter through its output inductor, and a means for adjusting the voltage reference coupled to each of the buck converter's PWM controllers through a one pin interconnection between the converters. The disclosed invention has the advantage of providing a high percentage current sharing level at lower cost, with reduced circuit wiring complexity and fewer components. In an alternate embodiment, the inductor-based current sensing is replaced with a resistor-based current sensing, such that comparable current sharing levels are achieved albeit with higher loss.

Abstract: A kilowatt-hour counter (10) is provided that accepts the male plug of a standard US household appliance and that is plugged into a standard US household electrical socket. An extremely low ohm resistor is used to create a voltage proportional to the electrical energy used. This voltage is used by an Analog Devices Energy Monitoring Integrated Chip, along with a Microchip Corporation microprocessor, to produce and display a kilowatt-hour count. Two alternate embodiments are presented. In the first, the kilowatt-hour counter is mounted behind a standard 2-female outlet (20). In the second, the kilowatt-hour counter is mounted behind a standard 1-switch wall switch (30).

Abstract: In a preferred embodiment, a sensor (10) for measuring magnitude and polarity of static charge on particles in a liquid, including: an electrically nonconductive conduit (26) through which the particles and the liquid can flow; a magnet (20) having first and second legs (22,24) with a gap therebetween, the gap being disposed in the conduit; and three electrodes (40, 42, 44) insulatedly disposed in the first leg and having distal ends protruding into the gap. A method of measuring magnitude and polarity of static charge on particles in a liquid is also provided.

Abstract: A method for evaluating measuring signals of an electromagnetic field is disclosed which is in interaction with an electrically conductive fluid for detecting components in the fluid which differ from the electric conductivity of the fluid, with the measuring signals being divided into at least two channels and being evaluated in order to detect different distributions and concentrations in the fluid.

Abstract: To provide an angle sensor which can equalize the magnetic flux distribution while using inexpensive magnets manufactured easily and which can reduce the detection error even if the relative position between the magnetoelectric conversion element and the magnet changes. The permanent magnets M1a, M1b, M2a, M2b each of which is rectangular solid are fixed to the yoke 13 of the rotational angle displacement sensor 11. The permanent magnets M1a, M1b are separated from each other with a clearance L. The permanent magnets M1a, M1b are magnetized in such a manner that the side fixed to the flat wall portion 15a of the yoke 13 is N pole and that the side opposing to the fixed surface side is S pole. Further, the permanent magnets M2a, M2b are separated from each other with a clearance L. The permanent magnets M2a, M2b are magnetized in such a manner that the side fixed to the flat wall portion 15b of the yoke 13 is S pole and that the side opposing to the fixed surface side is N pole.

Abstract: A ground reaction force measuring module for a walking robot includes a housing installed at a predetermined portion of the walking robot facing the ground, a moving unit installed capable of moving with respect to the housing according to the presence of a pressing force to the ground transferred from the ground to the walking robot, and a compression sensor installed in the housing to measure a reaction force of the ground from the presence of the pressing force transferred through the moving unit. Thus, a change in the ground reaction force in a wide range can be stably coped with and the installation position of the robot foot can be easily changed.

Abstract: A Position Sensor comprises: one or more excitation windings; a signal generator adapted to apply excitation signals to the or each excitation winding; tag means displaceable relative to said excitation windings; one or more sensor windings electromagnetically coupled to said excitation windings such that in response to said excitation signals being applied to said excitation windings, there is generated sensed signal in the or each sensor winding; and a signal processor adapted to process said sensed signals to determine the position of said tag means in any location in the X, Y and Z planes essentially in accordance with phase values or in accordance with phase values and amplitude values.

Abstract: A transducer (10) for distance measurement, especially between a stator and a rotor in a refiner for paper pulp production, in which the transducer is of the magnetic type and has a tubular casing (17), the one end of which forms a measuring head (14), in which a measuring pole (15) is fitted in a holder (16) which is mounted in the end of the casing (17) and seals this. The holder (16), with a first portion (22) of its axial length, reaches beyond the end of the casing. This first portion (22) and the measuring pole (15) are intended to be able to be worn away to a smaller axial length during use of the transducer, whilst the length of the casing is maintained.

Abstract: The invention concerns a device for detecting the displacement of an object comprising a ferromagnetic material. Said device comprises a magnetic circuit generator provided with first and a second cores made of ferromagnetic material and an excitation coil and a measurement coil. The magnetic circuit generator is connected to a detecting unit designed to detect a reluctance variation brought about in the circuit by the displacement of the object and to deduce therefrom its position. In said device the magnetic circuit generator comprises first and second transformers with open magnetic circuit, said transformers being juxtaposed and comprise each an axis extending across their respective core, said axes extending substantially perpendicular to said path. The excitation coil comprises two coils connected in series which form the primary windings of the first and second transformers.

Abstract: In a magnetically passive position sensor, a mechanical axis (11) and a magnetic axis (12) of a magnet (2) point toward the same contact spring element from two or more contact spring elements (5, 6). This results, in particular, in the end regions of the position sensor achieving a particularly high accuracy. The magnet (2) has a guide polygon (8) which is used to hold the magnet (2) in a holder (10) such that it cannot rotate.

Abstract: A method and apparatus to screen individuals specifically for paramagnetic or ferromagnetic objects they may be carrying or wearing, before they enter a controlled area. The device comprises a screening portal, including at least one magnetic gradiometer and its electronics. The device places all of the sensor arrays in close proximity to a subject's body, for screening purposes. The portal has at least one excitation coil oriented to cause the excitation field to have zero mutual inductance with the gradiometers.

Abstract: An eddy current inspection apparatus includes a holder for a specimen, a holder for an eddy current probe, and an eddy current instrument operatively joined thereto. The probe holder includes carriages for translating the probe along first and second axes. The probe holder is selectively moved to align the probe with an internal channel of the specimen for sliding movement therealong to conduct eddy current inspection thereof.

Abstract: A method is disclosed for interpretation of multi-dimensional nuclear magnetic resonance data taken on a sample of an earth formation. Specifically, a set of NMR data is acquired for a fluid sample located either in a borehole or in a laboratory environment. From the set of NMR data, a multi-dimensional distribution is calculated using a mathematical inversion that is independent of prior knowledge of fluid sample properties. The multi-dimensional distribution is graphically displayed on a multi-dimensional map. Each fluid instance or artifact visible on the graph is identified as representing a probable existence of a detected fluid. One or more quantitative formation evaluation answers for one or more fluid instances is computed based on the multi-dimensional distribution associated with the respective fluid instance.

Abstract: The invention consists of three image-postprocessing phases for the purposes of generating high-quality quantitative MR images (proton density (PD), T1, and T2) as well as high-quality virtual MR images with continuously adjustable computer-synthesized contrast weightings, from source images acquired directly with an MRI scanner. Each of the image-postprocessing phases uses one or several new computer algorithms that improve image quality with respect to prior art, including linear-combination-of source-images (LCSI) algorithms for generating PD images and model-conforming algorithms for generating Q-MR images of tissue properties that influence NMR relaxation.

Abstract: At least one quantity which is characteristic of the temperature-dependent magnetic properties of magnetizable material which interacts with the magnetic fields of a magnetic resonance imaging device is determined in order to compensate the temporally varying strength of the main magnetic field of a main magnet of such a device. On the basis of this quantity a compensation signal is formed for the correction of the influence of the varying field strength on the imaging result.

Abstract: A local coil for magnetic resonance applications has an annular base body in which a reception antenna is embedded to receive a magnetic resonance signal. The base body is fashioned with inherent stability, such that it assumes an inherent form when not subjected to deformation forces. It is dimensioned such that it substantially assumes its inherent form given arrangement in a palate and/or in a nasal cavity of a person. Furthermore, it is flexibly fashioned, such that is can be inserted via a nostril of a person into the nasal cavity and removed again from it.

Abstract: A cryostat is formed into a donut form, where a cylindrical or a square concave is formed in the center of the cryostat of the superconductive magnet apparatus for an open type MRI apparatus, and the cryo-compressor is disposed in the concave.

Abstract: The present invention provides a device for in-situ measurement and recording of various environmental parameters in a semiconductor fabrication process. The device comprises sensors for detecting the parameters and converting them to sensor outputs; and a data logger coupled to the sensors for receiving the sensor outputs and logging them in a file. The device may also comprise an analog to digital converter to convert the sensor outputs to digital data and a communication module to communicate the digital data with other devices. When applied to reticles used in a semiconductor fabrication process comprising a plurality of stages, the device may be used to monitor electrostatic field and electrostatic discharge activities on and around the reticle, convert the monitored parameters into data, and log the data along with a timestamp and an identification of each individual stage.

Abstract: An electrical continuity tester has a handheld housing having batteries, switch, test bulb, a probe and a power cord having a grounded plug on the end of the power cord. The handheld tester is used to first check that a common grounded outlet is wired properly by closing the switch and observing the test bulb. The test bulb should come on if the grounded outlet is wired properly. After the outlet has been verified, the probe can be used to touch any metal or conductive parts of any electrical device or appliance to verify that the metal part is properly grounded or wired to the hot side of the circuit. The tester's the cord and plug provides one connection and the probe provides the other connection.

Abstract: The present invention relates to a method for calculating the distance to fault in a section of a power transmission network, which section is arranged with line terminals at both ends, each terminal comprising impedance relays (AA, BB), comprising the steps of, at the occurrence of a fault: measuring the apparent impedances by each relay, measuring the relaying currents, determining the type of fault, checking whether the fault involves a fault resistance or not, and, if so, solving a quadratic equation for complex numbers, resolving the quadratic equation for the real and imaginary components, obtaining two quadratic equations for a fault distance in which the coefficients are real numbers, combining the two equations and obtaining a distance to fault, or, if not so, solving a quadratic equation for real numbers, obtaining two solutions for the distance to fault d1, d2 and comparing the solutions as O<(d1 or d2)<1 pu, where pu is the length of transmission lines between the line terminals.

Abstract: Wafer-level testing is performed on an electronic device to be used in an optical communications system. An optical test signal is generated and is provided to a first photo detector. An electrical output of the first photo detector is supplied to the electronic device on the wafer. An electrical output from the electronic device on the wafer is used to drive a light source. An optical output of the light source is supplied to a second photo detector and an electrical signal output from the second photo detector is examined.

Abstract: A method for testing a test component connected to a high-speed electrical component includes connecting a golden optical component to a high-frequency probe, connecting the high-frequency probe to the high-speed electrical component, operating the test component in an application environment to cause a transmission of a high-speed electrical signal from the high-speed electrical component to the golden optical component, and determining if the golden optical component responds to the high-speed electrical signal.

Abstract: A high density probe card contact apparatus including a support block fitted into an opening in a probe card, and holding a plurality of fine tipped needles extending inward and below an opening in the center of the block. The needle tips are a noble metal integrally connected with a less costly conductive metal which forms the more widely spaced fingers of the needles, and which terminate in contacts to the probe card. Laser etching defines the fine needle pattern in a thin sheet of the two-metal composition which is secured to a polymeric film. The contact apparatus is assembled by positioning one or more sections of the polymer with needles on the support film.

Abstract: The present invention provides a new electronic circuit board and a method of using such board to test electronic devices at elevated temperatures. The board comprises a steel base having a dielectric coating layer and a circuit formed on the layer. The circuit includes a connector region for attachment to an external electrical source and a mounting region for mounting sockets for supporting, powering and monitoring the electronic devices during elevated temperature testing. The board displays a leakage current of less than 10 &mgr;Amps at 350° C.

Abstract: The speed of on-chip ADC testing of image sensors is increased by testing multiple chips in parallel. A wafer typically contains many individual image sensor chips. In a parallel on-chip test procedure, power is applied to a plurality of the image sensor chips and the chips are then tested in parallel. Additional power lines may need to be added to the wafer to allow power to be supplied to a plurality of the image sensor chips at once. These power lines may be etched directly on the wafer, or a wafer master may be used to overlay the wafer with the power lines for testing purposes. Additionally, test engines may be added to the wafer map to control the overall test procedures.

Abstract: In a dynamic burn-in apparatus wherein a signal output from a signal generator is input to a semiconductor device to be tested in the burn-in tank, a converter is arranged at the output of the signal generator. The converter increases, by N times, the frequency of the signal output from a signal generator. The signal having the increased frequency and output from the converter, is input to the semiconductor device to be tested in the burn-in tank when the burn-in is operated at high-speed. The frequency of the signal is converted to the higher frequency, and the signal having the higher frequency is provided to the semiconductor device. As the result, the burn-in can be done in a shorter time for a high-speed sophisticated semiconductor device.

Abstract: A termination circuit for a differential transmission line. The termination circuit comprises a plurality of resistive sub circuits. Each of the resistive sub circuits comprises a PFET and an NFET in parallel. A first resistor is connected at one end to a drain of the NFET and a source of the PFET, and connected at an opposite end to one line of the differential transmission line. A second resistor is connected at one end to a source of the NFET and a drain of the PFET, and connected an opposite end to another line of the differential transmission line. Optionally, there is another resistor connected between the differential transmission line, whereby the termination resistance is based on this other resistance in parallel with one or more of the resistive sub circuits which are enabled. Means are provided to selectively enable one or more of the resistive sub circuits to yield a desired resistance to terminate the differential transmission line.

Abstract: A current driver circuit has a current driver and a current compensation circuit. The current driver has a current source transistor connected to a power source potential level, while it is coupled to a pair of transmission lines. The current compensation circuit is coupled to the output side of the current source transistor for the compensation of an output current from the current driver in response to a common mode potential of the pair of transmission lines.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.

Abstract: A pulse detector has a leading edge detector and a trailing edge detector. A timing circuit is provided for determining the pulse duration between the leading edge and the trailing edge of a signal pulse; and a divider divides the pulse duration to produce a first timing pulse representative of a mid-point or peak of the signal pulse. An inventer may also be provided to produce a second timing pulse representative of troughs between signal pulses. A combiner may optionally be provided for combining the first and second timing pulses. The detector has application in signal cleaning circuits.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: A base bias circuit generates a bias voltage for a bipolar transistor. The base bias circuit includes a current mirror circuit which tracks current through a current source which drives emitter current through the bipolar transistor. A primary biasing bipolar transistor and a secondary bipolar transistor have a &bgr; which tracks the &bgr; of the bipolar transistor. The primary biasing bipolar transistor receives current from the current source through a current mirror circuit to develop the bias voltage. A bias resistor coupled between the bias voltage and the base of the primary biasing bipolar transistor tracks resistance variations in the base resistor. The secondary biasing transistor tracks changes in base current to the bipolar transistor and supplies additional current to the primary biasing transistor to compensate for changes in &bgr;.

Abstract: A clock tree synthesis (CTS) apparatus, generator, and method for synthesizing a clock tree includes a plurality of clock signal generators that output different clock signals generated from a reference clock signal. The clock signal generators includes an additional logic circuit that is not recognized as an end point of the reference clock signal when the clock tree is synthesized. In one example, the clock signal generator is a flip-flop and the additional logic circuit is a tri-state buffer.

Abstract: Provided is a device for controlling a frequency response by scaling an impedance. The device includes a filter and a duty ratio controller. The filter generates an output signal after removing a frequency from an input signal, and comprises a first impedance component and a switch. The switch, which is serially connected to the first impedance component, is switched on or off in response to a duty-controlled clock signal. The duty ratio controller receives a clock signal, controls a duty ratio of the clock signal, and generates the duty-controlled clock signal. The duty ratio controller comprises a flip-flop, which has a clock terminal that receives the clock signal, and a reset terminal, which receives a delayed signal obtained after delaying the clock signal by a time delay. The duty ratio controller further comprises a delay component that receives the clock signal, generates the delayed signal, and controls the time delay in response to a duty control signal.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: In integrated circuit (IC) devices, skew concerns between the clock pulses supplied to different latches hinder high speed operation. An IC device therefor includes a first clock processor means to generate a third clock pulse in response to first and second clock pulses with identical phase and frequency, a second clock processor means to generate a fifth clock pulse in response the third clock pulse and a fourth clock pulse with identical phase and frequency, and first and second latch groups each including a plurality of latches, in which the second clock pulse is generated via a buffer or divider from the third clock pulse, a fourth clock pulse is generated via a buffer or divider from the fifth clock pulse, and the third and fifth clock pulses are supplied to the first and second latch groups via a buffer, respectively.

Abstract: A variety of embodiments may include a voltage controlled oscillator to generate a differential signal on two nodes; and phase detector to compare a phase of the differential signal and a phase of a received signal, the phase detector including a sampling circuit to periodically sample voltage values on the two nodes, and a linear voltage-to-current converter responsive to the voltage values to create a control voltage for the voltage controlled oscillator.

Abstract: A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (KVCDL). Low KVCDL values leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

Abstract: DLL circuit with a small minimum delay time while allowing a wide range of adjustment of the delay time. The DLL circuit according includes a first delay circuit for delaying an input clock signal (CLK1) to output a plurality of delayed clock signals (T1 to TN), a first selector (7) for selecting a first delayed clock signal (CLK_E) and a second delayed clock signal (CLK_O) from among the plurality of delayed clock signals (T1 to TN), for output, a second delay circuit (3) for delaying the input clock signal (CLK1) to generate a slightly delayed clock signal (CLKD), a second selector (4) for selecting two selected clock signals (FDLE, FDLO) from among the slightly delayed clock signal (CLKD), first delayed clock signal (CLK_E), and second delayed clock signal (CLK_O), and a delay synthesis circuit (5) for generating an internal clock signal (CLKIN) from the selected clock signals (FDLE, FDLO), for output.

Abstract: A delay locked loop design uses a fixed capacitance to load down a signal output from a phase selector of the delay locked loop to a phase interpolator of the delay locked loop. Such loading counteracts for variable capacitive coupling that occurs in the phase interpolator as interpolation weights to the phase interpolator change. Without such loading of the output of the phase selector, the delay of the phase selector varies as a function of the capacitance coupling of the phase interpolator.

Abstract: A differential delay cell is disclosed. The delay cell includes a voltage bus and a differential pair of MOS transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output. A current source is disposed at the current node while a differential diode-connected load is disposed between the differential pair and the voltage bus. The differential diode-connected load comprises at least one n-channel MOS transistor configured as a diode.

Abstract: A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit.

Abstract: A level shift circuit whereby a voltage shift amount is large, operation speed is fast, and the power consumption is low. A p-type first transistor is connected between the power supply line and the first node, a p-type second transistor is connected between the power supply line and the second node, and an n-type third transistor is connected between the ground line and the first node, and an n-type fourth transistor is connected between the ground line and the second node. The gate of the first transistor is connected to the second node, and the gate of the second transistor is connected to the first node. An input signal is supplied to the gate of the third transistor and an inverted value of the input signal is supplied to the gate of the fourth transistor. Additionally, this level shift circuit has a plurality of control transistors. The control transistor switches the ratio of the inflow current and emission current of the first node or the second node according to the control signal.

Abstract: A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS technology and can be applied to various applications, including monolithic integration of high-voltage display driver circuits in battery-powered applications.

Abstract: A flip-flop with built-in voltage translation is used in a transmission system so as to combine core flip-flop circuitry with a input/output voltage translator. The flip-flop with built-in voltage translation dynamically latches data and translates a core power supply voltage swing at an input of the flip-flop to an input/output power supply voltage swing at an output of the flip-flop. Thus, the flip-flop, dependent on a clock input, is able to output a data signal having a translated voltage swing.