Abstract: The present invention is a method for drug level detection by using a simplified and effective deproteinizing step from body fluids, such as plasma, blood, urine, saliva, tear fluid, followed by drug extraction and measurement using an accurate technique, such as a colorimetric assay or a High-Performance Liquid Chromatography method. In a particular embodiment, the invention is directed to a method to quantify rifampicin in order to monitor its levels in body fluids and also to a Kit for rifampicin concentration measurement.

Abstract: A chemical analysis method for determining chemically related differences between subject biological material such as genetically modified plant material and control biological material such as genetically unmodified plant material, which method includes at least the following six steps. The first step is to contact the subject biological material with a fluid extractant, such as a mixture of water, isopropanol and potassium hydroxide, to produce a fluid extract of the subject biological material. The second step is to contact the control biological material with the fluid extractant to produce a fluid extract of the control biological material. The third step is to chromatograph the fluid extract of the subject biological material, for example, gas or fluid chromatography, to produce a chromatogram of the fluid extract of the subject biological material.

Abstract: A time duration of end of product life indicator is disclosed which utilizes a volatile dye coated or impregnated into a substrate or carrier. The dye evaporates as a volatile component of the product evaporates thereby changing the color of the substrate or carrier. The consumer is alerted to the depletion of the volatile component of the product when the substrate or carrier changes from a colored or dyed state to an uncolored state. As a result, a visual time duration or end of product life indicator is provided.

Abstract: The invention relates to new systems, methods and products for analyzing polymers and in particular new systems, methods and products useful for obtaining sequence information from polymers. The invention has numerous advantages over prior art systems and methods used to obtain sequence-related information. Using the methods of the invention the entire human genome could be analyzed several orders of magnitude faster than could be accomplished using conventional technology. In addition to obtaining sequencing information for the entire genome, the systems, methods and products of the invention can be used to create comprehensive and multiple expression maps for developmental and disease processes. The ability to analyze an individual's genome and to generate multiple expression maps will greatly enhance the ability to determine the genetic basis of any phenotypic trait or disease process.

Abstract: A molecular sieve particle-based analytic chemistry system is disclosed in which populations of encoded molecular sieve particles carrying different chemical functionalities are distributed into wells etched in an optical fiber bundle. The chemical functionalities are encoded on separate shaped molecular sieve particles using luminescent dyes and/or molecular sieve particle shapes and thus, a single sensor array may carry thousands of chemistries. Such encoded molecular sieve particles can provide at least a five-fold enhancement in tunable parameters for increasing the encoding possibilities of high throughput screening assays relative to the present dye-modified polymeric microsphere standard.

Abstract: A method of speciated isotope dilution mass spectrometry (SIDMS) which will permit determination of concentrations of one or more species from a sample even if the sample has been subjected to species conversion prior to species separation or degradation or incomplete separation exists. At least one predetermined stable isotope is spiked to convert the stable isotope to a speciated enriched isotope corresponding to the specie or species to be measured in the sample. The sample containing the species to be measured is spiked and the isotopic spiked specie and species to be measured are equilibrated. The species are separated from the sample and an isotope ratio determination for each specie to be measured is made. The species concentrations are then mathematically deconvoluted while correcting for species conversion and/or incomplete separation. The method may be employed to validate other methods. The method may also be employed in the preparation and analysis of speciated standard reference materials.

Abstract: To sample hot liquids containing volatile materials, the liquid is cooled in a refrigerator and pumped through a syringe needle into a container until the container overflows. The needle is removed slowly and the container is automatically closed as the needle is withdrawn, wherein liquid flows upwardly continuously as the needle is withdrawn through an opening. The cap for the container includes a closure having a valve opening extending upwardly and sized to narrowly receive the syringe needle in a perpendicular valve member opening. The valve member includes a flat member on one end adapted to be gripped by a cam follower for opening and closing of the valve opening in coordination with the movement of the syringe needle.

Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.

Abstract: A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

Abstract: A method of forming a ferroelectric film includes the steps of forming a layer by a material that takes a metal state in a reducing ambient and an oxide state in an oxidizing ambient, and depositing a ferroelectric film on a surface of the layer by supplying gaseous sources of the ferroelectric film and an oxidizing gas and causing a decomposition of the gaseous sources at the surface of said layer, wherein the step of depositing the ferroelectric film is started with a preparation step in which the state of the surface of said layer is controlled substantially to a critical point in which the layer changes from the metal state to the oxide state and from the oxide state to the metal state.

Abstract: Methods for forming capacitor of FeRAM are disclosed. The disclosed methods can prevent the step difference from an etch-back process and scratch on a Pt layer in a CMP process using a basic slurry by performing a CMP process using an acidic slurry including an organic acid when isolating a storage electrode in a formation process of a FeRAM capacitor.

Abstract: Data retention of a ferroelectric transistor is extended by injecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.

Abstract: A method and apparatus for determining a possible cause of a fault in a semiconductor fabrication process. The method includes determining a first fault in a first processing tool executing under first operating conditions and determining a second fault in a second processing tool executing under second operating conditions. The method further includes identifying a possible source of the second fault based on at least the first operating conditions of the first processing tool.

Abstract: In this invention, a time period taken with a wafer W to be transferred to the heat processing apparatus in the post exposure baking unit through the out stage in the aligner, the wafer transfer mechanism, the transition unit, the wafer transfer mechanism, and the temperature regulation and transfer apparatus in the post exposure baking unit is controlled to be approximately constant.

Abstract: To provide increased yields of semiconductor devices to achieve efficient production there are provided a storage correlating and storing inspection data of each of a plurality of semiconductor chips formed in a wafer and the position of each of a plurality of triac chips as seen on the wafer, a wafer screening portion referring to the inspection data of the semiconductor chips in the storage to select a wafer from a plurality of wafers, and a die-bonding portion die-bonding a triac chip formed in the selected wafer to a lead frame of a high rank semiconductor device having a superior characteristic.

Abstract: The present invention is generally directed to various methods of controlling wet chemical processes in forming metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal while the wet chemical process is being performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal.

Abstract: A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same are disclosed. The wafer-on-wafer package can be burned-in and tested at the wafer level prior to segmenting, or singulating, the wafer-on-wafer package into a plurality of individual chip-scale packages. The device wafer includes a plurality of unsingulated semiconductor dice having a plurality of die bond pads being respectively bonded to a plurality of electrically conductive die bond pad connect elements provided on a first surface of the support wafer.

Abstract: A method of forming a test pattern includes: forming first and second junction regions having a symmetrical structure on both side of field oxide layer formed on a semiconductor substrate; forming third and fourth junction regions having a asymmetrical structure on front and rear portions of the field oxide layer; forming a test pattern having first and second projection portions on the semiconductor substrate, in which both side portions of the test pattern are overlapped with the first and second junction regions and the first and second projection portions which are formed on front and rear portions of the test pattern are overlapped with the third and fourth junction regions; forming an inter insulating layer on a resulting structure after forming the test pattern; patterning the inter insulating layer to expose a portion of the first to fourth junction regions; forming current supply lines connected to the first and second junction regions, respectively; and forming voltage measuring lines connected to t

Abstract: A method includes scheduling a plurality of workpieces for processing by a plurality of tools. Each workpiece has an associated priority. The processing in at least one of the tools is controlled in accordance with a process control model. A process control request associated with the controlling of the tool is generated. The priorities of at least a subset of the workpieces are determined based on the process control request. A manufacturing system includes a plurality of tools for processing workpieces, a dispatch unit, and a process control unit. The dispatch unit is configured to schedule a plurality of workpieces for processing by the tools. Each workpiece has an associated priority. The process control unit is configured to control the processing in at least one of the tools in accordance with a process control model and generate a process control request associated with the controlling of the tool.

Abstract: A substrate processing apparatus includes a processing chamber which processes a substrate; a substrate supporting body which supports the substrate in the processing chamber; a heating member which heats the substrate and which is disposed on an opposite side from the substrate with respect to the substrate supporting body; a substrate temperature detecting device provided at a position opposed to a surface of the substrate; and a light-shielding member which shields stray light from the heating member and which is disposed around the substrate, wherein the light-shielding member has quartz members and an opaque member sandwiched between the quartz members.

Abstract: An improved method of high pass filtering a data set includes flattening the data set and then filtering the flattened data set with an adaptive filter. The data set is flattened by fitting it to a predetermined function, and then obtaining the difference between the original data set and the fitted data set. Beneficially, the predetermined function is a polynomial. The adaptive filter includes a masking function that has a constant, non-zero value (e.g., 1) within the bounds of the original data set and value of zero outside the bounds of the original data set.

Abstract: A ring-type laser including a traveling wave cavity which incorporates at least first and second straight cavity sections and at least one curved cavity section. Corresponding first ends of the straight cavity sections are interconnected at a first light-emitting facet, and second ends of the straight sections are interconnected by the curved waveguide. Additional curved and straight sections can be linked to provide various ring configurations.

Abstract: ICs (20) are nearly separated from the semiconductor substrate (10) on/in which they are formed. Subsequently, the substrate is positioned upside down on a substrate (carrier) (3) which is provided with glue (21) at the location of a crystal. After attachment of the crystal to the carrier, the semiconductor substrate is removed and the crystal remains attached to the carrier e.g. at the crossing of rows and columns. The separate crystals may contain TFTs (simple AM addressing) but also more complicated electronics (address of pixel in memory+identification).

Abstract: A method for creating a hybridized chip by combining a bottom active optical device and an electronic chip when at least some of the active device contacts are not aligned with at least some of the electronic chip contacts. The method involves adding an insulating layer, having a thickness, a first side and a second side, to the bottom active optical device by affixing the first side to the surface, openings in the insulating layer extending from the second side to the first side at points substantially coincident with the active device contacts, making the sidewalls electrically conductive, and connecting the points and the electronic chip contacts with an electrically conductive material. A hybridized chip has at least one bottom active optical device coupled to an electronic chip, the hybridized chip having been created using a described method. A method of connecting two chips, each having electrically corresponding contacts to be joined together but are physically mismatched relative to each other.

Abstract: Formed first is a template having openings located to correspond to a pattern in which a plurality of semiconductor laser elements are to be arranged. Then, the template is held on the principal surface of a mounting wafer onto which the semiconductor elements are to be arranged. Subsequently, the semiconductor laser elements are dispersed into a fluid, and the semiconductor-laser-element-dispersed fluid is poured over the wafer on which the template is held. In this manner, the semiconductor laser elements are disposed into the respective openings of the template in a self-aligned manner.

Abstract: A laser diode that uses air as a reflective layer, thereby enhancing reflectance with respect to an oscillating laser beam, and a method for fabricating such a laser diode are provided. The laser diode includes a substrate, a laser oscillating layer formed on the substrate, an upper electrode formed on the laser oscillating layer, and a reflective layer formed at one side of the laser oscillating layer, wherein the reflective layer comprises air layers. According to the laser diode and the method for fabricating the same, it is possible to form a reflective layer having a higher reflectivity with a reduced number of pairs of reflective layers, thereby making a laser diode whose threshold voltage is reduced and which can produce a high-output laser beam.

Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.

Abstract: A method of manufacturing a semiconductor device capable of reducing the manufacturing cost and preventing the yield-down caused by etching process comprises the steps of forming a separation layer 120 and an epitaxial film 130 carrying LEDs 130c on a substrate 110, forming a protection layer 150 on the epitaxial film, forming etching grooves by etching a region of the epitaxial film, which is not covered by the protection layer, etching the separation layer to make discrete epitaxial films 130a, and adhering the discrete epitaxial films 130a onto the surface of a silicon substrate 170.

Abstract: A method of making an organic vertical cavity laser array device includes providing a substrate and a first portion of a bottom dielectric stack reflective to light over a predetermined range of wavelengths and being disposed over the substrate; forming an etched region in the top surface of the first portion of the bottom dielectric stack to define an array of spaced laser pixels which have higher reflectance than the interpixel regions so that the array emits laser light; and forming a second portion of the bottom dielectric stack over the etched first portion. The method also includes forming an active region over the second portion of the bottom dielectric stack for producing laser light, and forming a top dielectric stack over the active region and spaced from the bottom dielectric stack and reflective to light over a predetermined range of wavelengths.

Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.

Abstract: A process for patterning dielectric layers of the type typically found in optical coatings in the context of MEMS manufacturing is disclosed. A dielectric coating is deposited over a device layer, which has or will be released, and patterned using a mask layer. In one example, the coating is etched using the mask layer as a protection layer. In another example, a lift-off process is shown. The primary advantage of photolithographic patterning of the dielectric layers in optical MEMS devices is that higher levels of consistency can be achieved in fabrication, such as size, location, and residual material stress. Competing techniques such as shadow masking yield lower quality features and are difficult to align. Further, the minimum feature size that can be obtained with shadow masks is limited to ˜100 &mgr;m, depending on the coating system geometry, and they require hard contact with the surface of the wafer, which can lead to damage and/or particulate contamination.

Abstract: A method for manufacturing a semiconductor device includes the steps of providing a substrate, depositing a monocrystalline sacrificial layer onto the substrate, depositing a monocrystalline function layer onto the sacrificial layer, and removing at least part of the sacrificial layer after the function layer depositing step.

Abstract: The present invention provides an image sensor capable of suppressing the dark current due to crystalline defects occurring at an edge of a field oxide layer and a method for fabricating the same. The present invention provides an image sensor including: a semiconductor substrate; an active area including a photodiode area formed in a predetermined position of the substrate, a floating diffusion area having a smaller area than the photodiode area and a channel area having a bottle-neck structure connecting to the photodiode area and the floating diffusion area; a field area for isolating electrically the active area; a field stop layer being formed beneath the field area by having a wider area than the field area through an expansion towards the active area with a first width; and a gate electrode formed on the substrate by covering the channel area and having one side superposed with a second width on one entire side of the photodiode contacted to the channel area.

Abstract: A multi-wavelength semiconductor image sensor comprises a p-type Hg0.7Cd0.3Te photo-absorbing layer formed on a single crystal CdZnTe substrate, a CdTe isolation layer deposited on the photo-absorbing layer, a p-type Hg0.77Cd0.23Te photo-absorbing layer deposited on the CdTe isolation layer, n+ regions which are formed in these photo-absorbing layers and form a pn-junction with each of these photo-absorbing layers, an indium electrode connected to each of these n+ regions and a ground electrode connected to the photo-absorbing layer, the semiconductor isolation layer being electrically isolated from the photo-absorbing layer.

Abstract: A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted to the exterior faces of the base structure. The multichip module may incorporate memory chips, processor chips, logic chips, A to D converter chips, and other chips in a compact package. The module permits chips that require extensive cooling to be positioned within the structure in a manner such that a large surface area of the chip is not in contact with other chips. The module also permits extensive interconnection between chips within the module.

Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.

Abstract: A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.

Abstract: Provided is a semiconductor apparatus manufacturing method capable of severing a base material without producing burrs. A multiplicity of semiconductor apparatuses are produced as follows. A multi-segment base material is obtained by mounting a multiplicity of semiconductor chips on a substrate having a wiring pattern, followed by sealing the semiconductor chips with resin, further followed by attaching a terminal portion having a terminal hole to a back surface of the substrate. A filler is charged in each terminal hole, and, after curing the filler, the base material is severed along a cutting line covering the terminal hole, whereupon the multi-segment base material is divided into separate semiconductor apparatuses. The terminal hole is left exposed along the cut surface of the semiconductor apparatus. Chilled water is applied to the filler filled in the terminal hole to remove it from the terminal hole.

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Abstract: The present disclosure pertains to a method of preparing a test specimen for testing of the bonding strength of a layer of additive material to a crystalline substrate, or testing of the bonding strength of one layer of additive material to a second layer of additive material, where both layers of additive material overlie a crystalline substrate. The method includes both test specimen “cutting” from a large sample of material and preparation of an individual test specimen for four-point adhesion testing. Also described is a fixture which is useful for cutting the individual test specimen from the large sample of material.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.

Abstract: In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.

Abstract: A method of manufacturing a semiconductor device using a lead frame composed of a plate-like body having a non-planar upper surface and a planar under surface. The plate-like body includes a first thin portion for mounting a semiconductor chip with pad electrodes, first thick portions radially arranged for forming lead electrodes respectively corresponding to the pad electrodes of the semiconductor chip, a second thin portion between pairs of the first thick portions, a third thin portion peripherally surrounding the first thick portions, and a second thick portion surrounding the third thin portion. The semiconductor chip and the lead electrodes are sealed to the same surface as all of the thin portions with a resin, after making a connection between the pad electrodes and the lead electrodes with connecting wires.

Abstract: A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

Abstract: A semiconductor device having a thyristor is manufactured and arranged in a manner that reduces or eliminates difficulties commonly experienced in the formation and implementation of such devices. According to an example embodiment of the present invention, a thyristor (e.g., a thin capacitively-coupled thyristor) is formed having some or all of the body of the thyristor formed inlayed in a semiconductor device substrate. A trench is provided in the substrate, and a semiconductor material is formed in the trench. One or more layers of material are formed in the trench and used to form a portion of a body of the thyristor. The thyristor is formed having adjacent regions of different polarity, wherein at least one of the adjacent regions includes a portion of the semiconductor material and at least one of the adjacent regions includes a portion of the substrate.

Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.

Abstract: A method of forming a CMOS TFT device. The present method features that the n+-ion doping procedure is performed after defining the contact holes located in the doped areas. Thus, the source/drain region of the NMOS can be formed. The present invention requires only five photomasks, thereby reducing the number of photomasks consumed in the prior art.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: In order to fabricate a semiconductor component having a contact electrode that is T-shaped in cross section, in particular a field-effect transistor with a T gate, a method is described in which a self-aligning positioning of gate base and gate head is effected by means of a spacer produced on a material edge.