Patents Issued in September 14, 2004
  • Patent number: 6790768
    Abstract: Method and apparatus are provided for polishing substrates comprising conductive and low k dielectric materials with reduced or minimum substrate surface damage and delamination. In one aspect, a method is provided for processing a substrate including positioning a substrate having a conductive material formed thereon in a polishing apparatus having one or more rotational carrier heads and one or more rotatable platens, wherein the carrier head comprises a retaining ring and a membrane for securing a substrate and the platen has a polishing article disposed thereon, contacting the substrate surface and the polishing article to each other at a retaining ring contact pressure of about 0.4 psi or greater than a membrane pressure, and polishing the substrate to remove conductive material.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: September 14, 2004
    Assignee: Applied Materials Inc.
    Inventors: Yongsik Moon, David Mai, Kapila Wijekoon, Rajeev Bajaj, Rahul Surana, Yongqi Hu, Tony S. Kaushal, Shijian Li, Jui-Lung Li, Shi-Ping Wang, Gary Lam, Fred C. Redeker
  • Patent number: 6790769
    Abstract: A method of manufacturing a semiconductor device includes forming an insulation film having a recess above a semiconductor substrate, depositing a conductive film on the insulation film and filming conductive film in the recess, and polishing the conductive film by a CMP process using CMP slurry in order to selectively leave the conductive film in the recess, the CMP slurry including a polishing component and a restoring component, thereby reducing a scratch formed on at least one of the insulation film and the conductive film by causing the scratch to be filled.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyuki Kurashima, Gaku Minamihaba, Hiroyuki Yano
  • Patent number: 6790770
    Abstract: A method if provided for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer in subsequent lithographic patterning and RIE etching processes to form a trench opening formed substantially over the via opening.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: September 14, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chao-Cheng Chen, Jen-Cheng Liu, Jyu-Horng Shieh
  • Patent number: 6790771
    Abstract: A bitline structure for DRAM and the method for forming the same. The bitline structure includes a first dielectric layer on a substrate, a bitline contact hole, formed through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: September 14, 2004
    Assignee: Nanya Technology Corporation
    Inventor: Kuo-Chien Wu
  • Patent number: 6790772
    Abstract: The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 14, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-chi Chung, Shin-Yi Tsai
  • Patent number: 6790773
    Abstract: A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: John S. Drewery, Ronald A. Powell
  • Patent number: 6790774
    Abstract: A wiring film, which can be formed into wiring for ULSI semiconductor circuits, is formed by first forming holes in an insulating film on a substrate; then depositing a metallic material of copper, copper alloy, silver or silver alloy into the holes under an atmosphere including hydrogen; and finally annealing the deposited metallic material. The metallic material can be deposited by a sputtering process in which the atmosphere includes an inert gas in addition to the hydrogen. Hydrogen doped in the metallic material during the sputtering process promotes diffusion of atoms in the metallic material. The diffusion eliminates voids in the deposited metallic material.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Kobe Steel, Ltd.
    Inventors: Takao Fujikawa, Makoto Kadoguchi, Kohei Suzuki, Takuya Masui
  • Patent number: 6790775
    Abstract: Methods of fabricating a through-substrate interconnect for a microelectronics device, the device including a substrate having a frontside and a backside, are disclosed. Some embodiments of the methods include forming a circuit element on the frontside of the substrate, forming a trench in the backside of the substrate that extends to the circuit element, forming a layer of an insulating polymeric material in the trench, removing sufficient polymeric material from the layer of insulating polymeric material to at least partially expose the circuit element, and forming an electrically conductive interconnect layer in the trench, wherein the interconnect layer is in electrical communication with the circuit element.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Arjang Fartash
  • Patent number: 6790776
    Abstract: The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: September 14, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Tony Chiang, Tse-Yong Yao, Barry Chin
  • Patent number: 6790777
    Abstract: The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: September 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Glenn J. Tessmer, Ju-Ai Ruan, Mercer Lusk Brugler, Sarah Hartwig
  • Patent number: 6790778
    Abstract: A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: September 14, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Lung Cheng, Ying-Lang Wang, We-Li Chen
  • Patent number: 6790779
    Abstract: A method for creating deep features in a Si-containing substrate for use in fabricating MEMS type devices is provided. The method includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: September 14, 2004
    Assignee: Lockheed Martin Corporation
    Inventors: James H. Schermerhorn, Matthew C. Nielsen, Richard J. Saia, Jeffrey B. Fortin
  • Patent number: 6790780
    Abstract: A three dimensional capacitor fabricated as part of a dual damascene process is disclosed. The capacitor structure comprises two barrier metal layers separated by a high k dielectric and is formed in all the via and trench openings. The upper barrier layer and dielectric is selectively removed from those openings which will have ordinary vias and conductors, the other opening remains as capaitor.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, Bruce A. Block
  • Patent number: 6790781
    Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Jigish D. Trivedi
  • Patent number: 6790782
    Abstract: The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: September 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chih-Yuh Yang, Cyrus E. Tabery, Ming-Ren Lin
  • Patent number: 6790783
    Abstract: Methods and apparatus for fabricating and cleaning in-process semi-conductor wafers are provided. An in-process wafer is placed within a closed chamber. A reactant gas is incorporated in a liquid solvent to form a “reactant mixture” that is capable of reacting with photoresist material (or other material) on a wafer surface to facilitate removal of the material from the wafer surface. The reactant mixture is condensed on one or more of the in-process wafer surfaces to form a thin film on the surface(s) of the wafer. The solvent in the reactant mixture acts as a transport medium to place the reactant gas on the wafer surface. The reactant gas is then able to react with the photoresist material (or other material) on the in-process wafer surface to effect removal the material. Following reaction of the reactant gas with the photoresist, the thin film of reactant mixture is removed from the wafer surface by flash heating, rinsing, draining, or other suitable means.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Terry L. Gilton, Li Li
  • Patent number: 6790784
    Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: September 14, 2004
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia
  • Patent number: 6790785
    Abstract: A thin discontinuous layer of metal such as Au, Pt, or Au/Pd is deposited on a silicon surface. The surface is then etched in a solution including HF and an oxidant for a brief period, as little as a couple seconds to one hour. A preferred oxidant is H2O2. Morphology and light emitting properties of porous silicon can be selectively controlled as a function of the type of metal deposited, Si doping type, silicon doping level, and/or etch time. Electrical assistance is unnecessary during the chemical etching of the invention, which may be conducted in the presence or absence of illumination.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: September 14, 2004
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Paul W. Bohn, Jonathan V. Sweedler
  • Patent number: 6790786
    Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Morgan, Patrick M. Flynn, Janos Fucsko
  • Patent number: 6790787
    Abstract: A method of producing a structure having narrow pores includes a first step of bringing pore-guiding members into contact with upper and lower surfaces of a member comprising aluminum as a principal ingredient and a second step of anodizing the member comprising aluminum as the principal ingredient to form narrow pores. The pore-guiding members contain the same material as a principal ingredient. The second step includes preferably a step of transforming the member comprising aluminum as the principal ingredient into a porous body comprising alumina having narrow pores oriented substantially parallel to the interfaces between the pore-guiding members and the member comprising aluminum as the principal ingredient.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: September 14, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den
  • Patent number: 6790788
    Abstract: A method is provided for processing a substrate including providing a processing gas comprising hydrogen gas and an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 14, 2004
    Assignee: Applied Materials Inc.
    Inventors: Lihua Li, Tzu-Fang Huang, Li-Qun Xia
  • Patent number: 6790789
    Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcycloterasiloxane and cyclopentene oxide.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Vishnubhai V. Patel
  • Patent number: 6790790
    Abstract: Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: September 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Bharath Rangarajan
  • Patent number: 6790791
    Abstract: A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric film is formed by ion assisted electron beam evaporation of TiO2 and electron beam evaporation of a lanthanide selected from a group consisting of Nd, Tb, and Dy. The growth rate is controlled to provide a dielectric film having a lanthanide content ranging from about ten to about thirty percent of the dielectric film. These dielectric films containing lanthanide doped TiOx are amorphous and thermodynamically stable such that the lanthanide doped TiOx will have minimal reactions with a silicon substrate or other structures during processing.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6790792
    Abstract: A cured polyphenylene polymer having a glass transition temperature no greater than 465° C. An integrated circuit article having a fracture toughness as determined by the modified edge liftoff test of at least 0.3 MPa-m1/2.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: September 14, 2004
    Assignee: Dow Global Technologies Inc.
    Inventors: Edward O. Shaffer, II, Kevin E. Howard, James P. Godschalx, Paul H. Townsend, III
  • Patent number: 6790793
    Abstract: In a method for manufacturing a semiconductor device, the following three steps (oxide film forming step, cycle purge step, and coating step) are performed sequentially before performing substrates processing with a semiconductor device manufacturing apparatus. In the oxide film forming step, an oxide film 28 is grown on the surfaces of a flange portion 27 and a cap portion 30 which compose metal parts of a furnace port by baking the furnace port 40 so that corrosion resistance is improved. In the cycle purge step, residual moisture on the part of a gas supply system 35 and inside the piping is removed to suppress a chemical reaction between DCS gas which increases corrosiveness by reaction with moisture, and the metal parts 41 of the furnace port.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: September 14, 2004
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yutaka Nishino, Kenichi Suzaki, Norikazu Mizuno
  • Patent number: 6790794
    Abstract: Disclosed are cleaning sheets comprising an additive and perfume. The additive is preferably selected from the group consisting of wax, oil, and mixtures thereof. The cleaning sheets preferably have at least two regions, where the regions are distinguished by basis weight. In particular, the preferred cleaning sheets comprise one or more high basis weight regions having a basis weight of from about 30 to about 120 g/m2 and one or more low basis weight regions, wherein the low basis weight region(s) have a basis weight that is not more than about 80% of the basis weight of the high basis weight region(s). Also disclosed are cleaning sheets having substantial macroscopic three-dimensionality, in addition to having multiple basis weights. Optionally, the macroscopically three-dimensional cleaning sheets can comprise a scrim material, which when heated and then cooled, contracts so as to provide a macroscopic three-dimensional structure.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: September 14, 2004
    Assignee: The Procter & Gamble Company
    Inventors: Saeed Fereshtehkhou, Paul Joseph Russo, Wilbur Cecil Strickland, Jr., Nicola John Policicchio
  • Patent number: 6790795
    Abstract: A fire blocking material is disclosed comprising a nonwoven fabric including para-aramid fibers and pre-oxidized polyacrylonitrile, and optionally, a garnett of recycled polybenzimidazole, para-aramid or meta-aramid, or combinations thereof to form a fire blocking textile meeting Federal Aviation Administration regulation FAR 25.853 and Appendix F to Part 25.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Tex Tech Industries, Inc.
    Inventors: David F. Erb, Jr., Eliza L. Montgomery, Eric D. Ritter
  • Patent number: 6790796
    Abstract: An industrial fabric used in the form of an endless fabric belt to form and convey a nonwoven fiber web during the manufacture of a nonwoven fabric has a web-supporting surface which includes rough-surface yarns which inhibit movement, namely, slippage, of the nonwoven fiber web relative to the web-supporting surface. Preferably, the rough-surface yarns make long floats in one or both directions, that is, lengthwise and/or crosswise, on the web-supporting surface.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: September 14, 2004
    Assignee: Albany International Corp.
    Inventors: Scott Sheldon Smith, Paul Allen Zimmerman, Mark Joseph Levine
  • Patent number: 6790797
    Abstract: A system, for example a footwear system, with moisture transport properties includes an insulating layer, which has transport properties, coupled to a fabric lining fabric with moisture transport properties. Antimicrobial efficacy can also be obtained by adding anti-bacterial treatments to the insulation and the lining, where the treatments could be anti-bacterial fibers, applications, or other technologies.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: September 14, 2004
    Assignee: Invista North America S.a.r.l.
    Inventors: Thomas E. Benim, Susan C. Chamberlin, Roger Franklin Parry
  • Patent number: 6790798
    Abstract: A highly absorbent composite sheet wherein a non-woven substrate having a bulky structure and solid SAP with a part contained inside said bulky structure and the rest exposed on the surface of said non-woven substrate are provided, a thermally fusible component being a hot-melt adhesive, the hot-melt adhesive forming a fibrous network and covering said solid SAP and fine cellulose fibers in contact with the solid SAP whereby a single or double fibrous network is provided with the solid SAP held in position. A method for manufacturing same, and an absorbent article using such highly absorbent composite sheet are also provided.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: September 14, 2004
    Assignee: Japan Absorbent Technology Institute
    Inventors: Migaku Suzuki, Ryoichi Matsumoto
  • Patent number: 6790799
    Abstract: A glass panel for a color cathode ray tube, which has a linear absorption coefficient of X-ray with a wavelength of 0.06 nm of from 30 to 38 cm−1 and which has a layer having a compression stress of at least 70 MPa formed by a chemical strengthening method at least at short axis end portions and/or long axis end portions of the outer surface of a face portion and at a center portion of the inner surface of the face portion.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: September 14, 2004
    Assignee: Asahi Glass Company, Limited
    Inventors: Yuichi Kuroki, Tsunehiko Sugawara
  • Patent number: 6790800
    Abstract: Disclosed is a dielectric ceramic composition represented by (1−x) (Mg1/3Ta2/3)O2-xZrO2(0<x≦0.2) that has high dielectric constants, high quality factor (Q) values, and stable temperature coefficients of the resonant frequency. The composition can easily achieve a high quality factor (Q) value by sintering for a lesser duration and at lower temperatures.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 14, 2004
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyun-Jai Kim, Seok-Jin Yoon, Ji-Won Choi, Chong-Yun Kang, Jong-Yoon Ha
  • Patent number: 6790801
    Abstract: Disclosed is a nonreducible dielectric composition. Provided is a highly reliable TC based dielectric composition prepared by adding a sintering additive having excellent qualities to a conventional (Ca1-xSrx)m(Zr1-yTiy)O3 based dielectric composition, so that it can be sintered under a reducing atmosphere to be used in formation of a nickel electrode, can be sintered at a low temperature of less than 1,250° C., and has a small dielectric loss and a high resistivity. The composition of the present invention includes a nonreducible dielectric composition comprising a main component expressed by the general formula, (Ca1-xSrx)m(Zr1-yTiy)O3, which has the ranges of 0≦x≦1, 0.09≦y≦0.35, and 0.7≦m≦1.05; and 0.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: September 14, 2004
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Min Kim, Jong Hee Kim, Dong Sook Shin, Young Tae Moon
  • Patent number: 6790802
    Abstract: A method of recovering halogen-containing materials from the cyclic catalyst regeneration operation of a catalytic hydrocarbon conversion process is disclosed. The method uses an arrangement of beds of adsorbent to return the halogen-containing materials to a circulating regeneration circuit.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: September 14, 2004
    Assignee: UOP LLC
    Inventor: Paul A. Sechrist
  • Patent number: 6790803
    Abstract: A hydroconversion catalyst for hydrodesulfurizing feedstock while preserving octane number of the feedstock includes a support having a mixture of zeolite and alumina, the zeolite having an Si/Al ratio of between about 1 and about 20, and an active phase on the support and including a first metal selected from group 6 of the periodic table of elements, a second metal selected from the group consisting of group 8, group 9 and group 10 of the period table of elements and a third element selected from group 15 of the periodic table of elements. A hydroconversion process is also disclosed.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: September 14, 2004
    Assignee: Intevep, S.A.
    Inventors: Jorge Tejada, Nelson P. Martínez, José Antonio Pérez, Leonardo Escalante, José M. Larrauri, José A. Salazar
  • Patent number: 6790804
    Abstract: A process of forming a polyolefin catalyst component includes contacting a metal compound of the formula MR2 with a diketone to form a metal bis(diketonate) having the formula M(OCRCR′CRO)2, wherein M is a Group IIA or Group VIIB metal, and wherein R and R′ are each hydrocarbyls or substituted hydrocarbyls having from 1 to 20 carbons atoms. Catalyst components, catalysts, polyolefin polymers, catalysts systems, and methods of preparing same are disclosed.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Fina Technology, Inc.
    Inventors: Steven D. Gray, Tim J. Coffy, Edwar S. Shamshoum
  • Patent number: 6790805
    Abstract: The invention relates to a process for the in-situ preparation of alkylated single-site transition metal catalysts by contacting a precatalyst with an alkylating agent in the presence of one or more olefin monomers in the polymerization system. The precatalyst, which is produced prior to introducing into the polymerization system, is obtained by contacting a transition metal complex and boron-containing ionizing agent, optionally, with a support.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: September 14, 2004
    Assignee: Equistar Chemicals, LP
    Inventor: Shaotian Wang
  • Patent number: 6790806
    Abstract: The core/jacket catalyst molding with a core made from an inorganic support material and with a jacket made from a catalytically active material can be prepared by coextruding an aqueous molding composition which comprises the support material or a precursor thereof, with an aqueous molding composition which comprises the catalytically active material or a precursor thereof, then drying the coextrudate, and then calcining the dried coextrudate.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 14, 2004
    Assignee: BASF Aktiengesellschaft
    Inventors: Michael Hesse, Rainer Anderlik, Hans-Gerhard Fritz, Jochen Hammer
  • Patent number: 6790807
    Abstract: A zirconium metal oxide fiber comprises zirconium oxide and a metal oxide. The fiber is made by adding a metal oxide in a suitable form to a colloidal dispersion of an amorphous zirconium polymer. The mixed colloidal dispersion is subsequently made into a fiber. The fiber may be used as a substitute for glass fiber in the manufacture of paper and paper-like materials. The fiber's thickness is substantially uniform and has a length usually in excess of one micron.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: September 14, 2004
    Assignees: Rothmans, Benson & Hedges Inc., AMR International Corp.
    Inventor: James L. Woodhead
  • Patent number: 6790808
    Abstract: In an exhaust gas purifying catalyst, an acid material with a high affinity with respect to an absorbing agent is dispersed and mixed in a catalyst layer, to which the absorbing agent is added, or a layer of the acid material is formed inside the catalyst layer in order to prevent the absorbing agent from moving from the catalyst layer into the carrier. This reduces the permeation of the absorbing agent added to the catalyst layer into a carrier, the evaporation and splash of the absorbing agent from the catalyst, and the deterioration in the durability and the exhaust gas purifying performance of the catalyst.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventors: Hiroshi Tanada, Osamu Nakayama, Keisuke Tashiro, Kinichi Iwachido, Tetsuya Watanabe
  • Patent number: 6790809
    Abstract: A heat-responsive-discoloring coloring composition, which is colored at a temperature lower than its discoloration initiation temperature (T) of 60° C. to 200° C.; which is substantially discolored at a temperature equal to or higher than the discoloration initiation temperature (T); and which does not recover its color once discolored, even when its temperature is lowered to a temperature lower than the discoloration initiation temperature (T) again, the heat-responsive-discoloring coloring composition comprising a polymer having a glass transition temperature (Tg) of 60° C. to 200° C.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: September 14, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Keiichi Suzuki
  • Patent number: 6790810
    Abstract: The invention relates to novel tetrazolinone derivatives of general formula (I) wherein R1 represents halogen, C1-4 alkyl, C1-4 haloalkyl, C1-4 alkoxy, C1-4 alkylthio, C1-4 alkylsulfonyl, C1-4 alkylsulfonyloxy, C2-5 alkoxycarbonyl, C2-6 alkoxyalkyl, C2-6 alkylthioalkyl, nitro or cyano, R2 represents a hydrogen atom, C1-6 alkyl, C3-6 cycloalkyl which may be optionally substituted with halogen, or C1-3 alkyl, C1-4 haloalkyl or phenyl which may be optionally substituted with halogen, or C1-3 aklyl, C1-4 haloalkyl or nitro, m represents 0, 1 or 2, n represents 0 or 1, Q represents one of the groups which are mentioned in the description. The invention further relates to their use as herbicides and a process together with the intermediates for their preparation.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: September 14, 2004
    Assignee: Nihon Bayer Agrochem K.K.
    Inventors: Akihiko Yanagi, Shinichi Narabu, Toshio Goto, Seishi Ito, Chieko Ueno
  • Patent number: 6790811
    Abstract: Invert emulsion compositions including an oleaginous, a non-oleaginous and an amine surfactant that are useful in the oil and gas well drilling art are disclosed. The amine surfactant is selected so that the invert emulsion can be converted form a water-in-oil type emulsion to a oil-in-water type emulsion upon the protonation of the amine surfactant. Deprotonation of the amine surfactant reverses the conversion.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: September 14, 2004
    Assignee: M-I LLC
    Inventor: Arvind D. Patel
  • Patent number: 6790812
    Abstract: High fluid loss acid soluble lost circulation material and spotting pill comprising the lost circulation material. The spotting pill preferably is weighted to a density substantially the same as the drilling fluid used to treat the formation.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Baker Hughes Incorporated
    Inventors: William S. Halliday, Dennis K. Clapper, Michael Jarrett, Michelle Carr
  • Patent number: 6790813
    Abstract: Oil compositions and formulated crankcase engine oils demonstrate improved fuel economy performance when comprising an overbased sulfonate detergent having a total base number greater than about 450 and which contain at least one other additive which includes a succinimide type dispersant. Methods for improving fuel economy employing such high TBN sulfonates and engine oil formulations and concentrates containing such are disclosed.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: September 14, 2004
    Assignee: Chevron Oronite Company LLC
    Inventor: Alexander B. Boffa
  • Patent number: 6790814
    Abstract: The present invention relates to particles that may be used to deliver materials, including but not limited to, laundry additives such as perfume materials; and detergent composition that contain such particles.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: September 14, 2004
    Assignee: Procter & Gamble Company
    Inventors: Edgar Manuel Marin, Jose Maria Velazquez, Jiten Odhavji Dihora, Roberto GarciaGonzalez, Gaurav Saini
  • Patent number: 6790815
    Abstract: The present invention relates to a product of reaction between a primary and/or secondary amine and one or more active ingredients. By the present invention, there is provided a release of the active component over a longer period of time than by the use of the active itself.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: September 14, 2004
    Assignee: Procter & Gamble Company
    Inventors: Jean-Luc Philippe Bettiol, Alfred Busch, Hugo Denutte, Christophe Laudamiel, Peter Marie Kamiel Perneel, Marie Montserrat Sanchez-Pena, Johan Smets
  • Patent number: 6790816
    Abstract: Contact lens cleaning compositions comprising preserved surfactant-containing solutions of a poly(oxypropylene)-poly(oxyethylene) adduct of ethylene diamine having a molecular weight from about 7500 to as high as 27,000 wherein at least 40 weight percent of the adduct is poly(oxyethylene) hydrophilic units. The solutions are effective in removing protein/lipid tear film deposits on both hard and soft contact lenses while providing a prophylactic-like action in retarding the formation of subsequent tear film deposits. The compositions provide effective cleaning and conditioning action using both ambient and high temperature disinfection methods.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: September 14, 2004
    Assignee: Bausch & Lomb Incorporated
    Inventors: Erning Xia, Christine E. Soltys-Robitaille, Lisa C. Simpson
  • Patent number: 6790817
    Abstract: The invention is a solid chemical concentrate system of at least two cooperative shapes. The first shape is an inwardly curved bar having an inner opening. The second shape is an insert which is capable of interlocking with the bar by insertion into the bar inner opening. The solid chemical concentrate provides chemical systems having active constituents which may be the same, different but compatible or functionally and chemically incompatible combined within one matrix to provide at least one substantially continuous surface. The system may also comprise an aqueous soluble or dispersible polymeric film cover.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: September 14, 2004
    Assignee: Ecolab Inc.
    Inventors: Elizabeth J. Gladfelter, Tina O. Outlaw, James L. Copeland, Rhonda K. Schulz, Daniel K. Boche, Jeff W. Peterson