Patents Issued in September 14, 2004
  • Patent number: 6791824
    Abstract: A motor board 44 of a capstan motor, which is made of a metallic material offering good heat dissipation is provided in a tape running apparatus 1 in such a way as to face a circuit board 6 thereof. A motor drive IC 43, into which drive circuits for driving and controlling a capstan motor 4, a drum motor 2 and a loading motor 3 is incorporated, are mounted on this motor board 44. The circuit board 6 and the motor board are connected to each other by an inter-board connector 7. Further, electrical connection between the circuit board 6 and each of the motors 2, 3, and 4 is established through the motor board 44.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Sankyo Seiki Seisakusho
    Inventors: Satoshi Tanimura, Hayato Naito, Izumi Komatsu, Nobuki Kokubo
  • Patent number: 6791825
    Abstract: A tablet computer housing assembly and housing construction method. A molded front housing has a planar perimeter margin and a front opening for viewing a LCD screen which is sealingly mounted within the housing assembly. A front sealing bracket having an open central portion is rigidly connected along an outer margin thereof to, and forms a seal with, the perimeter margin of the front housing. A molded rear housing having a planar perimeter margin and a rear sealing bracket and having an open central portion is rigidly connected to, and forms a seal with the perimeter margin of the rear housing. A flat compressible main sealing gasket having an open central portion is positioned between the front and rear sealing brackets to form a sealed connection therebetween whereby a sealed interior volume is established within the mating housings.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Pro-Design Solutions LLC
    Inventor: Alan R. Taylor
  • Patent number: 6791826
    Abstract: A hinge device installed between a rotatable panel and a computing module, having a keyboard installed thereon, has a first connection rod and a second connection rod. The first connection rod has a connection end connected to the rotatable panel, and a protruding end. The second connection rod has a hollow cylinder, a connection end connected to the keyboard for transferring torque to rotate the rotatable panel, and an indented end, having an engaging groove, for connecting with the protruding end of the first connection rod. When the protruding end engages with the engaging groove, the second connection rod will rotate with the first connection rod.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 14, 2004
    Assignees: Wistron Corporation, Acer Incorporated
    Inventor: Pei-Jan Ho
  • Patent number: 6791827
    Abstract: A wireless module for notebook is disclosed. The wireless module for notebook is combined on a logo area located on a LCD (Liquid Crystal Display) screen housing of notebook computer, wherein the logo area has at least one fixing holes (such as screw holes) used for fixing the wireless module on the notebook computer via at least one screws. Since the wireless module has only about 8 mm in thickness; the wireless module can be matched with the notebook computer smoothly and tightly. The wireless module comprises: at least one penetrating holes penetrating from the upper surface of wireless module to the lower surface thereof, and corresponding to the fixing holes; and a module contact for electrically connecting to a LCD contact point on the LCD screen housing of notebook computer.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: September 14, 2004
    Assignee: Quanta Computer, Inc.
    Inventor: Wen-Che Kuo
  • Patent number: 6791828
    Abstract: A system unit includes a media drive bay. The media drive bay includes a metal drive bay housing configured to receive a media drive. A connector is provided to interface with a connector on a received media drive. A resilient tongue integral with the media drive bay housing is operable to urge onto a received media drive to hold the media drive in place and to ground a casing of the media drive. A detent is provided for latching a latching member attached to the media drive casing. The media drive can be a commercially available media drive for non-removable use, the media drive being modified by the provision of the latching member to provide for removability.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: September 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Gerald Ronald Gough, Sean Conor Wrycraft
  • Patent number: 6791829
    Abstract: A disk drive bracket (1) includes a connecting bracket (10), a first bracket (20), and a second bracket (30). A first supporting member (14) and a second supporting member (16) sequentially extend from one side of the connecting bracket. A third supporting member (18) extends from an opposite side of the connecting bracket. Each supporting member includes a supporting board (144, 164, 184), and a locating board (142, 162, 182) having locating pins (150, 160, 183). The first and second brackets each have a side panel (24, 34) and a bottom panel (26, 36). Each bottom panel includes two parallel guiding flanges (264, 364). Locating pins (242, 244, 362) extend from the side panel of the first bracket, and from the bottom panel of the second bracket. The guiding flanges of the first and second brackets slidingly engage with the supporting boards of the second and third supporting members respectively.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: September 14, 2004
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Yun-Lung Chen, Jung-Chi Chen
  • Patent number: 6791830
    Abstract: An input device includes a case, circuit boards, and a support member. The case includes a rib formed therein to extend in a given direction. The circuit boards each include an input part, and are temporarily fastened to the case via the rib in process of assembling the input device. After the circuit boards are temporarily fastened to the case, the support member is fixed to the case so as to support the circuit boards between the support member and the case.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: September 14, 2004
    Assignee: Fujitsu Takamisawa Component Ltd.
    Inventors: Katsuya Funakoshi, Takashi Arita, Masayuki Kato
  • Patent number: 6791832
    Abstract: An electronic package for providing an increased density of electronic components in systems includes electronic components mounted on two surfaces of a substrate. Electrical coupling is provided by electrical contacts mounted with substantially the same arrangement and number on both surfaces of the substrate. Two conductive substrates having apertures are mounted adjacent and substantially parallel to the two component mounting surfaces such that the electrical contacts mounted on the two surfaces protrude through the apertures of the two conductive substrates. The two conductive substrates are coupled to one or more heat sinks to conduct heat away from the multiple electronic components contained between the conductive substrates. Multiple electronic packages can be coupled together to form a stacked electronic package by physically connecting the electrical contacts of the electronic packages.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Jacek Budny, Gerard Wisniewski
  • Patent number: 6791834
    Abstract: In a liquid-cooling system for a notebook personal computer having a body part including a CPU and a chip set respectively mounted on a mother board and an HDD, and a display part rotatably supported by the body part, a heat receiving head is fixed to at least one heat generation part including the CPU. A tube filled with cooling liquid is connected to the heat receiving head. The tube connected to the heat receiving head is disposed in series on at least one heat generation part including the chip set so as to collect the heat generated from each heat generation part. The tube is also laid in a meandering or zigzagging pattern between a liquid crystal panel and a housing of the display part. The heat generated from each heat generation part is absorbed at part of the tube by the cooling liquid that circulates in the tube and functions as a heat transfer medium. The absorbed heat is then radiated at another part of the tube.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Nakagawa, Yasushi Neho, Tatsuhiko Matsuoka, Masahito Suzuki, Masaaki Eishima, Kenichi Nagashima, Shinji Matsushita, Katsuhiro Arakawa, Kenichi Saito
  • Patent number: 6791835
    Abstract: A rectangular heating section is so shaped as to touch the electronic component except corners of the rectangle when the surface of the electronic component does not parallel the heating section. For example, the heating section is formed to be smaller than the electronic component surface, to be a rectangle which is smaller than the electronic component surface and comprises rounded corners, to be an octagon which is smaller than the electronic component surface and is formed by cutting off corners of the rectangle, or to be an octagon which is larger than the electronic component surface and is formed by cutting off corners of the rectangle. A die is prevented from being damaged due to a contact with the heating section of a cooling module at a given point of the die according to a mounting error or a usage state.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Hashimoto, Yoshinori Kamikawa, Tornomi Murayama
  • Patent number: 6791836
    Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Cipolla, Richard I. Kaufman, Lawrence S. Mok
  • Patent number: 6791837
    Abstract: A heat dissipating assembly includes a heat sink (120) attached on an electronic package (110), a fan (140) mounted to the heat sink, and an air guide device (20). The air guide device includes a duct (21) fixedly attached to a computer enclosure (40) at an air opening (42) thereof, and a hood (25) adjustably connected to the duct. The hood has a connection portion (26) adjustably connected to the duct, and a cover portion (29). The duct defines annular grooves (22) in an outer circumferential surface thereof, and the connection portion forms protrusions (28) on an inner surface thereof. The protrusions are engaged in selected annular grooves, to retain the hood on the duct at a desired position. The cover portion of the hood is near to and aligned with the fan. Heated air blown by the fan passes directly through the duct and out of the enclosure.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: September 14, 2004
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Fu-Ming Chen, Deyi Shi
  • Patent number: 6791838
    Abstract: A flexible assembly system and mechanism adapted for optical projection apparatus, the flexible assembly system includes a flexible element, a heat-sink element, a digital micro-mirror device module, an optical holder and a locked element, wherein the locked element is serially connected the flexible element, the heat-sink element, the digital micro-mirror device module and the optical holder, for making each element be formed in one-piece, whereby using the flexible element to eliminate the accumulative tolerance between each assembly element, and producing a compact combination between the heat-sink element and the digital micro-mirror device module, so that the digital micro-mirror device module has a best heat dissipating effect.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 14, 2004
    Assignee: Lite-On Technology Corporation
    Inventors: Min-Hsiung Hung, Hua-Shing Chen, Yin-Fa Tu
  • Patent number: 6791839
    Abstract: A composition that can be used to prepare a thermal interface material includes: A) a curable matrix having a curing temperature, B) a metal filler having a low melting point, optionally C) a spacer, and optionally D) a conductive filler. The temperature at which component B) commences softening is less than the curing temperature of component A). A thermal interface material is prepared by: 1) interposing the composition between an electronic component and a heat spreader to form a bondline, 2) heating the composition to a temperature higher than the temperature at which component B) commences softening but less than the curing temperature of component A) and optionally applying pressure to the composition, and 3) heating the composition to a temperature greater than or equal to the curing temperature of component A). The average particle size of component B) is greater than or equal to the bondline thickness.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: September 14, 2004
    Assignee: Dow Corning Corporation
    Inventor: Dorab Edul Bhagwagar
  • Patent number: 6791840
    Abstract: An incandescent tube bulb replacement assembly that is used in place of a horizontal incandescent tube light in a standard interior horizontal tube light fixture. The assembly includes a small printed circuit board (PCB) with a plurality of LEDs mounted perpendicularly thereon. During installation, the existing horizontal incandescent tube is removed and replaced with an LED assembly so that the LEDs fit into the center of the reflector. Attached to the opposite sides of the PCB are two, upward extending conductor arms that snap-fit into the two existing end conductors. The PCB includes a lighting circuit that allows the assembly to connect without regard to the polarity.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: September 14, 2004
    Inventor: James K. Chun
  • Patent number: 6791841
    Abstract: An electronic system has electronic equipment, and an electronic cabinet which houses the electronic equipment. The electronic cabinet includes a support structure which is configured to carry the electronic equipment, and a door panel which is configured to pivotally mount to the support structure. The door panel and the support structure define an opening through which a set of cables is configured to pass. The electronic cabinet further includes an assembly which is configured to manage the cables. The assembly includes a mounting bracket which is configured to mount to one of the support structure and the door panel at a location which is adjacent the opening, a section of flexible material which defines a set of grooves to hold the set of cables, and a fastener interconnected between the mounting bracket and the section of flexible material to fasten the section of flexible material to the mounting bracket.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: September 14, 2004
    Assignee: EMC Corporation
    Inventors: Paul T. Tirrell, Ralph L. Specht, Jr.
  • Patent number: 6791842
    Abstract: An image sensor includes a substrate, a frame layer, signal input terminals, a photosensitive chip, a transparent layer, a plurality of wires and a glue layer. The substrate has a first surface and a second surface. The frame layer is placed on the first surface to form a cavity together with the substrate. The signal input terminals are formed on the frame layer. The photosensitive chip has plural bonding pads, and is placed on the first surface of the substrate and positioned within the cavity. The transparent layer is placed over the frame layer to define, in the cavity, at least one exposure area through which the bonding pads of the photosensitive chip are exposed. The wires penetrate through the exposure area and electrically connect the bonding pads to the signal input terminals. The glue layer covers the exposure area to seal the plurality of wires.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 14, 2004
    Assignee: Kingpak Technology Inc.
    Inventor: Chung Hsien Hsin
  • Patent number: 6791843
    Abstract: An electronic system includes a first system component having a first connector and a second system component having a second connector. One of the first system component having the second system component pivots between a first position in which the first connector and the second connector are disconnected and a second position in which the first connector and the second connector are connected.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert W. Dobbs, Stephan K. Barsun, Andrew H. Barr
  • Patent number: 6791844
    Abstract: An electronic instrument has an instrument body 2, an operation unit 3, and an engagement link 4. The engagement link 4 removably attaches the operation unit 3 to the instrument body 2. The engagement link 4 has a first joint member 22 and a second joint member 23. The first joint member 22 engages with a lower end 3a of the operation unit 3. The second joint member engages with an upper end 3b of the operation unit 3. The link mechanism moves the second joint member 23 to release the second joint member 23 from the upper end 3b when the first joint member 22 moves toward an engaging position of the first joint member 22 with the lower end 3a. The link mechanism can move the second joint member 23 to engage with the upper end 3b while the first joint member 22 has been engaged with the lower end 3a.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: September 14, 2004
    Assignee: Pioneer Corporation
    Inventors: Yasuyuki Tobishima, Yasuharu Nakamura, Akira Shimizu
  • Patent number: 6791845
    Abstract: Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 14, 2004
    Assignee: FCI Americas Technology, Inc.
    Inventor: Yakov Belopolsky
  • Patent number: 6791846
    Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Larry D. Smith, Istvan Novak, Michael C. Freda
  • Patent number: 6791847
    Abstract: A retention module (30) of the present invention is fastened to a motherboard (50), and surrounds a land grid array (LGA) central processing unit (CPU) (52) which is engaged on an LGA socket (54) that is mounted on the motherboard. The heat sink includes a base (12), and a plurality of fins (14) extending upwardly from the base. A notch (16) is defined in each of four sides of the base. The retention module includes a rectangular bottom plate (32). A side plate (36) extends upwardly from each of four sides of the bottom plate. A locating block (40) is formed on an inside of each side plate. The locating blocks are fittingly received in the notches of the base, thereby preventing the heat sink from sliding in horizontal directions. Thus the heat sink is prevented from disturbing mechanical and electrical engagement of the CPU with the socket.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: September 14, 2004
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Hao-Yun Ma
  • Patent number: 6791848
    Abstract: Method and apparatus are disclosed for providing a constant voltage, high frequency sinusoidal output across a varying load, using either a single or multiple switch topology operating at constant frequency while maintaining high efficiency over the entire load range. This embodiment is especially suited to applications which require the sinusoidal voltage be held very close to a desired value in the presence of rapid changes in the conductance of the load, even in the sub-microsecond time domain as is common in computer applications and the like and in powering electronics equipment, especially a distributed system and especially a system wherein low voltage at high current is required.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: September 14, 2004
    Assignee: Advanced Energy Industries, Inc.
    Inventors: Robert M. Porter, Gennady G. Gurov, Anatoli V. Ledenev
  • Patent number: 6791849
    Abstract: A synchronous rectifying circuit for a flyback converter includes a synchronous rectifying element (Q2) coupled to the secondary winding (N2) of a transformer (T) and performing a synchronous rectifying operation according to an on/off operation of the synchronous rectifying element; an auxiliary inductance circuit (L3) coupled to the secondary winding (N2) of the transformer (T) and having an energy discharge time period shorter than that of the secondary winding (N2); and a control element (Q3) for turning the synchronous rectifying element (Q2) off in response to the detection of termination of the energy discharge of the auxiliary inductance circuit (L3).
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: September 14, 2004
    Assignee: Pioneer Corporation
    Inventor: Kazuaki Nakayama
  • Patent number: 6791850
    Abstract: A DC-to-AC power inverter includes an input port, an output port, a switching circuit, and a system controller. The switching circuit is electrically connected between the input port and the output port responsive to control signals to convert a DC voltage at the input port to an AC output voltage. The system controller senses the AC output voltage at the output port and transforms the AC output voltage to generate a first reference current signal. Furthermore, the system controller senses an output current at the output port to generate an output current signal. Moreover, the system controller senses a reference current signal by adding the first reference current signal to the output current signal. Finally, the system controller generates the control signals responsive to the reference current signal and a sensed inverter current signal by sensing an inverter current at the switching circuit. The related methods are also discussed.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: September 14, 2004
    Assignee: Delta Electronics, Inc.
    Inventors: Fu-Sheng Pai, Ming-Tsung Tsai
  • Patent number: 6791851
    Abstract: A drive transformer and associated circuitry for providing power and appropriate delays to primary switches and synchronous rectifiers in switch-mode power converters in a full-bridge topology. The invention takes advantage of the leakage inductances of the drive transformer windings as well as the input capacitance of the primary switches (MOSFETs) to provide the delays. No separate circuitry is needed to provide such delays, thereby providing reliability. Exemplary embodiments further disclose means to disable or enable the primary winding from a condition sensed on the secondary side even with a control and feedback circuit located on the secondary side. The invention further discloses means to use one drive transformer winding to control two switches completely out of phase.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: September 14, 2004
    Assignee: di/dt, Inc.
    Inventor: Milivoljee S. Brkovic
  • Patent number: 6791852
    Abstract: A method is provided for determining a shorted thyristor cell in a bridge that supplies a load from a source, the bridge including a plurality of the thyristor cells. The method includes the step of sequentially gating each of the cells to a conducting state, so that only one cell is gated at one time; providing at least one current transformer in the bridge; generating a current flow that passes through the bridge including the one cell that is gated; observing current in the at least one current transformer to determine a short in one of the cells the that is not gated; and determining a shorted cell based on the step of observing current in the at least one current transformer.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 14, 2004
    Assignee: General Electric Company
    Inventors: Richard W. Carter, Rick L. Gintz, Allen M. Ritter
  • Patent number: 6791853
    Abstract: A peripheral power hub (PPH) (44) providing power to a plurality of outputs (46). The PPH provides multiple predetermined DC voltages which may be converted by an associated voltage converter circuit (28) to provide the power requirements to an associated mobile device (72). Alternatively, the voltage converter circuits (28) may be internal to the PPH. A programmable Ac/Dc converter (42) may provide a DC voltage to the PPH, which may be configured as an an accessory while powering another mobile device, such as a laptop computer (50). The voltage converter circuits (28) may be buck circuits or boost circuits depending on the application.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: September 14, 2004
    Assignee: Mobility Electronics, Inc.
    Inventors: Ejaz Afzal, Garry DuBose, Gil MacDonald
  • Patent number: 6791854
    Abstract: A semiconductor apparatus includes positive and negative side conductors for bridge-connecting semiconductor switches, constituted to a wide conductor, and laminated by sandwiching an insulator between them. A semiconductor apparatus includes positive and negative side conductors extended from its case, and an electrolytic capacitor connected to the extension portion of the positive and negative side conductors. A power converter uses the semiconductor apparatus.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Akira Mishima, Hideshi Fukumoto, Keiichi Mashino, Toshiyuki Innami
  • Patent number: 6791855
    Abstract: The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin A. Batson, Robert E. Busch, Gary S. Koch, Fred J. Towler, Reid A. Wistort
  • Patent number: 6791856
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Patent number: 6791857
    Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Darrel Bloomquist, Manoj K. Bhattacharyya, Thomas C. Anthony
  • Patent number: 6791858
    Abstract: A CMOS imager has a programmable current multiplication stage provided between a master current reference and the analog circuitry. The master current of each chip can be stored on-chip, for example, in a fuse-type ROM during production testing. By programming the current multiplication stage using the stored master current information, the master current can be chosen correctly for each chip, regardless of variations in manufacturing, thereby improving the production specification to the customer.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Sandor L. Barna, Giuseppe Rossi
  • Patent number: 6791859
    Abstract: A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Glen Hush, Jake Baker
  • Patent number: 6791860
    Abstract: By adding multiple rows of auxiliary switches and then multiple current paths a read only memory circuit can be formed to reduce loading values when reading a specific memory cell. Therefore, the current can be increased, and the error probability of the sense amplifier can be reduced when reading a specific memory cell.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: September 14, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Shi-Xian Chen
  • Patent number: 6791861
    Abstract: A ferroelectric memory device includes a plurality of wordlines and a plurality of plate lines, the wordlines and the plate lines being alternately formed at regular intervals in one direction; a plurality of sub bitlines and a plurality of main bitlines, the sub bitlines and the main bitlines alternately formed at regular intervals to cross the wordlines and the plate lines; a plurality of sub cell arrays connected with the wordlines, the sub bitlines and the plate lines, having cells in directions defined by a plurality of rows and columns, the cells in the direction of the rows being arranged every two columns and the cells in the direction of the columns being arranged every two rows, respectively; and switching elements each operating between one of the sub bitlines and one of the main bitlines by an externally applied bitline switch signal of a constant pulse type to selectively connect the sub bitline with the main bitline.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: September 14, 2004
    Assignee: Hynix Semiconductor INC
    Inventors: Hee Bok Kang, Hun Woo Kye, Geun Il Lee, Je Hoon Park, Jung Hwan Kim
  • Patent number: 6791862
    Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Craig T. Salling, Brian W. Huber
  • Patent number: 6791863
    Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa
  • Patent number: 6791864
    Abstract: A memory device including array (12) of memory cells (10) having an array voltage Vdd bussed such that the Vdd of columns are controlled independently. During a WRITE cycle, the Vdd of the addressed columns is lowered. Thereafter, the stability of the cell is reduced, and the cell (10) is advantageously more easily written. Cells in other columns in the addressed row remain at full Vdd and are more stable. Cells in un-addressed rows in the addressed columns will not have the access transistors turned on, and therefore will be more stable. With WRITE being facilitated with a lowered column Vdd, the cell is designed to be more stable than would otherwise have been possible while maintaining the ability to WRITE.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: September 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 6791865
    Abstract: A memory device having a cross point array of memory cells includes a temperature sensor and a reference memory cell. The temperature sensor senses the temperature of the memory device and data from the temperature sensor and the reference memory cell are used to update write currents used to program the array of memory cells. A method of calibrating the memory device involves detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating write current values if the temperature of the memory device changes by the threshold value. The write current values can be updated by data from the reference memory cell, or from write current values stored in a lookup table.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lung T. Tran, Manoj K. Bhattacharyya
  • Patent number: 6791866
    Abstract: A magnetoresistive film having a relatively large magnetoresistive effect includes a ferrimagnetic layer, a magnetic layer, and a tunneling barrier layer disposed between the ferrimagnetic layer and the magnetic layer, the ferrimagnetic layer whose major composition including a rare earth metal and a transition metal, the magnetoresistive film including oxidized are rare earth metal that exists near an interface between the ferrimagnetic layer and the tunneling barrier layer.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 14, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takashi Ikeda
  • Patent number: 6791867
    Abstract: A data storage device includes a plurality of shunt elements having controlled current paths connected in series, and a plurality of memory cells having programmable resistance states. Each memory cell is connected across the controlled current path of a corresponding shunt element.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Lung T. Tran
  • Patent number: 6791868
    Abstract: A new method of performing the write operation on the MRAM bit cell with improved switching selectivity and lower write current requirements is achieved utilizing oscillating word write currents at frequency near the ferromagnetic resonance frequency of the free layer, combined with the shift in said frequency due to the magnetic field produced by the current in the bit line. Operation is implemented in a conventional magnetic random access memory having a plurality of magnetoresisitive cells formed by an intersection of a grid of word and bit lines, wherein an individual cell within the grid can be selected and switched from one magnetic state to another by the magnetic fields produced by the currents in the word and bit lines.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Savas Gider, Vladimir Nikitin
  • Patent number: 6791869
    Abstract: A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tsukasa Ooishi
  • Patent number: 6791870
    Abstract: The invention includes a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit. The invention also includes methods of storing and retrieving information.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Hasan Nejad
  • Patent number: 6791871
    Abstract: An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: September 14, 2004
    Assignee: Infineon Technologies AG
    Inventors: Martin Freitag, Thomas Roehr
  • Patent number: 6791872
    Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Darrel Bloomquist, Manoj K. Bhattacharyya, Thomas C. Anthony
  • Patent number: 6791873
    Abstract: The invention includes an apparatus and method for generating a write current for a magnetic memory cell. The apparatus includes a write current generator for generating a write current, the write current being magnetically coupled to the magnetic memory cell. The apparatus further includes at least one test magnetic memory cell, the write current being magnetically coupled to the at least one test magnetic memory cell. A switching response of the at least one test magnetic memory cell determines a magnitude of the write current generated by the write current generator. The method for determining a write current for a magnetic memory cell includes supplying a test write current to a test magnetic memory cell, sensing a magnetic state of the test magnetic memory cell to determine a switching response of the test magnetic memory cell, and generating the write current having a magnitude that is dependent upon the switching response.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Frederick A. Perner
  • Patent number: 6791874
    Abstract: A memory device having a cross point array of memory cells includes a temperature sensor and a reference memory cell. The temperature sensor senses the temperature of the memory device and data from the temperature sensor and the reference memory cell are used to update write currents used to program the array of memory cells. A method of calibrating the memory device involves detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating write current values if the temperature of the memory device changes by the threshold value. The write current values can be updated by data from the reference memory cell, or from write current values stored in a lookup table.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lung T. Tran, Manoj K. Bhattacharyya
  • Patent number: 6791875
    Abstract: Two complementary bit lines corresponding to a selected column are pulled down to a ground voltage via each of a selected MTJ memory cell and a dummy memory cell and are pulled up to a power supply voltage via a read drive selection gate. A read gate corresponding to the selected column drives the voltages of two complementary read data buses by driving force according to the voltage of corresponding complementary two bit lines, respectively. A data reading circuit executes data reading operation on the basis of a voltage difference between the complementary two read data buses. The power supply voltage is determined in consideration of reliability of a tunneling insulating film of an MTJ memory cell.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideto Hidaka