Abstract: A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Abstract: A NAND type flash memory device including a word line decoder is disclosed. The word line decoder includes a row decoder, a control unit and a driving unit. The row decoder receives an address of a given memory cell to produce a signal informing whether the memory cell is selected. The control unit outputs a positive or a negative voltage according as the memory cell was selected or not. The driving unit has NMOS transistors for outputting the negative voltage from sources to drains if the positive voltage outputted from the control unit is applied to gates of the NMOS transistors. The NMOS transistors prohibits the negative voltage inputted to the sources from being outputted to the drains if the negative voltage from the control unit is applied to the gates. The negative voltage inputted to the sources is applied to a P well of the NMOS transistors.

Abstract: A programmable and non-volatile analog signal storage structure and method are disclosed that employ two non-volatile cells which are arranged as a differential transistor pair. The non-volatile transistor at the positive (or non-inverting) terminal of the amplifier is referred to as the reference cell, while the non-volatile transistor on the negative (or inverting) input of the amplifier is referred to as the storage cell. The structure comprises a storage cell and a reference cell that produces a voltage which is independent of temperature and supply voltage variation. Additionally, the circuit structure is capable of operating at low supply voltage levels (<1.5V).

Abstract: A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

Abstract: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a second source electrode and a second drain electrode and is capable of having different mutual conductances according to the threshold voltage of the non-volatile memory element. The read transistor element has a switching state according to the electron injection state or the electron emission state, in other words, the writing state or the erasing state of the floating gate electrode. In a read operation, it is not necessary to cause a channel current to flow according to the threshold voltage of the non-volatile memory element.

Abstract: An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.

Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract: A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a high state while accessing a storage node. The high state is provided by a boost created by the addition of the capacitive elements.

Abstract: The present invention relates to a simplified reference current generator for a magnetic random access memory. The reference current generator is positioned in the vicinity of the memory cells of the magnetic random access memory, and applies reference elements which are the same as the magnetic tunnel junctions of the memory cell and bear the same cross voltages. The plurality of reference elements are used for forming the reference current generator by using one or several bit lines, and the voltage which is the same as the voltage of the memory cell is crossly connected to the reference elements so as to generate a plurality of current signals; and a peripheral IC circuit is used for generating the plurality of midpoint reference current signals and judging the data states. Thanks to the midpoint reference current signals, the multiple-states memory cell, including the 2-states memory cell, can read data more accurately.

Abstract: A semiconductor memory device includes a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. The device includes an output driver for generating a data strobe signal in response to the data signal, a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a logic high level to a logic low level, when the preamble control signal is activated. Data output from the semiconductor memory device has a satisfactory preamble section.

Abstract: A system supports Double Date Rate (DDR) or Single Data Rate (SDR) data transfers on a data bus between a processor and a memory device. A controller-side interface block connects to a memory-side interface block for generating the control signals and transferring stored data from the memory device to the processor.

Abstract: A data read circuit produces read data in accordance with a difference between currents flowing through first and second nodes, respectively. In a data read operation, a current transmitting circuit and a reference current generating circuit pass an access current corresponding to a passing current of a selected memory cell and a predetermined reference current through first and second nodes, respectively. In a test mode, a current switching circuit passes equal test currents through the first and second nodes instead of the access current and the reference current, respectively. Thereby, offset of the current sense amplifier in the data read circuit can be evaluated.

Abstract: A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

Abstract: A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.

Abstract: The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.

Abstract: A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.

Abstract: A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.

Abstract: The state of a prescribed internal column address signal bit is selectively fixed according to a mode switch circuit. A specific row address signal bit is transmitted instead of a column address signal bit under the control of the mode switch circuit. Thus, a semiconductor memory device having a plurality of storage capacities and address spaces is realized with a single chip structure.

Abstract: A word line driving circuit is described herein. The word line driving circuit comprises a pull-up transistor and pull-down transistor serially connected to each other, and a control circuit configured to turn off the pull-up transistor and to turn on the pull-down transistor in response to an active command, to enable a word line driving signal to a LOW state, to turn on the pull-up transistor and to turn on the pull-down transistor for a given period of time in response to a precharge, to precharge the word line driving signal to a HIGH state, and to turn off the pull-up transistor and pull-down transistor to float the word line driving signal after the precharge command.

Abstract: Embodiments of the present invention provide a memory device having multiple modes of data transfer. In one embodiment, async/sync logic and a configuration register provide for asynchronous and synchronous data transfer. The async/sync logic utilizes the configuration register and various control signals to determine whether a data transfer operation should be asynchronous or synchronous. The async/sync logic also utilizes the configuration register and various control signals to determine other functionalities of the particular data transfer mode. Functionalities may include normal and page mode, page length, bust read, linear or interleaved burst, burst wrap, burst suspend, data hold length, first access latency, transition between synchronous and asynchronous mode, and the like.

Abstract: The patent discloses a signal processing technique for determining the fast and slow shear wave polarizations, and their orientation, for acoustic waves in an anisotropic earth formation. The signal processing method decomposes composite received waveforms a number of times using a number of different strike angles. The decomposed signals are used to create estimated source signals. The estimated source signals are compared in some way to obtain an objective function. Locations in a plot where the objective function reaches minimum values are indicative of the acoustic velocity of the fast and slow polarizations within the formation.

Abstract: A method of calculating a throw volume corresponding to a seismic data volume. A range of time shifts and a search direction for the seismic data volume are selected. A data location separation and a vertical time window are also selected. A cross-correlation is calculated between data values corresponding to first and second data locations separated by the data location separation and symmetrically located in the search direction on each side of a target data location. The cross-correlation is calculated throughout the vertical time window for each time shift in the range of time shifts. The time shift corresponding to the maximum calculated cross-correlation is stored in the throw volume.

Abstract: Seismic detection apparatus comprising seismic detection means capable of detecting a plurality of seismic components over a defined tetrahedral volume is provided. The seismic detection means comprises four three-component geophones. Seismic data acquired by the geophones is processed to separate P-wave components from S-wave components. The geophones are spaced apart by distances smaller than the wavelength of the detected seismic components. The apparatus may be used on surface or in a marine environment or transition zone. A method of processing seismic data is also provided comprising acquiring seismic data relating to a wavefield over a selected volume of acquisition, and measuring the curl and divergence of the wavefield from the seismic data, to thereby identify seismic components within the seismic data. Additionally, an apparatus and method for hydrocarbon exploration is disclosed for using three or more seismic receivers placed in a plane and spaced closely to each other.

Abstract: A portable fish finder device with a housing that defines a wrap cavity for receiving a signal cable that communicates between a depth finder device and a transducer attached to the water craft. A skirt connected to the housing moves between a first position covering the wrap cavity and a second position uncovering the cavity for winding or unwinding the signal cable. The depth finder device pivotally mounts to the housing to move between a storage position with a display screen received in a recess of the housing and an extended position for viewing the display. The cable winds into the wrap cavity for storage and unwinds when the housing is disposed on a portion of a water craft for use of the depth finder with the transducer communicating signals in a body of water for detecting underwater articles.

Abstract: An electronic diving watch (1) with an analog display is described, comprising bidirectional driving means respectively of an hour hand (11) and a minute hand (12). The watch has a diving operating mode in which the display hands of the current time are likewise used in order to display data relating to the dive. More precisely, the hour hand (11) is used for the indication of information which is vital for the wearer of the watch, i.e. either that his body has not been subjected to physiological modifications which are significantly substantial enough for him to be required to observe a decompression stage during the ascent, or the parameters of the stage(s) to be effected, if need be. Liquid crystal screens (14, 15) are furthermore provided in order to display complementary information.

Abstract: A method and apparatus to receive selected audio content. According to one embodiment of the invention, an audio playback system is described. The audio playback system includes an audio content server and a device. The audio content server includes audio content to be selected for playback. The device calls the audio content server to request and receive an audio playback of selected audio content at a scheduled time.

Abstract: A timepiece is provided with a solar cell 8 comprising a power generation unit 39, having a first electrode, a photovoltaic layer, and a second electrode, stacked up in that order on the solar cell substrate 31 so as to be superimposed on each other, and electric power generated by the solar cell 8 is used as an energy source for executing time display on a time display unit by a dial 14 and hands 5, 6 or a liquid crystal display panel 50. The solar cell 8 is constructed such that a plurality of the power generation units 39, and transmitting portions 40 having a transmittance of light, larger than that for the power generation units, are alternately patterned on a solar cell substrate 31, and is disposed on the visible side of the time display unit so as to be superimposed thereon, thereby ensuring satisfactory power generation efficiency of the solar cell without impairing visibility of the time display unit, and without introducing restrictions on the design feature of the timepiece.

Abstract: In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.

Abstract: Disclosed is an automobile audio system. The automobile audio system includes a control panel for displaying audio data, and a control unit that is wired to the control panel. The control unit includes a hard disk and a compact disc player capable of playing at least one compact disc. Interface circuitry enables the wiring of the control unit to the control panel, and a processor and memory are connected to the interface circuitry. The memory is configured to store program instructions for extracting music data from the at least one compact disc and for recording the extracted music data to the hard disk.

Abstract: A magneto-optical recording medium, including a recording layer, a transfer control layer magnetically coupled to the recording layer, and a reproduction layer. The recording layer includes a recording magnetic domain in which information is recorded by a magnetization direction vertical to the surface of the film. The reproduction layer includes a reproduction magnetic domain in which information in the recording layer is transferred and formed as a magnetization direction by magnetic coupling. The direction of magnetization of the recording magnetic domain of the recording layer and the direction of magnetization of the transfer control layer corresponding to the recording magnetic domain are in opposite directions in at least part of the range of temperatures less than a transfer temperature where the reproduction magnetic domain is transferred to the reproduction layer. The Curie point temperature of the transfer control layer is higher than this transfer temperature.

Abstract: When an instruction to enter information unqualified for programmed reproduction is accepted, an optical disc reproducing apparatus according to the present invention gives a notification indicating that that information cannot be entered in a program. The disc detection unit 204 detects and decides a type of each optical disc, whether or not the disc can be entered in the program, and also detects the largest track number, the system controller 501 directs the disc information memory unit 502 to store the types of optical discs, information about possibility of entry in the program, and the largest track number associated with disc accommodation locations.

Abstract: Disclosed is an automated data storage library for storing and retrieving data storage media in a plurality of storage slots, for a host processor. At least one drive unit is coupled to the host processor for reading and/or writing data on the data storage media. A library manager includes a stored table for identifying the data storage media stored in the storage slots, the stored table indicating artificial scaling of the data storage capacity of selected data storage media to selected values less than the actual data storage capacity thereof. The stored table also stores indicators of attributes of the library with respect to ones of the data storage media, such as indicating that the drive unit is to communicate at the drive/host interface in a specific protocol.

Abstract: The invention relates to a motion control system for driving a motor-driven device precisely to a predetermined position in a short time. More particularly, this invention relates to a CD-carousel loader having a precise and short access to the next information medium. The object of the invention is to provide a motion control system for a platter of a CD carousel which requires little outlay and satisfies the requirements in respect of high positioning accuracy, short motion duration and self-locking. According to the invention, this object is achieved by means of a drive system comprising a motor driving circuit and a braking circuit having a common input terminal responsive to a pulse signal during a deceleration period in front of a predetermined position of the motor-driven device.

Abstract: A connecting member connects a pair of holder plates toward the end of the holder plates at the recessed end in the direction in which the disk is inserted. By forming the holding member holding disks using three pieces, there is less deformation causes by high temperatures compared to integrally formed units. Also, since this connecting member only serves to connect the pair of holder plates, a thin rod-shaped connecting bar can be used. This allows the clearance between the disks held toward the back of the device and the rear panel to be minimized, thus contributing to a reduced depth dimension for the device.

Abstract: When an external disturbance that causes the corrected amount of light reflected from a glass master disk 15 to surpass a threshold value T1 is applied to the control loop, not only the main control section 38 but also the sub-control section 37 controls the corrected amount 27. In this case, the influence of the external disturbance is suppressed quickly. More specifically, the control voltage of the main control section 38 is held the moment the corrected amount 27 of light reflected surpasses the threshold value T1. The sub-control section 37 controls the corrected amount 27 while the corrected amount 27 remains greater than the threshold value T1, and the sum of the control voltages of the main control section 38 and sub-control section 37 is applied to the piezoelectric element 23, thereby suppressing the influence of the external disturbance.

Abstract: A method for multi-track optical data recording comprising the steps of providing an optical recording medium that includes a plurality of parallel, preformatted guide tracks, with sufficient space between adjacent guide tracks for recording a plurality of data tracks; providing relative motion between the optical recording medium and an optical head in a direction generally parallel to the guide tracks; imaging a guide track onto a detector array disposed relative to the optical recording medium; and generating a first tracking error signal representing the cross-track displacement of the guide track relative to the optical head. The method further comprises driving a closed-loop servo system to reduce the residual tracking runout of the guide track and simultaneously recording a band of data tracks in the unpreformatted space adjacent to the guide track and one or more control tracks parallel to the data tracks.

Abstract: The present invention relates to a track access apparatus and a method by which an optical pick-up unit quickly accesses a destination track of an optical disc by controlling a tracking actuator using a back electromotive force by detecting the vibration of an objective lens, the position variation, and the distortion of an actuator which occur when the optical pick-up unit is moved across the tracks of the optical disc at a high speed.

Abstract: A servo control apparatus is provided to a stable servo control even when delays occur in detecting defects. Based on reflected light of an optical beam from an optical disc, a defect resulting from dark spots, damages, or others on the optical disc is detected. Immediately before the detection, sample data of a control signal are memorized. The sample data are obtained during a predetermined interval of time that corresponds to a detection delay for the defects, which is dependent on a defect detecting device. Using the memorized sample data, a cancel signal is produced for canceling the influence of the control signal, which is owing to a pseudo error signal obtained during the predetermined interval of time. The cancel signal is outputted as the control signal immediately after the detection of the defect.

Abstract: An optical recording medium that permits high density recording and only needs a recording machine of simple structure, and a machine for reproducing recorded information from such optical recording medium. A track pitch of recording tracks is smaller than a diameter of a beam spot of a scanning laser beam, and tracking pits for tracking control are formed on the respective recording tracks. A certain number of neighboring recording tracks define a group, and in each group the tracking pits are spaced from each other in a recording track direction by a predetermined interval which is smaller than the diameter of the beam spot.

Abstract: A data recording apparatus that accurately records constant linear velocity (CLV) or zone constant linear velocity (ZCLV) data on a recording medium while rotating the recording medium based on the CAV method. A data recording apparatus supplies data recorded on a recording medium, which is rotated by a motor, to a pickup device. The pickup device generates position information indicating the position of the pickup device with respect to the recording medium. The apparatus includes a recording control circuit that controls the motor such that the recording medium is rotated in a manner compliant with a constant angular velocity (CAV) method and controls an output rate of the data supplied to the pickup device based on the position information such that the data is recorded on the recording medium in a manner compliant with a CLV or a ZCLV method.

Abstract: A selective disturbance compensating apparatus for use in reproduction from an optical recording medium, and a 3T-correcting method. A DC offset canceller extracts a DC offset from a reproduction signal to cancel the DC offset. An equalizer equalizes the offset-cancelled signal. A switching unit selects between the offset-canceled signal and the equalized signal according to whether distortion caused by asymmetry of the signal is above or below a predetermined reference level. A 3-T correcting unit corrects asymmetry of the selected signal. In another embodiment, a second switching unit selects between the 3-T corrected signal and a Viterbi corrected signal.

Abstract: A physical identification data (PID) addressing method using a wobble signal, a wobble address encoding circuit, a method and circuit for detecting the wobble address and a recording medium therefor. A wobble signal obtained by phase modulating address information indicating the physical identification information and a wobble signal having only a simple carrier are recorded in each groove track by way of time division multiplexing. Groove tracks are divided into odd groove tracks and even groove tracks, and a wobble carrier and wobble address information are alternately recorded in each groove track and between odd and even groove tracks such that the wobble address information is not recorded in a section of an even groove track corresponding to a section of an odd groove track in which the wobble address information is recorded. Therefore, interference between wobble signals of adjacent tracks can be removed, and a method and a circuit for detecting a wobble address can be simplified.

Abstract: An information reproducing apparatus includes a rotating portion to rotate an information recording medium on which information has been recorded by wobbling borders on both sides of a track with different phases; a beam irradiating portion for irradiating a beam spot on the track of the information recording medium; a photodetector for receiving a reflected beam of the beam spot from the information recording medium; a detector for detecting a composite waveform including waveforms on the borders on both sides from the received beam intensity of the photodetector; a phase change detector for detecting changes in the phase of wobbling waveforms on the borders on both sides from the composite waveform; and an information reproducer for reproducing information corresponding to detection result of the phase change detector by using a predetermined relation between phase changes and information.

Abstract: An information recording device is provided. The information recording device includes an end detecting unit, a timing management unit, an encoder, and the like. In a case in which the information recording device writes data having a fixed unit length on a recording medium by dispersing and rearranging the data based on a fixed rule, the end detecting unit detects an end location of data recorded on the recording medium. The timing management unit decides a starting location on the recording medium for dispersing and rearranging data based on the end location. The encoder disperses and rearranges additional data by starting from the starting location, and writes the additional data on the recording medium continuously from the end location.

Abstract: A device for recording information on an optical disc so as to improve the recording quality of the information when a recording operation has just started. The recording device includes a luminous element radiating a light for recording information on the optical disc; a radiation intensity controller constantly controlling an intensity of radiation of the light radiated by the luminous element; a constant outputting unit providing a constant energy to the luminous element; a selector selectively selecting one of the outputs of the intensity of radiation controller and the constant outputting unit; wherein, the selector selects the output from the constant outputting unit during a predetermined duration from a starting time of recording the information on the optical disc, and selects the output from the intensity of radiation controller afterward.

Abstract: An optical disk and compatible optical disk drive enabling erasable (rewritable) optical disks to have the same format and capacity as read-only or (recordable) write-once optical disks. A reference clock track and optional additional prerecorded phase synchronization patters are provided to enable writing of any random sector with frequency and phase matching of a random sector to the preceding and following sectors. The reference clock track and other phase synchronization patterns eliminate the need for preambles and extra space for speed variation. In a first embodiment, a disk has multiple layers, with at least one rewritable data layer and at least one reference layer. A spiral track on a surface of the reference layer has prerecorded patterns to be used for clocking. In a variation of first embodiment, the reference layer is also used for radial tracking control, eliminated the need for predefined tracks in the rewritable data layers.

Abstract: The present invention relates to an apparatus and method for adjusting the reproduction speed of an optical disk, and more particularly, to a method for adjusting the reproduction speed of an optical disk which is capable of selectively adjusting the reproduction speed to a lower speed in advance only with respect to an abnormal regional section of the optical disk inserted into a driver, and normally reproducing a recording signal on the optical disk at the original high speed with respect to sections excepting for the abnormal regional section. Thus, there is an effect of reproducing data at a high speed even if the state of the optical disk is bad. In addition, a delayed reproduction time delayed can be removed by gradually reducing the reproduction speed of the optical disk.