Abstract: A proximity probe system comprising a multi-coil proximity probe including a drive coil, a sense coil and a reference coil. The system includes a signal generator driving the drive coil with an alternating current for creating a magnetic field that induces eddy currents in a proximate conductive object resulting in an eddy current induced magnetic field emanating therefrom. The sense coil is interposed between the object and the drive coil for outputting an object induced alternating current that is detected by the system and correlated to a position of the object relative to the probe. The reference coil is positioned to be inductively coupled to the drive coil for carrying a drive coil induced alternating current that is detected, conditioned and feedback to the signal generator for controlling the magnetic field radiating from the drive coil while sensing the the object induced alternating current in the sense coil.

Abstract: A magnetically variable differential transformer, comprising: a primary winding; a first secondary winding; a second secondary winding; a non-movable permeable core disposed within the primary winding, the first secondary winding and the second secondary winding; and a movable magnet configured for movement about the primary winding, the first secondary winding and the second secondary winding, wherein movement of the movable magnet causes magnetic saturation of portions of the non-movable permeable core.

Abstract: The invention relates to a magnetic passive position sensor, comprising a substrate (1) with a resistance network (2) which is arranged on this substrate (19) and is assigned a contact spring structure (8), which can be deflected under the action of a permanent magnet (11), with electrical connection between the resistance network (2) and the contact spring structure (8) being established by contact which is dependent on the position of the permanent magnet (11), the contact spring structure (8) and the resistance structure (2) being enclosed in a sealed housing (1, 12) and the permanent magnet (11) being movable outside the sealed housing (1, 12) and having flux concentration, structure associated therewith.

Abstract: An apparatus for determining the angular position of a rotating component having a plurality of angularly spaced magnetic elements is described. The apparatus includes a sensor board and a processor circuit. The sensor board is disposed adjacent to the rotating component and includes a plurality of sensor groups. Each sensor group includes a plurality of magnetic sensors positioned to sense a magnetic field of one of the angularly spaced magnetic elements. Each sensor group generates a multi-state group signal in response to the passage of one of the angularly spaced magnetic elements. The processor circuit communicates with each of the sensor groups and generates position signals in response to the multi-state group signals.

Abstract: An apparatus is disclosed for generating a magnetic field of high field strength, spatial uniformity and minimal drift of magnetic field intensity over a temperature range of about 0° C. to 175° C. This apparatus may be used in a standard modular logging tool for direct downhole NMR measurements of various parameters of fluid samples of geologic formations near the walls of a borehole. In one embodiment, the apparatus is composed of two tubular permanent magnets made of different magnetic materials with different magnetic temperature coefficients to provide temperature compensation. The apparatus preferably also utilizes a pressure barrel that surrounds the magnets and provides a return path for magnetic flux lines, thereby increasing flux density within the measurement volume.

Abstract: The invention relates to a pulse train, to a nuclear magnetic resonance scanner, which comprises means for generating this pulse train, and to an imaging method in which the pulse train according to the invention is used. The pulse train according to the invention comprises an &agr; high-frequency pulse, a preceding 180° pulse or a preceding 180° and a 90° pulse that precedes the 180° pulse, as well as a slice selection and a k-space line coding as well as an acquisition module, which is subsequent thereto for purposes of generating data. This invention is characterized in that the acquisition module for generating data results from at least two slices. By means of the pulse train and imaging method according to the invention, 20 slices of an image can be acquired at 16 different points in time for a matrix size measuring 256×256 during a measuring time of 8 minutes and 28 seconds. As a result, T1 relaxation times can be used for the first time for imaging methods in medical diagnosis.

Abstract: A phase correction method for MR devices includes collecting non-phase encoded reference data, calculating phase coefficients, and then phase correcting the regular phase-encoded image dataset based on these coefficients. The phase correction method can be used for two dimensional or three dimensional FSE imaging and variants thereof. As the method is conducted after signal acquisition, it is considered a retrospective phase correction.

Abstract: An improved high-speed spinner for solid-state NMR spectroscopy is provided. This spinner has a rotor portion comprising a radial flow type turbine that is rotated efficiently when a gas is blown at the turbine. Furthermore, stable high-speed rotation is assured. The gas blown at the turbine via gas supply holes formed in a turbine nozzle is vented rearward at a given angle to radial directions to thereby apply a rotating force to the turbine itself. The turbine has blades that are greater in number than the gas supply holes in the nozzle. The number of the blades is prime to the number of the gas supply holes.

Abstract: In a system for detecting misfire for an internal combustion engine wherein ionization current that flows following the discharge current is detected and integrated during a period (gate) and occurrence of misfire of the engine is detected based on the integrated value, a processing delay circuit is provided which inputs at least one of the discharge current or the ionization current and based on the inputted current, delays starting of the period by a time point which is not earlier than termination of the discharge current. With this, the system is unaffected by fluctuation in ignition coil discharge period, various kinds of noise and the like, and can therefore ensure accurate misfire detection by preventing erroneous detection owing to such causes.

Abstract: A battery cell voltages are read in parallel to a capacitor for each battery block of a battery pack by the use of analog switches. The stored voltages of the capacitors are A/D-converted sequentially through the analog switches. Thereby, each cell voltage is measured with suppression of measurement error by the use of the simple flying capacitor type circuit structure, while the circuit safety is secured by providing the current limitation resistor having a large resistance value between each cell and the analog switch. A noise reduction circuit having a pair of capacitors is provided.

Abstract: A method for generating a fault signal in a system voltage regulator by a phase signal includes detecting the system voltage and phase signal; comparing the system voltage and phase signal with respective fault levels; and generating a fault signal upon either the system voltage or the phase signal falling below the respective fault level of the fault levels. The fault signal generating method also inhibits generating a fault signal using a drive signal of the system voltage regulator. A diagnostic circuit for a system voltage regulator is also disclosed.

Abstract: A cable continuity test system, comprising a terminator unit electrically connected to a first side of a cable to be tested, and a test set unit electrically connected to a first side of the cable. The test set unit includes a display and further includes a microprocessor adapted for performing standard continuity tests. The test unit stores records for each site tested with a time and date stamp. The terminator unit is a programmable unit, and preferably is capable of being programmed with a unique terminator ID between the numbers of 00 and 99.

Abstract: A tester for testing multiconductor cable having a first tester is connectable to a first end of the multiconductor cable. The first tester produces one or more test signals individually on each conductor of the cable. A second tester is connectable to the second end of the cable at a remote location. The second tester monitors each of the plurality of separate conductors to detect the test signals produced by the first tester. Preferably, a first wireless transceiver is provided for the first tester that wirelessly transmits control signals to automatically coordinate testing procedure control. A second wireless transceiver joined to the second tester wirelessly transmits test result data.

Abstract: A paving material analyzer system is disclosed that uses paving material impedance to determine paving material density. The invention also includes methods for analyzing paving material, in particular, determining paving material density. The paving material density can also be used to determine a percentage of maximum compaction. A paving material analyzer system is also disclosed that determines paving material density regardless of moisture presence on the paving material or a standoff distance of a sensor to the paving material. Sensor circuits providing for improved accuracy are also provided.

Abstract: One end of an inductor is connected to a drain of a P-channel type MOS transistor. A source of source of MOS transistor is connected to an electric power source which supplies a voltage Vdd. The other end of inductor is connected via a dummy capacitor to a ground. Furthermore, a dummy resistor is connected between a drain of MOS transistor and the ground. The dummy resistor has the same resistance as that of a parasitic resistor existing between the inductor and the MOS transistor. Another dummy capacitor is connected between the dummy resistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground.

Abstract: A method and circuit for detecting a change in inductance of a variable inductance element. An oscillating signal has a frequency that varies with inductance of the element. An intermediate voltage is produced at a level that varies according to frequency of the oscillating signal. The intermediate voltage is scaled to produce an output voltage.

Abstract: A meter for measuring the root-mean-squared potential of an AC signal characterized by a frequency f is disclosed. The meter includes first and second capacitors. The AC signal is applied to the first capacitor, which includes first and second plates separated by a distance that depends on the root-mean-squared potential of the AC signal, but not on changes in the AC signal that occur over a time of 1/f. The second capacitor has first and second plates separated by a distance that depends on the separation of the first and second plates in the first capacitor. A detection circuit measures the capacitance of the second capacitor. The first plate of the first capacitor is preferably connected to the first plate of the second capacitor by a non-conducting mechanical link.

Abstract: A sensing element (2) for sensing a fluid (50) composition and a method of using the sensing element (2) are provided. The sensing element (2) includes an electrode base (36) having a first electrode (4) and a second electrode (6) disposed on the electrode base (36); the first electrode (4) and a second electrode (6) being electrically isolated one another except through an external circuitry (64); the first electrode (4) and the second electrode (6) defining a gap (42) between one another such that electrical conduction through a fluid (50) within the gap (42) is proportional to the composition of the fluid.

Abstract: A current comparator technique is applied to four-terminal resistance measurements for obtaining a highly accurate AC resistance bridge at power frequencies of 50 Hz to 60 Hz. Active circuits are used to establish equal voltage drops between the potential terminals of the two resistances being compared. The bridge is suitable for measuring resistances from 10 &mgr;&OHgr; to 100 k&mgr;&OHgr;. A cascading technique using two two-stage current transformers provides extension of the ratio range to 100,00,000 with a maximum applied current of 10,000 A. The bridge features measurement with a resolution of 0.1×10−6. The total combined uncertainty (2&sgr;) of the bridge including the range extenders, at power frequencies, is estimated to be less than 5 &mgr;&OHgr;/&OHgr;.

Abstract: A method of testing a device under test comprising providing a beam of light from a light source having a first wavelength. Imposing the beam of light on a test device over a spatial region within the test device substantially greater than the first wavelength, wherein the test device has a first state of refraction. Imposing the beam of light on the test device over a spatial region within the test device substantially greater than the first wavelength, wherein the test device has a second state of refraction. Obtaining data resulting from the interference of the first beam and the second beam within the device under test representative of the voltages within the region, wherein the first state of refraction is at a first voltage potential, and wherein the second state of refraction is at a second voltage potential different from the first voltage potential.

Abstract: In a natural state of a probe (41), a plunger (61) is distanced from a rod (62) by a spring (63), the rod (62) is held in contact with a contact element (75) by a spring (74), so that the rod (62) is connected to a common conductor of a base plate via a barrel (55). On the other hand, when an end of a wire comes into contact with an end of the plunger (61) to push it toward the rod (62), the rod (62) is distanced from the contact element (75). To be electrically disconnected from the common conductor of the base plate. Thus, all the barrels (55) and contact elements (75) of a plurality of probes (41) can be held at a specified potential only by a wiring for the signal common conductor.

Abstract: An interconnect assembly for evaluating a probe measurement network includes a base, respective inner and outer probing areas in mutually coplanar relationship on the upper face of the base, a reference junction, and a high-frequency transmission structure connecting the probing areas and the reference junction so that high-frequency signals can be uniformly transferred therebetween despite, for example, variable positioning of the device-probing ends of the network on the probing areas. A preferred method for evaluating the signal channels of the network includes connecting a reference unit to the reference junction and successively positioning each device-probing end that corresponds to a signal channel of interest on the inner probing area.

Abstract: A sample chuck for supporting sample semiconductor wafers during testing includes an upper layer formed from a semiconducting material laminated to a lower layer formed from a conducting material.

Abstract: An output terminal is provided at the middle point of each of output windings 112X and 112Y of a resolver 10. A difference between a voltage V2X (V2Y), between one of the end terminals and the middle point of the output winding, and a voltage V1X (V1Y), between the other end terminal and the middle point of the output winding, is detected by a difference voltage detection circuit 101, and supplied to a logical summing circuit 126 via a rectifier circuit 124 and a comparator circuit 125. In accordance with an output from the logical summing circuit 126, a fault of the windings, such as short-circuiting or the like, can be detected even at a specific rotation angle of the rotor. Thus, a resolver in which a fault thereof can be easily detected, as well as a resolver fault detection circuit, can be provided.

Abstract: A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.

Abstract: An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

Abstract: A microprocessor uses an interrupt signal for terminating a power-down mode, and a method thereof is used for controlling a clock signal related to the power-down mode. The microprocessor has a clock control unit for controlling whether a clock signal is outputted from a clock generator to the microprocessor, a first control unit which outputs a first control signal to the clock control unit when being level-triggered by an interrupt signal, and a second control unit which outputs a second control signal to the clock control unit for activating a power-down mode. The method includes (a) generating the second control signal to stop the clock generator from outputting the clock signal to the microprocessor, and (b) generating the interrupt signal to trigger the corresponding first control signal for terminating the power-down mode and actuating the clock generator to output the clock signal to the microprocessor after performing step (a).

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

Abstract: A programmable logic device (PLD) is disclosed that includes a state machine integrated into a block memory. The state machine includes state machine logic and memory elements from the block memory. The state machine logic and memory elements together may be used as an instruction unit of a processor. In such a case, the instruction unit is coupled to a processor execution unit to form a high-performance, embedded processor within a PLD.

Abstract: A SSTL interface voltage translator that uses dynamic biasing to translate an input signal to an output signal is provided. The voltage translator uses a first device that, dependent on a first bias signal, causes the output signal to be pulled down, where the first bias signal is dependent on the input signal. The voltage translator also uses a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.

Abstract: The present invention discloses a high voltage tolerant output buffer, which is compatible with a 5-volt input signal on its output node while operating with a 3.3-volt power supply. The high voltage tolerant output buffer includes a NAND gate, a NOR gate, a pair of pull-up transistors, a pair of pull-down transistors, a pair of enable transistors, an inhibit transistor, and a substrate bias circuit. The present invention overcomes the problems due to the degradation of gate-oxide integrity reliability and reduces the fabrication cost by minimizing the chip size.

Abstract: A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Abstract: A receiver performs on data to clock skew compensation by compensating ISI between signals, the ISI being caused by a bandwidth limitation generated in case of chip-to-chip communications in a digital system. A problem of an attenuation of a high frequency signal may occur due to an attenuation in a channel in case of a transmission of a signal at a high speed in the digital system. Therefore there is a limitation in transmitting data at a high speed. The receiver provides a circuit for applying an equalizing technology at the terminal of the receiver. And by compensating for the attenuation of a high frequency component of the signal by using the circuit, the transmission of a signal at a high speed is realized by over-sampling the signal and compensating the data to clock skew.

Abstract: Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT1, OUT2 therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT 1 and OUT 2 are combined in-phase.

Abstract: A circuit arrangement uses differential pass transistor logic, a low voltage swing and charge recycling to save power, in which the swing voltage is reduced, but the supply voltage is not reduced, thereby maintaining the transistor device current and avoiding speed degradation. SOI devices including an adder, which uses this circuit arrangement, can avoid the body effect to long pass transistor network and improve the speed at lower supply voltage.

Abstract: A differential capacitance sense amplifier capable of measuring a small difference-signal capacitance in the presence of circuit mismatches and large unequal interconnect capacitances. The sense amplifier includes three sections: a common-mode section applies a ‘read’ voltage to two capacitors in a manner that rejects unequal interconnect capacitance, a difference-mode section generates a signal proportional to the capacitance difference between the two capacitors, and an offset-canceling section compensates for circuit mismatches in the difference-mode section. The amplifier can be adapted for use as a sense amplifier for a ferroelectric differential capacitance memory unit.

Abstract: A comparator circuit includes a differential amplifier including load resistors, for amplifying difference between two input voltages of the comparator circuit; an emitter follower circuit for applying positive feedback with respect to a differential amplifier and outputting an output voltage of the comparator circuit; and a grounded-base amplifier, and outputting an output voltage of the comparator circuit, for realizing both voltage output and current output. A grounded-base amplifier includes two transistors each of which has a base supplied with a reference voltage. The differential amplifier includes two load resistors respectively connected to each emitter of the transistors of the grounded-base amplifier. The load resistor flowing a current which is obtained through a collector of the transistor as an output current of the comparator. With this arrangement, it is not necessary to provide a current switch circuit for obtaining current output of the comparator circuit.

Abstract: The present invention is to provide a multiple phases switching circuit which is operable with a multiple phase signal generator and a succeeding circuit. The multiple-phase signal generator generates N multiple-phase clock signals. Phases of the multiple-phase clock signals are different. The multiple phases switching circuit comprises an alternative signal generator and a multiplexer. The alternative signal generator outputs an alternative signal according to an up/down switching signal. The multiplexer is coupled to the alternative signal generator for receiving the multiple-phase clock signals and proceeding a glitch/spike preventing process according to the alternative signal so as to output a target clock signal to the succeeding circuit.

Abstract: A delay-locked loop includes an override controller for controlling the frequency range within which the loop operates. The override controller controls this range based on the output of a detector which compares a phase error between input and output frequency signals to a predetermined range. If the phase error lies outside this range, the controller disables a phase detector to allow the input signal delay to be adjusted based on the output of the range detector. Delay adjustments may be iteratively performed until the range detector determines that the phase error lies within the predetermined range. At this point, the override controller activates the phase detector, and the phase detector is allowed to control further delay adjustments until the phase error is eliminated or reduced, for example, to within tolerable limits.

Abstract: The invention provides an output control apparatus for adjusting the output level of a pulse width modulation (PWM) signal by changing the amplitude level of the output PWM signal. The output control apparatus comprises a control signal generator, a digital-to-analog converter (DAC), and an output circuit. The control signal generator generates a digital control signal. The DAC outputs a predetermined level according to the digital control signal. The output circuit with a negative feedback loop receives the PWM signal and receives the predetermined level by the negative feedback loop. While the PWM signal is logic number “0”, the negative feedback loop is not switched on, so as to control the level of the PWM signal at a base level. While the PWM signal is logic number “1”, the negative feedback loop is switched on, so as to control the level of the PWM signal at the predetermined level.

Abstract: A low power, high speed D type flip flop is disclosed. The D type flip flop uses four inverters and four transmission gates to store and output the data states. The flip flop comprises two memory elements wherein each memory element is made up of a transmission gate and two inverters. Each of the four inverters contained in the flip flop is referred to as a bypass current limiting inverter. Each of the four inverters contains biasing circuitry to limit current flow and thereby save power. Additionally, each inverter has switching circuitry that enables the current limiting features to be automatically and advantageously bypassed thereby allowing for large currents and fast response times whilst simultaneously retaining the low power performance.

Abstract: A negative voltage switch for use in flash memory. The switch has a control end and two voltage output ends, and includes two inverting units for transferring a positive voltage, two driving units for transferring a negative voltage, and two negative voltage pass-gate transistors for respectively transferring the negative voltage to the voltage outputs. Each inverting unit connects to a driving unit at a corresponding node, and each negative voltage pass-gate transistor connects to one of the nodes. According to a voltage at the control end, the switch turns on one inverting unit to transfer the positive voltage at the corresponding node, and the driving unit connected to the other node turns on to transfer the negative voltage to the corresponding negative voltage pass-gate transistor such that the negative voltage pass-gate transistor stops outputting the negative voltage at the other voltage output.

Abstract: A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

Abstract: A switched-capacitor integrator eliminates noise caused by the switching of an input signal. For this purpose, the integrator includes a switched-capacitor unit for providing a capacitor with one of a first and a second input voltage in response to clock signals, a reference voltage providing unit for receiving a reference voltage and outputting an amplified reference voltage, a switching noise eliminating unit for maintaining an output of the reference voltage providing unit at a stabilized voltage level, an operational amplifying unit for receiving an output of the switched-capacitor unit as its negative input and the output of the reference voltage providing unit passed through the switching noise eliminating unit as its positive input and a feedback capacitor for feeding back an output of the operational amplifying unit to the negative input.

Abstract: An exemplary compensation circuit includes: a temperature compensation circuit which provides as an output a temperature compensation signal indicative of temperature variations; a supply compensation circuit which provides as an output a supply compensation signal indicative of supply voltage variations; and a compensation conversion circuit coupled to the temperature compensation circuit and the supply compensation circuit to provide as an output a bias signal from the temperature compensation signal and the supply compensation signal. The supply compensation circuit includes a voltage divider circuit coupled to a supply compensation node, to a source voltage, and to a sink voltage, where the supply compensation node is coupled to an input of the compensation conversion circuit. The source voltage provides a supply voltage, and the supply compensation signal is indicative of variations in the supply voltage.

Abstract: A latch includes an inverter; a pass transistor having a first terminal coupled to an input of the inverter and a second terminal coupled to a programming voltage; a first capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a first predetermined voltage; and a second capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a second predetermined voltage; wherein each of the first and second capacitors uses an antifuse.

Abstract: A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

Abstract: Different reference voltages are employed in different logical electrical circuits. In the conventional arts, a reference voltage circuit is only employed in a specific logical electrical circuit or a reference voltage circuit with fuse can changes a reference voltage by fusing the fuse. Nevertheless, the reference voltage circuit with fuse is still only employed in a specific system of logical circuit regardless of the fuse is fused or unfused. A select reference voltage circuit for a logical electrical system of the present invention can solve the problem. Therefore, the select reference voltage method for a logical electrical system can be employed in different systems having respective different system voltages.

Abstract: In a negative voltage output charge pump circuit, first a capacitor C1 is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C1 is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C1 is made to conduct to an output terminal OUT so that the voltage with which the capacitor C1 is charged is output as a negative voltage −Vin. Here, at least one of the switching device DP1 that is kept on while the capacitor C1 is being charged so as to apply the reference voltage to the point B and the switching device DP2 that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.