Patents Issued in November 9, 2004
  • Patent number: 6815203
    Abstract: The invention features methods of promoting dedifferentiation of pancreatic cells, methods of obtaining pancreatic islet cells from the dedifferentiated pancreatic cells, and methods of treating a subject having a disorder characterized by insufficient pancreatic islet function by administering pancreatic islet cells obtained by these methods.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: November 9, 2004
    Assignee: Joslin Diabetes Center, Inc.
    Inventors: Susan Bonner-Weir, Monica Taneja
  • Patent number: 6815204
    Abstract: The invention relates to a method of improving the transfer in an annular biological reaction chamber defined by coaxial inner and outer walls (11, 12) and in which there flows a liquid reaction medium containing a culture of microorganisms or of cells from vegetable or animal macroorganisms in suspension. At least one of the walls is an exchange wall enabling gaseous or liquid matter to be transferred or allowing light to pass through. The reaction medium is subjected to a turbulent primary flow that is helical and that under the action of centrifugal force creates rotary secondary vortices so as to encourage renewal of the culture in the vicinity of the exchange wall.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 9, 2004
    Assignee: Institut Francais de Recherche pour l'Exploitation de la Mer (IFREMER)
    Inventors: Arnaud Muller-Feuga, Jack Legrand, Jérémy Pruvost, Patrick Legentilhomme, Roland Leguedes
  • Patent number: 6815205
    Abstract: The present invention provides compounds and compositions capable of stimulating plant growth, regeneration of plant cells and tissues, and transformation of plant cells and tissues, comprising mono- and multi-substituted auxinic analogues of indole-3-acetic acid (IAA) comprising substituent groups such as halo-, alkyl-, alkoxy-, acyl-, acylamido- and acyloxy-groups. The invention relates to a method of using such mono- and multi-substituted auxinic analogues of IAA to affect growth, regeneration or transformation in monocotyledonous and dicotyledonous plants, as well as in transgenic plant tissues. The invention also contemplates the use of these auxinic IAA analogues in the presence of other plant growth regulators, such as cytokinin, etc., to enhance plant growth.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: November 9, 2004
    Assignee: Invitrogen Corporation
    Inventors: Jhy-Jhu Lin, Jianqing Lan, Nacyra Assad-Garcia
  • Patent number: 6815206
    Abstract: A sterilization system uses a sterilization process monitoring device which is capable of indicating the efficacy of the sterilization process. To enhance accuracy of the monitoring function, the monitoring device is located in such a fashion that an antimicrobial agent used in the process can only reach the monitor through an area containing the article to be sterilized.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: November 9, 2004
    Assignee: Ethicon, Inc.
    Inventors: Szu-Min Lin, Su-Syin Wu
  • Patent number: 6815207
    Abstract: A method of detecting moisture or wetness which enables determination as to whether or not precision instruments or industrial products have undergone improper conditions, is described, which comprises: (i) use of a composite material which contains at least one water-soluble decoloring agent and at least one methine dye whose color disappears upon reaction with the decoloring agent in a state that the decoloring agent and the dye are spatially isolated from each other, and (ii) detection of a history of contact with moisture or water by disappearance of color from the composite material.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: November 9, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Yoshiharu Yabuki, Akio Ishizuka
  • Patent number: 6815208
    Abstract: A method of treating hydrotest water to inhibits oxygen corrosion, microbiologically influenced corrosion (MIC) and to allow safe discharge of water. The combination treatment plan reduces biocide usage in a high pH brine. The reduced overall chemical usage facilitates meeting environmental guidelines while also minimizing chemical cost. The method includes: adding an oxygen scavenger to remove oxygen and prevent or minimize oxygen corrosion; raising the hydrotest water pH, typically in excess of pH 9.5; adding a biocide in reduced amount; and adding a scale inhibitor to inhibit scale.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: November 9, 2004
    Assignee: Champion Technologies, Inc.
    Inventor: Rupi Prasad
  • Patent number: 6815209
    Abstract: A method of determining laser parameters for lysing cells involves exposing cells from a sub-sample of a sample to laser light. At least one parameter of the laser is varied, and damage to intracellular molecules of sub-samples of the sample at such varied parameters is measured. At least one parameter is determined based on the measured damage. In one embodiment, the laser parameters comprise power, wavelength and duration. A microchannel system provides a transport mechanism for cells to be lysed. The microchannel system is combined with a laser to lyse cells while they are being transported. The laser is disposed within a trench to expose the cells in the channels in one embodiment. In still further embodiments, the laser is integrated into a semiconductor substrate in which the channels are formed.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: November 9, 2004
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Antje J. Baeummer, Mohit D. Dhawan
  • Patent number: 6815210
    Abstract: An assay for the determination of protein in an aqueous test fluid which combines the test fluid with a buffer and a dye. The buffer is selected from citrulline, malonic acid, cyanoacetic acid, citraconic acid, methyl phosphonic acid, sarcosine, saccharin, or combinations thereof. The buffer is added in sufficient quantity to maintain the pH of the assay including the test fluid at a selected target pH range within a range of from about 2.0 to about 3.0. The dye has a pKa which enables it to operate as a protein indicator at the target pH range. The dye also has affinity for protein such that it will provide a detectable response in the presence of greater than about 15 mg/dL protein to thereby render the assay suitable for the detection of total protein in the test fluid. The buffer and dye may be absorbed in a test strip of absorbent material.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: November 9, 2004
    Assignee: Bayer Healthcare LLC
    Inventors: James A. Profitt, Alexander H. Orn, Jennifer Farr
  • Patent number: 6815211
    Abstract: Apparatus or systems which employ luminescence quenching to produce an oxygen concentration indicative signal. Components of such systems include: (1) an airway adapter, sampling cell, or the like having a sensor which is excited into luminescence with the luminescence decaying in a manner reflecting the concentration of oxygen in gases flowing through the airway adapter or other flow device; (2) a transducer which has a light source for exciting a luminescable composition in the sensor into luminescence and a light sensitive detector for converting energy emitted from the luminescing composition as that composition is quenched into an electrical signal indicative of oxygen concentration in the gases being monitored; and (3) subsystems for maintaining the sensor temperature constant and for processing the signal generated by the light sensitive detector. Sensors for systems of the character just described, methods of fabricating those sensors, and methods for installing the sensors in the flow device.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: November 9, 2004
    Assignee: NTC Technology
    Inventors: Perry R. Blazewicz, Leslie E. Mace, Jerry R. Apperson, Gamal-Eddin Khalil
  • Patent number: 6815212
    Abstract: Methods are provided for detecting the binding of a first member to a second member of a ligand pair, comprising the steps of (a) combining a set of first tagged members with a biological sample which may contain one or more second members, under conditions, and for a time sufficient to permit binding of a first member to a second member, wherein said tag is correlative with a particular first member and detectable by non-fluorescent spectrometry, or potentiometry, (b) separating bound first and second members from unbound members, (c) cleaving the tag from the tagged first member, and (d) detecting the tag by non-fluorescent spectrometry, or potentiometry, and therefrom detecting the binding of the first member to the second member.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: November 9, 2004
    Assignee: Qiagen Genomics, Inc.
    Inventors: Jeffrey Van Ness, John C. Tabone, J. Jeffry Howbert, John T. Mulligan
  • Patent number: 6815213
    Abstract: The invention concerns a method for analyzing a sample of a complex molecule relatively to a reference batch of the same complex molecule. Said method is characterized in that it consists in breaking up the complex molecule into at least two molecular sub-entities; in determining, on the basis of the atomic sites of said products of the breakup involved in the breakup reactions, the isotope(s) to be analyzed; and in establishing, for at least part of the breakup products, their isotopic profile; and in comparing the isotopic profile of the products of the breakup with the isotopic profile of the raw material(s) previously indexed and/or with the isotopic profile of the reference complex molecule subjected to the same breakup reactions. The invention is useful for detecting counterfeiting in manufacturing processes.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: November 9, 2004
    Assignee: Eurofins Scientific
    Inventors: Gerard Martin, Gilles Martin
  • Patent number: 6815214
    Abstract: The synthesis of novel diketopiperazines, their use in inhibiting cellular events such as those involving NFK-&agr;, NFK-&bgr; and in the treatment of inflammation events, a combinatorial library of diverse diketopiperazines and process for their synthesis as a library and as individual compounds. In particular novel diketopiperazines are disclosed including their synthesis and use in cellular events such as activation of the transcription factor, nuclear factor, TNF-&agr;, TNF-&bgr; and also apoptosis.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 9, 2004
    Assignee: Celltech R & D, Inc.
    Inventors: Jim P. Boyce, J. Jeffry Howbert, John C. Tabone
  • Patent number: 6815215
    Abstract: The present invention absorbs and captures nucleic components from various specimens by a single stationary phase and finally recovers the nucleic components by eluting the captured nucleic components from the stationary phase. This invention enables recovery of nucleic components without reducing the concentrations of nucleic acids and detection of specific nucleic components such as specific viruses.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Igarashi, Toshinari Sakurai, Toshiaki Yokobayashi
  • Patent number: 6815216
    Abstract: The invention relates to a method for solid-phase microextraction and analysis of substances in a carrier fluid, in which a collector is brought into contact with the stirred fluid containing the substances for a sufficient time and is then subjected to a solid-phase extraction directed at at least one substance adhering to the collector, and desorbed substances are transported for analysis by means of a carrier gas, in which the carrier fluid containing the substances is stirred in a receptacle of a magnetic stirrer by means of a coated magnetic stirring element as the collector, and/or the carrier fluid is made to move intimately relative to the collector by means of ultrasound, and then the stirring element is placed in a solid-phase extraction device.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: November 9, 2004
    Assignee: Gerstel Systemtechnik GmbH & Co. KG
    Inventors: Patrick Sandra, Erik Baltussen, Frank David
  • Patent number: 6815217
    Abstract: A solid phase with at least one test area is described which contains reagents for the detection of at least one analyte in a sample, wherein the solid phase additionally comprises at least one control area for the detection of interfering reactions.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: November 9, 2004
    Assignee: Roche Diagnostics GmbH
    Inventors: Johann Karl, Helmut Lenz, Friedemann Krause, Peter Finckh, Hans Hornauer, Johann Berger
  • Patent number: 6815218
    Abstract: Bioelectronic components are formed using nanoparticles surrounded by attached shells of at least one biological material. The nanoparticles are deposited (e.g., using a printing process) onto a surface, and by associating the deposited nanoparticles with one or more electrical contacts, electrical measurement across the nanoparticles (and, consequently, across the biological material) may be made. A finished component may include multiple layers formed by nanoparticle deposition.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: November 9, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Joseph M. Jacobson, Scott Manalis, Brent Ridley
  • Patent number: 6815219
    Abstract: A method for fabricating a non-volatile memory device. The method includes providing a substrate, e.g., silicon. The method also includes forming an oxide layer overlying the substrate; and forming a buffer layer overlying the oxide layer. A ferroelectric material is formed overlying the substrate and is formed preferably overlying the buffer layer. The method also includes forming a gate layer overlying the ferroelectric material, where the gate layer is overlying a channel region. The method further includes forming first source/drain region adjacent to a first side of the channel region and a second source/drain region adjacent to a second side of the channel region. In other embodiments, the method can also include other steps.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: November 9, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hong Koo Kim
  • Patent number: 6815220
    Abstract: A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: November 9, 2004
    Assignee: Intel Corporation
    Inventors: Ankur Mohan Crawford, Donald S. Gardner
  • Patent number: 6815221
    Abstract: A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Cha-young Yoo, Doo-sup Hwang, Jae-hyun Joo, Eun-ae Chung, Yong-kuk Jeong
  • Patent number: 6815222
    Abstract: Disclosed is a method for production of a semiconductor device having capacitive elements. The method includes steps of covering an insulating film formed on a substrate sequentially with a lower electrode film, a dielectric film, and an upper electrode film; applying a photoresist to the top of the films in laminate structure by photolithography, thereby forming a photoresist pattern to form an upper electrode; performing selective etching on the upper electrode film by using the photoresist pattern to form the upper electrode as a mask, thereby forming the upper electrode pattern; covering the upper electrode pattern with a photoresist pattern to form a dielectric pattern; and performing selective etching on the dielectric film by using the photoresist pattern to form the dielectric as a mask, thereby forming the dielectric pattern. The above-mentioned production method prevents a short circuit between the upper electrode and the lower electrode when the capacitive element is formed.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri
  • Patent number: 6815223
    Abstract: A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: November 9, 2004
    Assignee: Symetrix Corporation
    Inventors: Jolanta Celinska, Vikram Joshi, Narayan Solayappan, Myoungho Lim, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6815224
    Abstract: In a method for producing ferroelectric strontium bismuth tantalate having the composition SrxBiyTa2O9 (SBT) or SrxBiy(Ta, Nb)2O9 (SBTN), the element strontium, which is normally present in an amount y=2, is provided in excess in a range from 2.1≦y≦3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T1, which is lower than 700° C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Harald Bachhofer, Thomas Haneder, Oswald Spindler, Rainer Waser
  • Patent number: 6815225
    Abstract: In the method for forming a capacitor of a nonvolatile semiconductor memory device, a TaON glue layer is formed over a semiconductor substrate, and a lower electrode is formed on the TaON glue layer. A ferroelectric film is then formed on the lower electrode, and an upper electrode is formed on the ferroelectric film.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: November 9, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam Kyeong Kim, Ki Seon Park, Dong Su Park, Byoung Kwon Ahn, Seung Kyu Han
  • Patent number: 6815226
    Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Kyu-Mann Lee, Yong-Tak Lee, Hyeong-Geun An
  • Patent number: 6815227
    Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Geun An
  • Patent number: 6815228
    Abstract: A standard pattern of a differential value of an interference light is set with respect to a predetermined film thickness of a first member to be processed. The standard pattern uses a wavelength as a parameter. Then, an intensity of an interference light of a second member to be processed, composed just like the first member, is measured with respect to each of a plurality of wavelengths so as to obtain a real pattern of an differential value of the measured interference light intensity. The real pattern also uses a wavelength as a parameter. Then, the film thickness of the second member is obtained according to the standard pattern and the real pattern of the differential value.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tatehito Usui, Takashi Fujii, Motohiko Yoshigai, Tetsunori Kaji
  • Patent number: 6815229
    Abstract: A system and method for analyzing sheet resistivity of a layer on a wafer employing electrical methods and for controlling rapid thermal annealing (RTA) of the layer is provided. The system includes components for performing RTA on the layer and components for analyzing the sheet resistivity of one or more portions of the layer upon which RTA was performed. The system further includes a feedback generator adapted to accept sheet resistivity data and to produce feedback information that can be used to control the RTA components. The system further includes a data store that can be employed in machine learning and/or to facilitate generating feedback information that can be employed to control RTA and a monitoring application that can be employed to schedule maintenance on the various components in the system.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: November 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arvind Halliyal, Ramkumar Subramanian, Bhanwar Singh
  • Patent number: 6815230
    Abstract: A method and a device are disclosed for transmitting a control signal to an option pad of an integrated circuit chip at its package level. The method includes the steps of: electrically isolating one of a plurality of commonly connected power transmitting pins of the integrated circuit package; connecting the electrically isolated power transmitting pin to the option pad to thereby transmit a control signal from outside through the electrically isolated power transmitting pin to the option pad.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Dae Park, Uk-Rae Cho
  • Patent number: 6815231
    Abstract: A simple and easy method for exercising quality control over memory cell inter-layer dielectric film within a short period of time, using a memory array or single memory formed in the scribe area, without stressing nonvolatile semiconductor memory cells and a method of manufacturing a nonvolatile semiconductor memory device; whereby a single nonvolatile memory is formed in an area other than a chip area on a semiconductor wafer and used after completion of a wafer manufacturing process to perform an inter-layer dielectric film quality control process for evaluating the write saturation characteristic, cut out nondefective chips only, and conduct a plastic molding process, achieving an increased yield after chip cutting.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Akemi Miura, Hitoshi Kume, Toshiaki Nishimoto
  • Patent number: 6815232
    Abstract: A method includes measuring a first overlay error between a first process layer and a second process layer using a first overlay target formed on the second process layer. A second overlay error between the first process layer and a third process layer is measured using a second overlay target formed on the third process layer. At least one parameter of an operating recipe for performing a photolithography process on the first process layer is determined based on the first and second overlay error measurements. A system includes a metrology tool and a controller. The metrology tool is configured to measure a first overlay error between a first process layer and a second process layer using a first overlay target formed on the second process layer and measure a second overlay error between the first process layer and a third process layer using a second overlay target formed on the third process layer.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: November 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gary K Jones, Christopher A Bode, Richard D Edwards
  • Patent number: 6815233
    Abstract: A system for processing tester information is provided. Data is collected for a plurality of dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data are graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: November 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey P. Erhardt, Shivananda S. Shetty
  • Patent number: 6815234
    Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Uwe Wellhausen, Stefan Gernhardt, Rainer Bruchhaus, Andreás Hilliger, Jing Yu Lian, Nicolas Nagel
  • Patent number: 6815235
    Abstract: The present invention is generally directed to various methods of controlling the formation of metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a feature, performing at least one anneal process to convert a portion of the layer of refractory metal to at least one metal silicide region on the feature, and measuring at least one characteristic of at least one metal silicide region while the anneal process is being performed. In another illustrative embodiment, the method comprises forming a layer of refractory metal above a feature, performing at least one anneal process to convert a portion of the layer of refractory metal to at least one metal silicide region on the feature, and performing at least one scatterometric measurement of the metal silicide region after at least a portion of the anneal process is performed to determine at least one characteristic of the metal silicide region.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: November 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard J. Markle
  • Patent number: 6815236
    Abstract: A method of measuring a concentration of a material includes irradiating an infrared light onto a substrate having a layer including a first material and dopants, wherein the infrared light is partially absorbed by and partially transmitted through the substrate including the layer. Intensities of the infrared light absorbed in the first material and the dopants are computed according to light wave numbers by utilizing a difference between intensities of the infrared light before and after transmitting the substrate and layer and by utilizing a difference between intensities of the infrared light absorbed in the substrate and layer and absorbed in only the substrate. Concentrations of the dopants are obtained by utilizing a ratio of light wave number regions corresponding to predetermined intensities of infrared light absorbed in the dopants relative to light wave number regions corresponding to the predetermined intensity of infrared light absorbed in the first material.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Kyoung Kim, Sun-Yong Choi, Chung-Sam Jun, Kwang-Soo Kim, Koung-Su Shin, Jeong-Hyun Choi, Dong-Chun Lee
  • Patent number: 6815237
    Abstract: A testing apparatus for determining the etch bias associated with a semiconductor-processing step includes a substrate, a first cathode finger with a first width on the substrate, a second cathode finger with a second width on the substrate, and a cathode large area on the substrate wherein the cathode large area has a third width W″ and a length L″ that are both substantially larger than either of the first and second widths.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: November 9, 2004
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: James Chingwei Li, Richard L. Pierson, Jr., Berinder P. S. Brar
  • Patent number: 6815238
    Abstract: A method of manufacturing a field emission device. In the method, emitters are formed using a lift-off process, and an isolation layer is formed between a sacrificial layer for patterning the emitters and emitter materials. The isolation layer prevents the sacrificial layer from reacting on the emitter materials to facilitate the lift-off process. Thus, the field emission device, which uniformly emits light having a high brightness, can be obtained.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: November 9, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jeong-hee Lee, Hang-woo Lee, Shang-hyeun Park, You-jong Kim
  • Patent number: 6815239
    Abstract: Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. These five methods accommodate the fabrication of an optical interference multilayer, which improves the image quality of the reflected light. These five methods are: Silicon Dioxide Posts by Wet Etching. Amorphous Silicon Posts by Plasma Etching. Silicon Nitride Posts by Plug Filling. Insulation Material Posts by Lift-off. Polyimide Posts by Photosensitive Etching.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sik On Kong, Rajan Rajgopal, George Wong
  • Patent number: 6815240
    Abstract: Substrates suitable to manufacture and products of a thin film semiconductor device are provide, by at first preparing a manufacturing substrate having a characteristic of being capable of enduring a process for forming a thin film transistor and a product substrate having a characteristic of being suitable to direct mounting of the thin film transistor in a preparatory step, then applying a bonding step to bond the manufacturing substrate to the product substrate for supporting the product substrate at the back, successively applying a formation step to form at least a thin film transistor to the surface of the product substrate in a state reinforced with the manufacturing substrate and, finally, applying a separation step to separate the manufacturing substrate after use from the product substrate.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventor: Hisao Hayashi
  • Patent number: 6815241
    Abstract: Included in the invention are laminates having layers of group III-V materials having low dislocation densities, semiconductor devices fabricated using low dislocation density group III-V layers, and methods for making these structures. Some of the inventions are concerned with GaN layers, GaN semiconductor devices, and semiconductor lasers fabricated from GaN materials. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: November 9, 2004
    Assignee: Cao Group, Inc.
    Inventor: Tao Wang
  • Patent number: 6815242
    Abstract: The present invention relates to a semiconductor device with quantum dots and a method of manufacturing the same, and a structure of the semiconductor device which can control an emission wavelength of the quantum dots and a method of manufacturing the same are provided. The semiconductor device comprises a compound semiconductor substrate containing at least three elements, and quantum dots which are formed on the compound semiconductor substrate and whose emission wavelength is adjusted by the lattice constant of the compound semiconductor substrate.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: November 9, 2004
    Assignee: Fujitsu Limited
    Inventors: Kohki Mukai, Hiroshi Ishikawa
  • Patent number: 6815243
    Abstract: A method for fabricating MEMS structure includes etching a recess in an upper surface of a substrate that is bonded to a wafer that ultimately forms the MEMS structure. Accordingly, once the etching processes of the wafer are completed, the recess facilitates the release of an internal movable structure within the fabricated MEMS structure without the use of a separate sacrificial material.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: November 9, 2004
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Mark A. Lucak, Richard D. Harris, Michael J. Knieser, Robert J. Kretschmann
  • Patent number: 6815244
    Abstract: A method produces a thermoelectric layer structure on a substrate and the thermoelectric layer structure has at least one electrically anisotropically conductive V-VI layer, in particular a (Bi, Sb)2 (Te, Se)3 layer. The V-VI layer is formed by use of a seed layer or by a structure formed in the substrate, and disposed relative to the substrate such that an angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. The orientation can also be effected by an electric field. Components are formed of the thermoelectric layer structure in which the angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. As a result, the known anisotropy of the V-VI materials can advantageously be used for the construction of components.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Harald Böttner, Axel Schubert, Joachim Nurnus, Christa Künzel
  • Patent number: 6815245
    Abstract: According to this invention, silicon-based photodetectors using waveguides formed with silicide regions can have high speed and high efficiency for near IR applications. Utilizing the unique properties of suicides, the proposed method provides a simple and elegant way to implement a photodetector design in which photogenerated carriers travel perpendicular to the direction of light propagation. Therefore, the speed and quantum efficiency of the photodetector may be optimized independently. This device configuration may be implemented in one of the two approaches: (a) waveguides formed through surface silicidation of a silicon-based layer of a substrate (b) waveguides formed through silicidation of ridge waveguide side-walls of a silicon-based layer of a substrate; The use of mature silicon technology promises low cost of production and other benefits.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: November 9, 2004
    Assignee: National Research Council of Canada
    Inventors: Dan-Xia Xu, Siegfried Janz
  • Patent number: 6815246
    Abstract: In the manufacture of a wafer-type silicon solar cell having on its front side a silicon nitride AR coating and an electrical contact that is formed by printing a thick film metal ink onto the silicon nitride in the form of a grid-like pattern having narrow fingers and then firing that ink to convert it to a bonded metal contact, a surface treatment method is provided to adjust the condition of the surface of the silicon nitride coating in a manner that substantially improves the adherence of the thick film ink to the silicon nitride coating, thereby eliminating or substantially inhibiting the tendency of the narrow fingers of the unfired ink to peel away before the ink has been fired to produce the electrical contact. The surface treatment method comprises subjecting the silicon nitride layer to a corona discharge using a plasma jet and is readily incorporated into the manufacturing process sequence without requiring any modification of existing stages of that sequence.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 9, 2004
    Assignee: RWE Schott Solar Inc.
    Inventors: Ronald C. Gonsiorawski, Grace Xavier
  • Patent number: 6815247
    Abstract: A thin-film opto-electronic device on a conductive silicon-containing substrate includes a sequence of layers. The layers include a layer of a porous medium preferably a porous silicon, on a substrate. The porous layer has both light diffusing and light reflecting properties. In addition, a non-porous layer is located on said porous silicon layer, with at least one first region and at least one second region being in said non-porous layer. The first region is of a first conductivity type acting as a light absorber and the second region has a conductivity of a second type, different from said first conductivity type. The sequence of layers is such that optical confinement is realised in the device.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: November 9, 2004
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Lieven Stalmans, Jef Poortmans, Matty Caymax, Khalid Said, Johan Nijs
  • Patent number: 6815248
    Abstract: A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN, The use of the material WN improves etch process selectivity during the manufacturing process.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Rainer Leuschner, George Stojakovic, Xian J. Ning
  • Patent number: 6815249
    Abstract: A surface-mount device has a substrate, a pair of electrodes, each of which comprises an upper electrode and a lower electrode. A pair of grooves are formed in opposite sides of the substrate. The upper electrode and the lower electrode are connected by a connecting layer formed on an inside wall of each of the grooves. An LED is mounted on one of the electrodes, and a lid is provided in an upper portion of each of the grooves. A protector layer is formed on the substrate to seal the upper electrode, LED and lids.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: November 9, 2004
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Tsuyoshi Miura
  • Patent number: 6815250
    Abstract: A method for manufacturing an infrared detector forms a p-n junction by forming a low concentration p type HgCdTe layer, forming a diffusion preventing layer for exposing some upper part of the low concentration p type HgCdTe layer, and by forming a low concentration n type HgCdTe layer by diffusing hydrogen ions and atoms to the low concentration p type HgCdTe layer using hydrogen plasma. The hydrogen ions or atoms are diffused on some of the low concentration p type HgCdTe layer to be a predetermined depth using the hydrogen plasma to form the low concentration n type HgCdTe layer in order to prevent an interface of the p-n junction from damaging, and thereby leakage current can be prevented, fabrication cost is not increased and yield is increased due to simple processes.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: November 9, 2004
    Assignee: Agency for Defense Development
    Inventors: Hee Chul Lee, Ki Dong Yang
  • Patent number: 6815251
    Abstract: A high density multi-chip module and method for construction thereof, wherein a plurality of integrated circuit dice with at least one row of generally central bond pads is bonded in a staggered flip-chip style to opposite sides of a metallized substrate. The bond pads of each die are positioned over a through-hole in the substrate, and the bond pads are wire-bonded from one side of the substrate to circuitry on the opposing side of the substrate. Application of a glob-top sealant into the through-holes seals the bond pads and bond wires. A ball grid array may be formed in the peripheral area surrounding the dice on one side of the substrate, or an edge connector may be incorporated for connection to an external circuit.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: November 9, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Jerry M. Brooks
  • Patent number: 6815252
    Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: November 9, 2004
    Assignee: ChipPAC, Inc.
    Inventor: Rajendra D. Pendse