Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: A chip package having an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another. Such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggering in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

Abstract: A semiconductor device assembly package includes a semiconductor device having components thereon which are generic to a variety of applications by manipulation of the pinout configuration. The lead frame includes redundant leads for connection to the semiconductor device, as desired. The semiconductor device may include redundant wire bond pads, each redundant pair including one pad on a lateral edge and one pad on a non-lateral edge of the die. In applications requiring less than all of the available leads, the pinout configuration of the leadframe is adjusted to use the extra space from unused NC leads and missing pins for providing wider, shorter leads with reduced inductance, and wider paddle arms for reduced bending and breakage.

Abstract: The present invention comprises a first main face (22a) on the surface side of a substrate (21a). An island portion (26) is formed on the first main face (22a) and a semiconductor chip (29), etc. are adhered onto the first main face (22a). The semiconductor chip (29), etc. are sealed in a hollow space made by a column portion (23) and a transparent glass plate (36). Then, the column portion (23) and the glass plate (36) are adhered by the light-shielding adhesive resin made of epoxy resin. Accordingly, there can be provided the semiconductor device and a method of manufacturing the same, which can prevent the direct incidence of the light onto the semiconductor chip (29) and the degradation of the characteristic of the semiconductor chip (29) can be suppressed.

Abstract: The electronic device (10) comprises an integrated circuit (30) with a first (18) and a second side (19), on both sides (18, 19) of which first and second conductive areas (31, 32) are present. The electronic device (10) further has a first (64) and a second (65) conductive structure, which (64, 65) are present on a—preferably enveloping—layer (71) of dielectric material. Signal and power to and from the integrated circuit (30) are transferred through capacitors (11, 12) formed by the conductive areas (31, 32) and the conductive structures (64, 65) and an intermediate layer (73, 74) of dielectric material. The integrated circuit (30) may contain a protective layer (33) in the second conductive area (32).

Abstract: A high-frequency semiconductor device is provided with a ceramic substrate, an element group including semiconductor elements and passive components mounted onto a bottom portion of the ceramic substrate, and a composite resin material layer formed on the bottom portion of the ceramic substrate so as to bury the element group. The composite resin material layer is formed by a composite resin material including an epoxy resin and an inorganic filler material, and has a flat bottom surface on which electrodes for connecting to the outside are formed. As packaging of a structure in which the receiving system and the transmitting system are formed in a single unit, such as an RF module, the high-frequency semiconductor device achieves a small size, a high mounting density, and excellent heat release properties.

Abstract: A semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an arrangement that avoids areas overlapping positions of the wires.

Abstract: A packaged circuit with VDDcore contacts in first positions and VSScore contacts in second positions. A redistribution layer is adjacent the integrated circuit, and overlies VDDcore and VSScore mesh layers. First contacts in the redistribution layer are positioned in alignment with the first positions, to make connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second positions, to make connections between the redistribution layer and the VSScore contacts. First vias are positioned in alignment with the first positions, to make connections between the first contacts and the VDD mesh layer. The traces of the VDD mesh layer are positioned in alignment with the first positions. Second vias are positioned in alignment with the second positions to make connections between the second contacts and the VSS mesh layer. The traces of the VSS mesh layer are positioned in alignment with the second positions.

Abstract: A system and method are provided for thermal dissipation from a heat producing electronic device. The system includes a substrate for fabricating integrated circuits, the substrate having a first face and a second face. The second face is disposed substantially parallel to the first face having an electronic device disposed therein. A metallized crack stop is disposed in the first face surrounding the electronic device. A plurality of first metal conduits extend through the substrate from the second face thereof to the crack stop, wherein each first metal conduit is in thermal contact with the crack stop to provide a thermal drain from the electronic device to the second face.

Abstract: An objective of the present invention is to provide a thermoelectric module which can achieve high heat release and heat absorption efficiencies and which can obviate any thermal stress-caused damages. A thermoelectric module (1) in an embodiment has a predetermined number of thermoelectric semiconductor elements P and N which are arranged in a flat plate configuration. Each of the thermoelectric semiconductor elements P and N has on one face thereof a one-side electrode (2) and has on the other face thereof an other-side electrode (3), thereby allowing all of the thermoelectric semiconductor elements P and N to be connected in series. The one-side electrodes (2, 2 . . . ) have heat release/heat absorption fins (heat transfer fins) (2F, 2F . . . ) and the other-side electrodes (3, 3 . . . ) have heat release/heat absorption fins (heat transfer fins) (3F, 3F . . . ).

Abstract: The semiconductor device comprises an insulating film in which penetrating holes are formed, a semiconductor chip having electrodes, a wiring pattern adhered by an adhesive over a region including penetrating holes on one side of the insulating film and electrically connected to the electrodes of the semiconductor chip, and external electrodes provided on the wiring pattern through the penetrating holes and projecting from the surface opposite to the surface of the substrate on which the wiring pattern is formed. Part of the adhesive is drawn in to be interposed between the penetrating holes and external electrodes.

Abstract: A camouflaged interconnection for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity to type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.

Abstract: A method and apparatus are provided for attaching a semiconductor device to a substrate. One end of the substrate is elevated to position the substrate and the coupled semiconductor device on an inclined plane. An underfill material is introduced along a wall of the semiconductor device located at the elevated end of the inclined substrate with the underfill material being placed between the substrate and the semiconductor device. An optional but preferred additional step of the invention includes coupling a barrier means to the substrate at a point on the substrate adjacent to a sidewall of the semiconductor device located at the lowest point of the slope created by the inclined substrate. The barrier means prevents the underfill material from spreading beyond the sidewalls of the semiconductor device, particularly in instances where the substrate is inclined at a steep angle.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: A method of deoxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing to remove oxygen molecules from the surface to which adherence of the refractory metal. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Abstract: A seal ring structure having an electrostatic discharge protection function, suitable for a conductive first-type substrate which has a bias provided by a second power source. The new seal ring scheme including a conductive second-type doped diffusion region located on the first-type substrate; and a metal conductive structure, comprising at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.

Abstract: Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract: The present invention relates to a semiconductor device in which a barrier insulating film is formed to cover a copper film or a wiring consisting mainly of the copper film. The barrier insulating film is a structure of two or more layers including at least a first barrier insulating film containing silicon, oxygen, nitrogen and hydrogen or silicon, oxygen, nitrogen, hydrogen and carbon, and a second barrier insulating film containing silicon, oxygen and hydrogen or silicon, oxygen, hydrogen and carbon.

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: Electrical connection between two faces of a substrate and manufacturing process. The connection is made by a part (46) of a conducting or semi conducting substrate (20) completely surrounded by at least one electrically insulating trench (32, 36, 44). A contact pad (42) is located on the back face (40) and conducting tracks (38) are located on the front face. The connection is made through the substrate itself. Application to the manufacture of circuits, components, sensors, etc.

Abstract: An integrated circuit device includes a thin semiconductor layer disposed on a surface of a wafer, a plurality of wafer-scale integrated (WSI) circuits formed on the semiconductor layer, and a node formed on the semiconductor layer that provides an optoelectronic interface to an axial optical data bus for high-speed optical interconnectivity between the WSI circuits and other external devices interconnected to the optical data bus.

Abstract: In a semiconductor device having a structure in which a semiconductor chip is bonded to a surface of a solid device (a semiconductor chip, a wiring substrate or the like), the semiconductor device is thinned. A primary chip 31 and a secondary chip 32 are bonded together with the active surfaces thereof being opposed to each other to form a chip-on-chip structure. The primary chip 31 has bumps BE for outer connection on the outer side of the secondary chip 32. The bumps BE are connected to a surface of an interposed substrate 33. In the inner region of the interposed substrate 33, a through hole 40 for containing the secondary chip 32 is provided. A heat radiating plate 45 is bonded to the inert surface of the primary chip 31. The primary chip 31 and the secondary chip 32 can be well heat-radiated.

Abstract: A method of manufacturing a semiconductor device, including a first step of placing a resin between one surface of a semiconductor chip, having a plurality of electrodes formed thereon, and a substrate having a wiring pattern formed thereon and defining at least one through-hole in the region in which the semiconductor chip is to be mounted on the substrate, to form a space therebetween that opens into the through-hole, and a second step of pressing either one of the semiconductor chip and the substrate against the other to thereby bond the semiconductor chip to the substrate.

Abstract: A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.

Abstract: A semiconductor device having first and second semiconductor chips opposed and connected, at respective active surfaces, to each other. The first semiconductor chip has a first internal connection electrode and a first lateral-deviation confirming electrode. The second semiconductor chip has a second internal connection electrode and a second lateral-deviation confirming electrode.

Abstract: A flip chip package mainly comprises a chip, a leadless lead frame. The leadless lead frame has a die paddle and a plurality of leads. The active surface of the chip has a plurality of bonding pads formed thereon. Besides, a plurality of bumps formed on the bonding pads are electrically connected to the chip, the leads and the die paddle. Therein, the die paddle electrically connected to the chip via the bumps not only prevents the chip from being dislocated but also provides another grounding and heat transmission paths to enhance the electrical, thermal and mechanical performance of the flip chip package. Similarly, the bumps formed on the bonding pads of the chip are electrically connected to the leads so as to fix the chip to the lead frame more securely.

Abstract: An electronic component includes an electronic element and a substrate to which the electronic element is mounted, the electronic element and the substrate being electrically or mechanically connected to each other by at least three bumps. Both the value obtained by dividing the total bonding-area of the bumps bonded to the electronic element by the mass of the electronic element and the value obtained by dividing the total bonding-area of the bumps bonded to the substrate by the mass of the electronic element are at least about 8.8 mm2/g.

Abstract: An adhesive system and a method of adhesion for a ball grid array semi-conductor device package facilitate the encapsulation of a die attached to a circuit board. A material is added between a die and a circuit board tape, and is oriented perpendicular to a conventional two-piece rape system used to attach the die to the circuit board. The material, which is located across from a gate through which an encapsulation compound is injected to form a package, acts as a diversion dam. The material thereby enables the injected encapsulation compound to fill a wirebond slot last and avoid an overflow which might otherwise damage the ball grid array.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater.

Abstract: A laser alignment target is provided having a surface that is out of plane with and has substantially the same first reflectivity as an adjacent surface of the semiconductor device, and a sidewall having a second reflectivity different than the first reflectivity. The target provides sidewalls that provide contrast for finding the target despite loss of contrast created by layers of dielectric over the target and use of short wavelength light.

Abstract: The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and the probability of soft errors is lowered.

Abstract: A system for generating electric power comprises an electrically driven air compression unit (10), a high-pressure storage tank (14) and a hydraulic system. The hydraulic system comprises a fluid reservoir (20), a pneumatically driven fluid pump (18) and a hydraulic motor (26), having a drive shaft (28) rotatably coupled to an electric generator (8). Initially a high-speed compression unit (10) is operated by an outside electric source. The air is compressed into the high-pressure storage tank (14) and controllably released into the pneumatically driven fluid pump (18), causing its operation. Hydraulic fluid being pressured from the fluid reservoir (20) into the hydraulic motor (26) causes the rotation of the motor drive shaft (28) and the electric generator (8). Electric power is generated. The outside electric source is removed. Part of the generated power is used to operate the compression unit (10) the other part of the power is used by a load.

Abstract: A fuse arrangement for use in a vehicle is provided having a configuration wherein a common bus terminal connected to a voltage supply is connected to terminals of one or more axial fuses. The other fuse terminals are, in turn, connected to a wiring harness that is located on an opposite side of the fuse box from the common bus terminal in a base of a fuse box. Additionally, the present invention includes a fuse array including a planar substrate with fuses constructed on the substrate by film metallization. Furthermore, the invention includes a carrier strip used for packaging automotive fuses that is made of a flexible material capable of being rolled into a package for shipping to an end user. The invention also includes a mini fuse having reduced terminal spacing for use in vehicles with mixed voltage systems wherein the reduced terminal spacing fuse is used for a particular voltage.

Abstract: A control circuit for driving a plurality of electrical loads, one at a time, has a converter circuit for receiving a DMX compatible digital control signal and extracting a plurality of address bits therefrom. A decoder circuit receives the digital address bits and generates a plurality of enable signals, each corresponding to a particular load. One of the load enable signals is in an active state and each other enable signal is in an inactive state at any one time. A relay circuit for receives the enable signals, and in response passes an electrical drive signal to the electrical load corresponding to the enable signal that is in the active state. The relay circuit preferably includes a plurality of relay devices each coupled to one of the enable signals and a plurality of discharge circuits for rapidly discharging each electrical load when the enable signal corresponding to that load changes from the active state to the inactive state.

Abstract: A power supply device with n power supply units comprises main power supplies generating DC voltage supplies VDC1 to VDCn supplied to a load, respectively, unit side control sections each informing a main control section of the result of abnormality monitoring of each section, and control power supplies supplying DC voltage supplies VB1 to VBn to the unit side control sections, respectively. For example, the unit side control section is parallel connected to the control power supply units of other power supply units in addition to the control power supply.

Abstract: The invention relates to a circuit for supplying power to a network termination unit (55) of a message transmission system, which is connected to a central station via a subscriber line (30). A local power supply voltage source (41), which is arranged in the network termination unit (55) and which supplies power during a normal operating state, is provided as well as a remote power supply source, which is arranged in the central station and which supplies power during an emergency operating state in the case of a failure or malfunctioning of the local power supply voltage source (41). The network termination unit (55) comprises a direct current converter with a transformer and a clocked switch (20). The primary winding (1) of the transformer is connected via the clocked switch (20) to the local power supply voltage source (41), and a connection of the primary winding (1) is connected via a first controllable switch (5) to a wire of the subscriber line (30).

Abstract: The present invention is directed to a circuit for reversing the polarity of a high voltage power supply. Circuits according to embodiments of the invention may include four switches, one or more of which may be solid-state switches. The solid-state switches may include a transistor stack that is supplied a biasing voltage in response to the receipt or removal of a control signal. When the biasing voltage is supplied to one transistor in the stack to change it to the closed or “ON” state, the other transistors in the stack may also be changed to the closed state in a cascading process. The control signal may be a low voltage signal and may be isolated from the solid-state switch by a control switch, which may be an optocoupler.

Abstract: Disclosed is a linear voice coil actuator having a latching feature, the actuator having a coil assembly, a field assembly, a magnetic structure positioned in the coil assembly, and a stop which limits the position of the magnetic structure with respect to the field assembly when the coil is not energized. The coil assembly has a coil base and a coil located in a cavity in the coil base. The field assembly preferably has an axially magnetized cylindrical magnet, a soft pole piece, and a soft magnetic housing. Preferably the magnetic structure is a magnetic plate positioned coaxially with the axis of magnetization of the magnet and having a diameter or a thickness which is selected to set a latching force between the plate and the magnet when the coil is not energized.

Abstract: An electric linear motor for driving a reciprocating load includes a stator, a coil, an armature and a commutation circuit. The stator has a magnetically permeable core with an air gap. The coil is wound around a portion of the stator and energized with a non-constant voltage for producing a non-constant magnetic flux in the stator and the air gap. The armature supports a permanent magnet having a substantial portion located in the air gap. The interaction of the magnetic field of the magnet and the non-constant flux in the air gap produces a force on the armature. The armature is connected to the load and reciprocates with respect to the stator. The circuit controls the coil such that at least one end of the magnet passes outside the region of substantially uniform flux density within the air gap during a portion of the motion of the armature.

Abstract: An electrical machine has a stator, a rotor, and radially extending coolant passageways provided in a laminated core section of at least the stator. The coolant passageways are defined between axially spaced stacks of laminations in the laminated core section. The radial passageways are connected to coolant supply ducts through a gap between the stator and the rotor. More efficient cooling of the machine is obtained by providing a matrix of coolant duct sections extending circumferentially and axially of the core section. The matrix has first and second radially spaced apart faces respectively in fluid communication with the radially extending coolant passageways in the laminated core section and coolant exhaust ducts.

Abstract: A magneto generator including: a magnet rotor having a cup-shaped rotor yoke formed with a plurality of air vents in a bottom wall and a permanent magnet secured to an inner periphery of a peripheral wall of the rotor yoke; and an armature having an armature coil, wherein a cooling air introducing portion is provided for each of the plurality of air vents, a cooling air introducing passage for introducing cooling air into a corresponding air vent is formed inside the cooling air introducing portion, the cooling air introducing passage has a rectangular section, and opens in a sloping direction with respect to the direction orthogonal to a plane including both a straight line between the center of the bottom wall and the center of the air vent, and a central axis of the magnet rotor.

Abstract: A spindle design for a hard disk drive assembly constructed in accordance with the present invention includes a significantly large gap between the rotating, ferromagnetic hub with its permanent magnet rotor and the rotating sleeve of the fluid bearing journal member. The large gap may be filled with a medium, such as air, or a non-permeable material. The large gap is preferably on the order of several hundred microns. Because of the large gap, the magnetic flux leakage from the rotating hub members and sleeve into the stationary shaft at the center of the spindle is negligible. Consequently, iron loss in the shaft caused by magnetic flux leakage into the shaft is reduced to acceptable noise levels.

Abstract: A motor which includes a core having two or more coiled teeth; a base to which the core is secured; and a terminal assembly secured to the base. The terminal assembly has lands for attaching coil ends, and is secured to the base by welding. This terminal assembly is configured by assembling at least next three components: an upper terminal holder which is an insulator; a terminal which is a conductor; and a lower terminal holder which is an insulator.

Abstract: An optical disk drive motor includes a rotor and a disk tray. At least one adjusting member is provided between the rotor and the disk tray. The adjusting member is adjustable to adjust a pressing force exerted on one of the rotor and the disk tray, thereby keeping the rotor and the disk tray in a parallel relationship.

Abstract: A stator core 1 is surrounded by a first insulating member 40 and a second insulating member 41. Locking protrusions 9 are formed on the outer periphery of the stator core 1, and the locking protrusions 9 form a keyway 11. A modular connector 2 includes a key part 21 that fits within the keyway 11 to secure the modular connector 2 to the stator core 1. Fastening pins 18 are embedded in the modular connector 2 to conduct electricity from a mating connector 91 and a lead line 93 to the resolver.

Abstract: A spindle motor for use in a disk drive having a base frame, a housing cover, a fixed shaft and a rotatable bearing sleeve. The fixed shaft has a larger diameter section and a smaller diameter section with a step formed therebetween. The rotatable bearing sleeve has a central cylindrical opening, the shaft being inserted into the central cylindrical opening. A bearing gap is formed between the fixed shaft and the rotatable bearing sleeve, the bearing gap being filled with lubricating fluid. One end of the fixed shaft is secured to the base frame while another end of the shaft is secured to the housing cover.