Abstract: A programmable resistance memory element including a pore of memory material which is raised above a semiconductor substrate by a dielectric layer. The pore may be formed with the use of sidewall spacers.

Abstract: An optical sensor is provided, comprising (a) a silicon nanowire of finite length having an electrical contact pad at each end thereof; and (b) a plurality of self-assembled molecules on a surface of the silicon nanowire, the molecules serving to modulate electrical conductivity of the silicon nanowire by either a reversible change in dipole moment of the molecules or by a reversible molecule-assisted electron/energy transfer from the molecules onto the silicon nanowire. Further, a method of making the optical sensor is provided. The concept of molecular self-assembly is applied in attaching functional molecules onto silicon nanowire surfaces, and the requirement of molecule modification (hydroxy group in molecules) is minimal from the point view of synthetic difficulty and compatibility. Self-assembly will produce well-ordered ultra-thin films with strong chemical bonding on a surface that cannot be easily achieved by other conventional methods.

Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

Abstract: An optic superconducting circuit element (10) is disclosed that is operable to transmit and receive on an identical chip an electromagnetic wave having frequencies in an extended frequency band ranging from microwave to THz frequency bands and with high sensitivity. The optic superconducting circuit element (10) includes the chip (3), and a superconducting electromagnetic wave oscillating (generating and transmitting) source (16) and a superconducting Josephson junction device (14) disposed in close vicinity to each other on the chip (3), the superconducting Josephson junction device (14) detecting the electromagnetic wave transmitted from the superconducting electromagnetic wave oscillating (generating and transmitting) source (16).

Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Abstract: An active matrix organic electroluminescence unit which is easy to manufacture. The organic electroluminescence unit comprises an organic material layer formed on a surface of the electrode panel, a dielectric layer formed near the organic material layer on the surface of the electrode panel, a metal electrode formed continuous to the surfaces of the organic material layer and the dielectric layer, and having a portion corresponding to the organic material layer functioning as a control electrode, and an organic electroluminescence element formed on the organic material layer.

Abstract: An organic field-effect transistor comprises source and drain electrodes formed separately from each other on a substrate, wherein the substrate comprises at least an organic semiconductor layer constituting a channel between the source and drain electrodes, an insulation layer underlying the organic semiconductor layer, and a gate electrode formed on the opposite side of the isolation layer. The organic semiconductor layer comprises hole and electron transporters, wherein the electron transporters comprise (6,6)-phenyl C61-butyric acid methyl ester (PCBM), and wherein the hole transporters comprise poly(2-methoxy-5-(3′,7′-dimethyloctyloxy)-1,4-phenylene-vinylene)(OC1C10-PPV) and/or poly(3-hexylthiophene) (P3HT).

Abstract: A matched set of integrated circuit chips (24) and a method for assembling such integrated circuit chips (24) into a matched set are disclosed. A semiconductor wafer (18) having a plurality of integrated circuit chips (24) is electrically and mechanically coupled to a wafer interposer (12) to form a wafer-interposer assembly (10). The integrated circuit chips (24) of the wafer (18) are then tested together by attaching the wafer-interposer assembly (10) to a testing apparatus and running the integrated circuit chips (24) through various testing sequences. The wafer-interposer assembly (10) is then diced into a plurality of chip assemblies each having a chip (24) and a section of the wafer interposer (12). Based upon the testing, the chip assemblies are sorted and at least two of the chip assemblies are selected for inclusion in the matched set.

Abstract: A process via mismatch detecting device is disclosed. Because the vias in the detecting circuit of process via mismatch detecting device are mismatched while the vias between the metal layers of the chips are mismatched, by appropriately placing vias in detecting circuit of process via mismatch detecting device properly, metal lines of different metal layers in the detecting circuit can become short-circuited by mismatched vias, so as to output a voltage signal that is higher after vias mismatch and is regarded as the result of detecting via mismatch. Therefore, the direction and quantity of via mismatch between the metal layers in the chip are detected and monitored effectively, so as to optimize the process. Thus, the yield of process is increased and the cost is decreased.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.

Abstract: A storage capacitor structure comprising a first capacitor electrode on a substrate, a capacitor dielectric layer on the first capacitor electrode and a second capacitor electrode on the capacitor dielectric layer, a passivation layer on the second capacitor electrode and a pixel electrode layer on the passivation layer. The second capacitor electrode has an area smaller than the first capacitor electrode. The passivation layer has an opening that exposes a portion of the second capacitor electrode. The pixel electrode layer and the second capacitor electrode are electrically connected through the opening in the passivation layer.

Abstract: The invention concerns an active TFT matrix for optical sensor comprising a substrate, a TFT transistor matrix formed on said substrate, a set of transistor control lines (3): a conductor level (4) according to a specific pattern forming an electrode array (5), each electrode (5) defining a zone called pixel: a set of columns (10) for load transfer between the electrodes (5) and an external electronics. The pixel electrode (5) is located entirely inside an outline delimited by two lines (3) and two successive columns (10), a protective gap (g1, g2) being provided between the inside edge of said outline and the periphery of the pixel (5) such that the pixel electrode (5) does not cover either the lines (3) or the columns (10).

Abstract: To a polycrystalline silicon layer crystallized by irradiation with laser light, a mixed gas comprised of ozone gas and H2O or N2O gas is fed at a processing temperature of 500° C. or below, or the polycrystalline silicon layer is previously treated with a solution such as ozone water or an aqueous NH3/hydrogen peroxide solution, followed by oxidation treatment with ozone, to form a silicon oxide layer with a thickness of 4 nm or more at the surface of the polycrystalline silicon layer for forming a thin-film transistor having characteristics that are less varying on a glass substrate previously not annealed.

Abstract: A TFT is provided completely separated by an insulating film, in which a parasitic MOSFET is not generated at ends of a semiconductor layer, and the variation in characteristics is small. At least one portion of the ends in the gate-width direction of a gate electrode forming the TFT is disposed in a semiconductor region which forms the TFT, and the ends in the gate-length direction of the gate electrode extend toward the outside of the semiconductor region forming the TFT. With this arrangement, a uniform TFT in which a parasitic MOSFET is not generated at the ends in the gate-width direction is obtainable.

Abstract: A field effect transistor includes an n+ high-density impurity injection area, a p+ high-density impurity injection area, an i-impurity non-injection area, and a gate electrode. The gate electrode is free from completely lapping over the i-impurity non-injection area, but laps over substantially half the i-impurity non-injection area adjacent to the n+ high-density impurity injection area so as to avoid channel carrier capture levels due to crystal defects/grain boundaries and an effect of potential barriers due to the channel carrier capture levels.

Abstract: A method of making a substrate having a buried structure includes the steps of preparing a glass substrate having a principal surface, forming a groove on the principal surface of the glass substrate by a wet etching process, and depositing a first material over the principal surface of the glass substrate and filling the groove with the first material to form the buried structure having a surface that is substantially flush with the principal surface. The step of forming the groove includes the step of performing the wet etching process by using an etchant that includes hydrofluoric acid, ammonium fluoride, and hydrochloric acid or oxalic acid.

Abstract: A diamond semiconductor has an exciton light-emission intensity characteristic that varies nonlinearly.

Abstract: A light-emitting device with reduced lattice mismatch. The light-emitting device comprises a substrate having a first lattice constant, a first buffer multilayer deposited on the substrate, a second buffer multilayer deposited on the first buffer multilayer, and a GaN base epitaxial layer deposited on the second buffer multilayer. The lattice constant of the first buffer multilayer ranges from the first lattice constant at the bottom of the first buffer multilayer to a second lattice constant at the top of the first buffer multilayer. The lattice constant of the second buffer multilayer ranges from the second lattice constant at the bottom of the second buffer multilayer to a third lattice constant at the top of the second buffer multilayer.

Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.

Abstract: A light source that utilizes light emitting diodes that emit white light is disclosed. The diodes are mounted on an elongate member having at least two surfaces upon which the light emitting diodes are mounted. The elongate member is thermally conductive and is utilized to cool the light emitting diodes. In the illustrative embodiment, the elongate member is a tubular member through which a heat transfer medium flows. A cooling or fluid movement device coupled with the elongate thermally conductive member enhances cooling of the light emitting diodes.

Abstract: There are provided a semiconductor light emitting device wherein the variation in tone in each device is small and the variation in tone due to deterioration with age is also small, and a method for manufacturing the same. The semiconductor light emitting device includes an active layer for emitting primary light having a first wavelength by current injection, and a light emitting layer excited by the primary light for emitting secondary light having a second wavelength different from said first wavelength, wherein the primary light and the secondary light are mixed to be outputted.

Abstract: A semiconductor device includes: a crystalline substrate including a primary surface and a crystal plane provided within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface; a semiconductor layered structure grown over the crystalline substrate; and an active region provided at a portion in the semiconductor layer structure above the crystal plane.

Abstract: A resonant cavity type light emitting diode has a first DBR made of n-type AlAs or Al0.5Ga0.5As, a quantum well active layer, a second DBR made of p-type (Al0.2Ga0.6)0.5In0.5P or Al0.5In0.5P, and an n-type current constriction layer on an n-type GaAs substrate. The first DBR and the second DBR form a resonator. The quantum well active layer is formed in a position of an antinode of a standing wave inside the resonator. Between the second DBR and the current constriction layer, there is provided a p-type GaP etching protection layer that has a value obtained by dividing resistivity by thickness being 1×103 &OHgr; or more. Since a current in a current flow pass formed in the current constriction layer hardly diffuses to the outside of the current flow pass, there is generated few region with low current density that causes deterioration of responsespeed in a quantum well layer. Thus, the light emitting diode has an excellent high-speed response.

Abstract: A light-emitting device has a light-emitting layer of nitride semiconductor containing As, P or Sb and accordingly its emission efficiency or emission intensity is enhanced. The light-emitting device includes a substrate, and further includes n-type and p-type nitride semiconductor layers and a light-emitting layer between the n-type and p-type semiconductor layers that are formed on the substrate. Light-emitting layer includes one or a plurality of well layers formed of nitride semiconductor containing N and element X (element X is As, P or Sb). The nitride semiconductor of the well layer has at most 30% in atomic percent represented by expression {NX/(NN+NX)}×100 where NX represents the number of atoms of element X and NN represents the number of atoms of N. The thickness of the well layer ranges from 0.4 nm to 4.8 nm.

Abstract: An electro-optical device preferably includes a printed circuit board (PCB) having a cutout region or a rigid region. A leadframe having an electro-optical semiconductor device arranged thereon can be arranged in proximity to the cutout region of the PCB. Alternatively, the electro-optical device can be arranged on the rigid region of the PCB. A lens is preferably arranged over the electro-optical semiconductor device. A connector array can also be arranged on the PCB to communicate electrical signals with an external device. An interface circuit, such as a driver circuit or an amplifier circuit, can also be arranged in close proximity to the electro-optical semiconductor devices on the leadframe or the PCB.

Abstract: A nitride-based semiconductor light-emitting device includes a GaN-based substrate and a semiconductor stacked-layer structure including a plurality of nitride-based semiconductor layers grown on the GaN-based substrate by vapor deposition. The GaN-based substrate has an interface region contacting the semiconductor stacked-layer structure and the interface region contains oxygen atoms of concentration n in the range of 2×1016≦n≦1022 cm−3.

Abstract: A light emitting semiconductor device, which includes a Ga0.9In0.1As0.97 active layer disposed between lower n-Ga0.5In0.5P and upper p-Ga0.5In0.5P cladding layers, being provided with lower and upper GaAs spacing layers each intermediate the active layer and the cladding layer. The active layer is approximately lattice-matched to a GaAs substrate and has a thickness of about 0.1 &mgr;m with a photoluminescence peak wavelength of approximately 1.3 &mgr;m, and the GaAs spacing layers each have a thickness of about 2 nm.

Abstract: A silicon controlled rectifier, which has a substrate and an overlying epitaxial layer that is formed on the substrate, is formed in the epitaxial layer to have a number of semiconductor regions with alternating dopant conductivity types where a number of the regions extend through the epitaxial layer to the substrate.

Abstract: The switching element has a switching layer between a first electrode layer and a second electrode layer. The switching layer includes a charge transfer complex containing an electron donor and an electron acceptor. An insulating layer is provided between the first electrode layer and the switching layer, and contacts the switching layer. The switching layer switches from a high-resistance state to a low-resistance state upon application of a voltage greater than a first threshold value in a first bias direction. Thereafter, the switching layer maintains the low-resistance state when the applied voltage decreases beyond the first threshold value. When the applied voltage becomes not smaller than a second threshold value in a second bias direction or a reverse direction to the first bias direction, the switching layer switches from the low-resistance state to the high-resistance state.

Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g. in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate.

Abstract: A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1−xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1−xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.

Abstract: Isoelectronic co-doping of semiconductor compounds and alloys with deep acceptors and deep donors is used to decrease bandgap, to increase concentration of the dopant constituents in the resulting alloys, and to increase carrier mobilities lifetimes. Group III-V compounds and alloys, such as GaAs and GaP, are isoelectronically co-doped with, for example, N and Bi, to customize solar cells, thermal voltaic cells, light emitting diodes, photodetectors, and lasers on GaP, InP, GaAs, Ge, and Si substrates. Isoelectronically co-doped Group II-VI compounds and alloys are also included.

Abstract: A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

Abstract: A method is disclosed for fabricating multifaceted, tensilely strained Si MOSFET (FinFET) devices. The method comprises the growing by selective epitaxy of a monocrystalline Si strip onto a monocrystalline SiGe layer sidewall surface, where the SiGe layer is bonded to a support platform, typically an insulator on a Si substrate, and where the Si strip also bonds to the support platform. The SiGe sidewall surface has a lattice constant which is larger than the relaxed lattice constant of Si, whereby the Si strip is in a tensilely strained state. Upon removing the SiGe monocrystalline layer the monocrystalline strained Si strip is turned into a multifaceted Si strip on the support platform, suitable for fabricating multifaceted gate FinFETs. Fabrication of processors with such FinFet devices is also disclosed.

Abstract: A phased-array antenna system and other types of radio frequency (RF) devices and systems using microelectromechanical switches (“MEMS”) and low-temperature co-fired ceramic (“LTCC”) technology and a method of fabricating such phased-array antenna system and other types of radio frequency (RF) devices are disclosed. Each antenna or other type of device includes at least two multilayer ceramic modules and a MEMS device fabricated on one of the modules. Once fabrication of the MEMS device is completed, the two ceramic modules are bonded together, hermetically sealing the MEMS device, as well as allowing electrical connections between all device layers. The bottom ceramic module has also cavities at the backside for mounting integrated circuits. The internal layers are formed using conducting, resistive and high-k dielectric pastes available in standard LTCC fabrication and low-loss dielectric LTCC tape materials.

Abstract: A FET or BJT structure or distributed transistor amplifier having a tapered gate feed line and a tapered channel width (tapered source fingers, tapered drain fingers) provides increased bandwidth and gain in the microwave/mm-wave frequency spectrum.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: One or more deep-array implants under the photosensitive region of a semiconductor substrate are conducted to improve optical cross-talk between pixel cells. According to an embodiment of the present invention, one or more deep-array implants of a first conductivity type are used to dope predefined regions of a well of a second conductivity type. This way, first conductivity type dopants from the one or more deep-array implants counterdope second conductivity type dopants from the predefined regions of the well. The dosage and energy of each deep-array implant may be optimized so that the collection of signal carriers by the photosensitive region and the photoresponse for different wavelengths are maximized.

Abstract: A microelectronic device is designed such that it includes a region between electrodes having a switchable ohmic resistance wherein the region is made of a substance comprising components Ax, By, and oxygen Oz. The ohmic resistance in the region is reversibly switchable between different states by applying different voltage pulses. The different voltage pulses lead to the respective different states. An appropriate amount of dopant(s) in the substance improves the switching, whereby the microelectronic device becomes controllable and reliable.

Abstract: When a tunnel magnetoresistive effect element having a multilayer film structure containing two ferromagnetic material layers (11, 12) and a barrier layer (13) is constructed, after one ferromagnetic material layer (11) had been deposited, a conductive layer (16), formed by adding a material of an element different from a metal material to said metal material serving as a principal component thereof, is deposited on the ferromagnetic material layer (11) and the barrier layer (13) is formed by oxidizing the conductive layer (16), whereafter the other ferromagnetic material layer (12) is deposited on the barrier layer (13). Thus, in the tunnel magnetoresistive effect type memory device, dispersion of resistance value between respective elements can be suppressed while a large TMR ratio can be obtained.

Abstract: The present invention provides a small-sized and inexpensive semiconductor device wherein a synchronous dynamic random access memory and a flash memory are built in a single encapsulater. A flash memory chip and a synchronous dynamic random access memory chip (SDRAM chip) are fixed to a main surface of a wiring board in a parallel state, and another SDRAM chip is fixed onto the flash memory chip. Electrodes for the respective semiconductor chips are respectively exposed and these electrodes are connected to their corresponding electrodes of the wiring board. An encapsulater formed of an insulating resin is formed on the main surface side of the wiring board so as to cover wires. Since the encapsulater is formed by cutting a block encapsulater formed by block molding by dicing, the side faces of the encapsulater result in cut surfaces. Bump electrodes are provided on the back surface of the wiring board in an array fashion.

Abstract: A conductive film forming a capacitor lower electrode has portions extending perpendicularly to the main surface of a semiconductor substrate and a portion extending in parallel with the main surface of the semiconductor substrate. An insulator film forming a capacitor dielectric film is provided along the surface of a recess portion defined by the conductive film. Another conductive film forming a capacitor upper electrode is embedded in a recess portion of the insulator film. The conductive film and a wiring layer are formed on the same layer, so that the wiring layer functions as a dummy pattern of a capacitor having the conductive films. Consequently, a semiconductor device having a capacitor capable of increasing the electrostatic capacitance and reducing the quantity of the material forming the dummy pattern without occupying a large area in the direction parallel to the main surface of the semiconductor substrate is obtained.

Abstract: The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

Abstract: In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.

Abstract: A field effect transistor (FET) has a channel formed in a pore extending up from a conductive portion of a substrate through a stack of planar layers including a first insulating layer, a gate layer, and a second insulating layer. The pore can be upright or inclined relative to the layers. A nanoparticle used for a mask of a directional etching process ultimately defines the size of the pore and therefore the channel width. The substrate or a doped region of the substrate formed immediately beneath the channel can be a source/drain of the FET with the other drain/source being a doped region adjacent the top of the channel. The gate layer can form the gate or can contact a separate gate inside the pore.

Abstract: Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

Abstract: A semiconductor memory device including 1T-1C memory cells for increasing an access speed thereto. The semiconductor memory device is composed of a substrate, a MOS (metal oxide semiconductor) transistor formed in a surface portion of the substrate, an inter-level dielectric covering the MOS transistor, a capacitor element, and a contact formed through the inter-level dielectric. The contact electrically connects the capacitor element to the MOS transistor on a source thereof. The contact includes a metal portion formed of metal. The metal portion reduces the resistance of the contact, and thereby increases the access speed of the semiconductor memory device.

Abstract: A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls of an insulative material having an opening therein, forming sidewalls of conductive hemispherical grained material on the metal silicide material, and forming a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material.

Abstract: A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown of the high dielectric constant material. The combination of high dielectric constant material in a memory cell along with a relatively large surface area conductive structure is achieved through the use of a buffer material as caps on the thin edge surfaces of the relatively large surface area conductive structures to dampen or eliminate the intense electric field which would be generated at the corners of the structures during the operation of the memory cell capacitor had the caps not been present.