Abstract: A proportional brake light system having an LED display carried on a motor vehicle and capable of instantaneously warning motorists following from behind whether and how quickly the vehicle is likely to stop in response to an operator generated foot pressure being applied to the brake pedal shoe. The brake pedal shoe of the vehicle has a hollow interior, and an optical signal is transmitted along an optical transmission path extending therethrough. As the pressure applied by the operator to the brake pedal shoe is increased, more of the optical signal being transmitted along the optical transmission path is interrupted. A multi-stage comparator is responsive to an interruption of the optical signal so as to cause a corresponding number of LEDs from the display to be illuminated.

Abstract: A vehicle light can include a light source, a major reflecting surface, a projection lens, and a shutter. A first reflecting surface of an ellipse group reflecting surface preferably has a first focus on the light source and a second focus, capable of being inserted in or removed from an optical path from the light source to a second fixed reflecting surface. A first fixed reflecting surface of a parabolic group reflecting surface can include a focus on the second focus of the first reflecting surface, and at least two second reflecting surface elements. The second fixed reflecting surface can include a first focus on the light source and at least two third reflecting surface elements for reflecting light rays that have traveled an optical path from the light source thereto without being reflected by the first reflecting surface.

Abstract: Headlight for motor vehicles, comprising at least one light source and at least one light guide associated with each light source, into which the light emitted by the light source can be coupled via a light coupling surface, wherein each light guide is associated with a light terminator body into which the light from the light guide is passed, wherein the light terminator body has a light output surface and the output light can be imaged through a downstream lens, wherein the at least one light terminator body is fixed on or to a holder and the holder can be pivoted about at least one axis and/or be displaced in at least one plane relative to the at least one lens.

Abstract: I realized that our society pays more and more attention to safety. Therefore, I decided to follow this trend by focusing specifically on safety of driving. The most important aspect of driving is being able to stop or apply brakes. However, if other drivers are unaware we are in the process of doing that, or if they do not pay enough attention, our safety is at risk. Having said all that, our reaction is based on what we see. On the road, we know that a vehicle in front of us is applying brakes when the red light comes on. However, that red light can be easily missed or confused with other lights on a vehicle. Why did we come up with an idea of pulsating signal lights but the same suggestion was not made for brake lights? Imagine yourself driving behind a vehicle when suddenly its red braking lights are starting to flash. Instantly, you react and your awareness is awaken. As an added benefit pulsating lights are more visible in any type of weather or driving conditions.

Abstract: An LED light, such as used as a vehicle backup light, includes an LED board having first and second sides. At least one LED is mounted on the first side. A lens is positioned at a distance from the LED board to face the first side of the LED board. A potting compound is provided on the second side of the LED board. The potting compound can completely fill the second side of the LED board. The lens can include a first surface facing an external side of the LED light that is substantially smooth, to prevent collecting dust therein, and a second surface facing the LED board. That second surface can be contoured to include an upper region to refract light in a first direction, a lower region to reflect light in a second direction opposite to the first direction, and a middle region including horizontal grooves. That middle region may diverge light in a horizontal direction and converge light in a vertical direction.

Abstract: An illumination apparatus for illumination of light by emitting light from LED for each of RGB colors capable of optionally setting a color temperature and controlling the brightness after the setting while maintaining the color temperature as it is, in which a light control circuit supplies a light control voltage for variably controlling the light quantity of the illumination light equally to each color setting circuit connected with LED of each color which is lit by a light quantity in proportion with a driving current and a color temperature setter of the color temperature setting circuit adjusts the light control voltage by a predetermined ratio to a control voltage, and a constant current circuit outputs a driving current in accordance with the control voltage to each LED for each of RGB colors.

Abstract: The backlight for a flat display device including a light source, a light guide plate and a surface hologram is provided. The light guide plate is installed at one side of the light source, and light from the light source travels in the light guide plate while being totally reflected. The surface hologram is formed on at least one surface of the light guide plate. The surface hologram has a pattern of a predetermined grating interval and a predetermined grating depth in order to diffract light at a predetermined angle toward the light guide plate.

Abstract: A compact, high-efficiency, high-power, solid state light source, comprising a high-power solid state light-emitting device, a light guide having a proximal light-receiving end proximate the light-emitting device and a distal light-transmitting end spaced farther from the light-emitting device, and a mechanical light guide fixing device coupled to the light guide near its proximal end, to hold the proximal end of the light guide in position near the light-emitting device.

Abstract: The invention relates to optical filters comprising an opacified portion. The optical filters are preferably suitable for use in illuminators for weathering devices.

Abstract: The invention relates to a method for controlling a VSC-converter provided with a resonant circuit (16).

Abstract: A voltage sense circuit and power supply regulation technique. In one aspect, a voltage sense circuit utilized in a power supply regulator includes a transformer including a sense winding and an output winding. A first diode is coupled to the sense winding, a first resistor is coupled to the first diode and a first capacitor coupled to the first resistor and the first diode. A second diode coupled to the first capacitor, the first resistor and the first diode. A second capacitor coupled to the second diode such that a voltage across the second capacitor is representative of a voltage across the output winding.

Abstract: A non-isolated bridge-buck DC-DC converter has self-driven synchronous rectifiers Q5 Q6 in the buck circuits 28 30. Gate electrodes of the synchronous rectifiers Q5 Q6 are connected to midpoints 24A 24B of the bridge circuit. The voltage at the midpoints provides the necessary voltage waveform for switching the synchronous rectifiers Q5 Q6. In another aspect of the invention, voltage shift circuits 34 are provided between the midpoints and the gates of the synchronous rectifiers. The voltage shift circuits are necessary in some embodiments to make sure that the synchronous rectifiers are turned completely OFF when necessary. The present invention provides a more power efficient and less expensive technique for controlling the synchronous rectifiers compared to conventional external driver circuitry.

Abstract: An energy transfer element having an energy transfer element input winding, an energy transfer element output winding and energy transfer element windings that reduce displacement currents. In one aspect, an energy transfer elements includes an energy transfer element core with first and second windings wound around the energy transfer element core. The first winding is capacitively coupled to the second winding. A third winding is wound around the energy transfer element core to generate a third winding electrostatic field to substantially cancel relative electrostatic fields generated by the first and second windings relative to the energy transfer element core to substantially reduce a capacitive displacement current between the first and second windings. Fourth and fifth windings are wound around the energy transfer element core between the first and second windings to substantially reduce the capacitive displacement current between the first and second windings.

Abstract: In a fly-back DC voltage conversion circuit, a transformer accumulates energy during the on-state of a switching element, and the accumulated energy is outputted from a secondary winding during the off-state of the switching element. The switching element is placed in the on-state when the accumulated energy is completely outputted from the secondary winding. A voltage applied to the switching element is differentiated by a capacitor to detect a discharge termination point at which the current of the transformer becomes zero to change a switching frequency of the switching element. The DC voltage conversion circuit can attain control in a current boundary state without significantly increasing cost.

Abstract: An active EMI filter senses current in a ground line as a voltage across a capacitor coupled to the ground line. The EMI filter senses common mode voltage and determines a difference between the common mode voltage and noise to provide an output to the ground line to reduce the difference.

Abstract: A valve control circuit in accordance with the invention comprises a direct current (DC) voltage source and a DC-DC step-up converter coupled with the DC voltage source. The circuit also comprises a programmable controller coupled with the DC-DC converter, a first valve control switch coupled with the DC source and the controller, and a first valve coupled with the first valve control switch. The circuit further comprises a valve-picking circuit coupled with the controller such that a current source of the valve-picking circuit is selectively coupled with the first valve control switch to open the first valve in response to electrical signals from the controller.

Abstract: A DC converter is connected to a DC source on its input side. On the output side, the DC delivers a converted DC voltage to at least one electric consumer via a cable connection. To improve such a DC converter in that it has a comparatively simple structural design and is able to reliably convert high DC voltages even in the case of high power, and in such a way that the reliability of the converter is increased and cooling systems entailing high costs can be dispensed with, the DC converter comprises a plurality of DC converter components, each of said DC components being, on the input side, serially connected to the DC source and, on the output side connected in parallel to the cable connection so as to provide the converted DC voltage for the electric consumer.

Abstract: A method and system is provided for programming the digital filter compensation coefficients of a digitally controlled switched mode power supply within a distributed power system. The distributed power system comprises a plurality of point-of-load (POL) regulators each comprising at least one power switch adapted to convey power to a load and a digital controller adapted to control operation of the power switch responsive to a feedback measurement. The digital controller further comprises a digital filter having a transfer function defined by plural filter coefficients. A serial data bus operatively connects each of the plurality of POL regulators. A system controller is connected to the serial data bus and is adapted to communicate digital data to the plurality of POL regulators via the serial data bus. The digital data includes programming data for programming the plural filter coefficients. The system controller further comprises a user interface adapted to receive the programming data therefrom.

Abstract: An input rectifier of a power supply apparatus rectifies a selected one of two, higher and lower AC voltages applied to it. First and second inverters are connected in the output of the input rectifier. A high-frequency transformer is connected to the output of each of the first and second inverters. An output rectifier is connected to the output of each of the high-frequency transformers. When the higher one of the two AC input voltages is applied to the input rectifier, a switching circuit connects the first and second inverters in series between output terminals of the input rectifier. When the lower AC voltage is applied to the input rectifier, the switching circuit connects the first and second inverters in parallel between the output terminals of the input rectifier. When the first and second inverters are connected in series between the output terminals of the input rectifier, a voltage balancing control unit operates to suppress imbalance between input voltages to the first and second inverters.

Abstract: The invention relates to a converter provided with a resonant circuit, in which converter the resonant circuit comprises means for detecting a zero current condition in the auxiliary valve. The means is adapted to send to the control device of the converter signals indicating a prevailing zero current condition in the auxiliary valve, and the control device is adapted to allow a turn-off of a semiconductor component of turn-off type of the auxiliary valve only after the receipt by the control device of a signal indicating a prevailing zero current condition in the auxiliary valve. The invention also relates to a method for controlling such a converter.

Abstract: For an inspection of a display device which incorporates a driver circuit around pixels, a start pulse and a clock pulse are required to be inputted as inspection signals. The more complex the driver circuit is, the more complexity the start pulse and the clock pulse tend to have, which will increase the manufacturing cost of inspection signals. In addition, since a clock generator is required, cost of an inspection device is increased. Furthermore, it will lead to a longer inspection time. By setting all the power supplies for the driver circuit at a desired potential, a desired potential is outputted regardless of an input signal.

Abstract: A shift register includes at least one stage circuit that has at least three voltage control switches, a storage element, and a first clock signal, a second clock signal and a third clock signal to control various switches. Input signals are stored in the capacitor and sequentially transferred to the next stage. During transferring to the next stage, pixel switches of one row on the panel display are activated to receive information delivered from the data end for displaying on the pixels. The clock signals have the characteristics that the first clock signal, second clock signal and third clock signal are not at the same certain potential concurrently to prevent the switches of each stage (the second and third switches) from forming a DC path and burning out.

Abstract: A nonvolatile memory device includes a memory cell array, a control circuit, a voltage boost circuit, a timer circuit, a discharge circuit and a sensor circuit. The control circuit generates an erase execution (EE) signal in response to an erase command (EC) signal, stops the EE signal and generates a discharge control (DC) signal in response to an erase termination (ET) signal, stops the DC signal in response to a discharge termination (DT) signal, and stops the EE signal and the DC signal in response to a reset signal. The boost circuit provides high voltage in response to the EE signal. The timer circuit generates the ET signal after receiving the EE signal. The discharge circuit discharges the high voltage and the sensor is enabled in response to the DC signal or the reset signal. The sensor generates the DT signal when the high voltage drops to a predetermined voltage.

Abstract: An amplifier circuit including a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit including a PMOS transistor (11), an NMOS transistor (12), and the like is provided with an NMOS transistor (13) connected to the NMOS transistor (12) to increase a source voltage of the NMOS transistor (12) and DC offset detecting means for detecting a DC offset and applying a voltage adjusted so as to reduce the DC offset to a gate of the NMOS transistor (13).

Abstract: In a data reading method according to the present invention, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell. Next, reference signal generating data corresponding to a high level side is written to the memory cell. Next, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data. Next, a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is first written to the memory cell without using a bit line. A high-level or low-level signal corresponding to data to be written is applied to the bit line in advance. When a low-level signal is applied to the bit line, low-level data is written from the bit line to the memory cell.

Abstract: To provide a technology enabling a terminal device to use various functions provided in a data processing device without the use of a device driver. A multifunction device executes a process for implementing a function indicated by instruction data when such instruction data is stored in a shared area of the RAM. Here, the shared area of the RAM in which the instruction data is stored can be recognized by a personal computer connected to the multifunction device as a storage area that can be accessed through the file system, which is a function provided as a standard feature of the operating system. Accordingly, operations of the multifunction device can be controlled from the personal computer end simply by storing instruction data in the shared area via the operating system, eliminating the need for a special device driver to control the operations of the multifunction device.

Abstract: The present invention has a configuration with which the data “0” and the data “1” can be arbitrarily written to a reference cell capacitor for generating a reference potential, and comprises a non-volatile capacitor for storing the data to be written. This configuration makes the fine adjustment of the reference potential possible without a mask correction, which improves yield. The present invention also comprises a means of rewriting only the reference capacitors. By this configuration, the dispersion of the reference potential can be controlled, and yield is improved.

Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

Abstract: An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated,.

Abstract: A nonvolatile memory cell occupying a minimum chip area is provided with a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of the cell structure so that one or more programmed states are determined. A semiconductor memory constructed by a large number of the nonvolatile memory cells can be obtained in a compact manner with simple and as few as possible steps. This process vertically stacked layers, and this semiconductor memory is thus easily to be combined with other integrated circuits on a single chip.

Abstract: Memory interface apparatus and methods utilize unidirectional links. An embodiment of a memory apparatus may include a first redrive circuit to receive a first signal from a first unidirectional link and redrive the first signal on a second unidirectional link, a second redrive circuit to receive a second signal from a third unidirectional link and redrive the second signal on a fourth unidirectional link, and a memory device or interface coupled to the first redrive circuit. An embodiment of a method may include transmitting a first signal from a memory controller to a memory module over a first unidirectional link, selectively redriving the first signal from the first memory module to a second memory module over a second unidirectional link, and transmitting a second signal from the first memory module to the memory controller over a third unidirectional link.

Abstract: The invention is in the field of Computer Engineering and can be used in memory devices for various computers, specifically in developing a universal memory system with high data reading and writing speed along with capabilities for long term storage and high information density, as well as in developing video and audio equipment of a new generation, in developing associative memory systems, and in creating synapses (electric circuit elements with programmable electric resistance) for neuronal nets. The lack of such an element holds back the development of true neuronal computers.

Abstract: A device and a method that permit easy and accurate determination of a walking condition regardless of differences in foot landing points on soles or lengths of legs of a walker are provided. According to this device, a measuring device measures a parameter indicating a displacement speed or a displacement acceleration of a bottom end portion of one leg with respect to a bottom end portion of the other leg of the walker. A first storage device stores patterns of plots corresponding to parameters and walking conditions of the walker. A generating device generates plots defined in the determination space by parameters measured by the measuring device. A determining device determines walking conditions of the walker on the basis of the patterns of the plots stored and retained in conjunction with the walking conditions by the first storage device and the patterns of the plots generated by the generating device.

Abstract: There are provided an organic bistable element, which is simple in structure, can eliminate the need to increase production process steps, and has a low switching voltage, a memory device using the same, and a method for driving the organic bistable element and the memory device. The organic bistable element having a laminate structure comprises a laminate interposed between a first electrode and a second electrode, the laminate comprising two or more layers of organic thin film which are each dielectric and are different from each other in electrical conductivity. The two or more layers of organic thin film have been stacked on top of each other through an electrically conductive thin film.

Abstract: A method of storing data includes transferring first data from a data line to a first sense amplifier, transferring the first data from the first sense amplifier to a first bit line, and transferring second data from the data line to a second sense amplifier. In the above operation, a period of the data storing operation of the second data from the data line to the second sense amplifier and a period of the data storing operation of the first data from the first sense amplifier to the first bit line are overlapped.

Abstract: Provided are a semiconductor integrated circuit including a unit for detecting soft defects in a pull-down circuit of a static memory cell, and a method of detecting soft defects. The semiconductor integrated circuit includes a static memory cell, a bit line connected to a first node of the static memory cell and a complementary bit line connected to a second node of the static memory cell, and a current supply unit connected to the bit line and the complementary bit line to supply current to the bit line and the complementary bit line in response to a test signal during a test mode. Accordingly, a voltage difference between the bit line and the complementary bit line during a read operation of the test mode is smaller than that during a read operation of a normal mode. When a failure occurs after the read operation is performed under this test mode condition, it is determined that the semiconductor integrated circuit having the failure is vulnerable to soft defects.

Abstract: Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

Abstract: Embodiments of the present invention provide a memory system. In one embodiment, the memory system comprises an array of memory cells, a write circuit configured to write memory cells in the array of memory cells and a control circuit. The control circuit is configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells, and control the write circuit to write the encoded received data into the array of memory cells at a fault address of the fault pattern.

Abstract: A method of writing to a magnetic random access memory comprising: producing a magnetic field along a magnetically hard axis of a free layer of a magnetoresistive element; and passing current through the magnetoresistive element to change a direction of magnetization of the free layer by spin momentum transfer. A magnetic random access memory that operates in accordance with the method is also included.

Abstract: A magnetic random access memory comprises a plurality of memory elements each comprising a magnetic pinned layer; a synthetic antiferromagnetic free layer including a first ferromagnetic layer, a second ferromagnetic layer, and a first nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, wherein the directions of magnetization of the first ferromagnetic layer and the second ferromagnetic layer are antiparallel; and a first conductive nonmagnetic layer positioned between the magnetic pinned layer and the synthetic antiferromagnetic free layer; and means for applying a current to each of the plurality of memory elements to affect the direction of magnetization of the synthetic antiferromagnetic free layer. A method of storing data using the magnetoresistive random access memory is also provided.

Abstract: A photolithographic process using an X-direction delimiting mask (S11) for aligning respective side faces of a TMR element (1) and a strap (5) situated in a negative X side is performed, to shape the TMR element (1) and the strap (5) into desired configurations. The X-direction delimiting mask (S11) includes a straight edge and is disposed such that the straight edge is parallel to a Y direction and crosses both the TMR element (1) and the strap (5) in plan view. In use of the X-direction delimiting mask (S11), respective portions of the TMR element (1) and the strap (5) situated in a positive X side relative to the straight edge in plan view are covered with the X-direction delimiting mask (S11).

Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

Abstract: A memory card (100) is comprised of: a flash memory (120) that includes a plurality of physical blocks (122) made up of a plurality of pages for storing data and a page register (121) that holds data to be written to a page; and a controller (110) that specifies and erases an invalid physical block with reference to a valid block table (114) indicating whether valid data is stored in each of the physical blocks (122), when data is written, and that transfers, at the same time, the data to be written to the page register (121) while carrying out said erasure.

Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Abstract: A master block lock control word is written to a mini array of non-volatile fuses. The control word is recalled and decoded. A successful recall of the control word generates an indication that the master block lock bit is permanently disabled from subsequent changes.

Abstract: In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data judging control unit generates an average reference current based on a first reference current from the first reference cell and a second reference current from the second reference cell, and determines data of each of the memory cells by comparison of a read-out current of each memory cell with the average reference current. A control unit performs a program verification operation to each memory cell. A compensation current supplying unit supplies a compensation current to a bit line of a target memory cell when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation.

Abstract: A memory agent may include a link interface having a plurality of bit lanes, wherein the memory agent is capable of utilizing more than one of the plurality of bit lanes to detect the presence of another memory agent coupled to the link interface.

Abstract: A memory agent may have a redrive circuit having a plurality of redrive paths, and a deskew circuit separate from the plurality of redrive paths. A deskew circuit may be integral with or separate from a redrive circuit having the plurality of redrive paths. A deskew circuit may be coupled between a redrive circuit and a memory device or interface.