Patents Issued in December 9, 2004
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Publication number: 20040246787Abstract: First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.Type: ApplicationFiled: July 12, 2004Publication date: December 9, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Hiroyuki Yamauchi
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Publication number: 20040246788Abstract: There are provided a magnetoresistive effect element having a satisfactory magnetic characteristic and a magnetic memory device including this magnetoresistive effect element to produce excellent write/read characteristics.Type: ApplicationFiled: February 11, 2004Publication date: December 9, 2004Inventors: Takeyuki Sone, Kazuhiro Bessho, Masanori Hosomi, Tetsuya Mizuguchi, Kazuhiro Ohba, Tetsuya Yamamoto, Yutaka Higo, Hiroshi Kano
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Publication number: 20040246789Abstract: A polycrystalline silicon plate has grain boundary lines on a surface thereof, and at least one of the grain boundary lines is a quasi-linear grain boundary line (1). The silicon plate is used to produce a solar cell. The silicon plate is formed using a base substrate having an irregular surface provided with dotted or linear protrusions, which makes it possible to control the grain boundary lines. As such, an inexpensive and high-quality silicon plate can be provided. Further, by employing this silicon plate to produce a solar cell, an inexpensive and high-quality solar cell can be provided as well.Type: ApplicationFiled: February 27, 2004Publication date: December 9, 2004Inventor: Yoshihiro Tsukuda
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Publication number: 20040246790Abstract: Circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are presented. The source terminal of a low Vtp PMOS transistor is maintained at ground potential during DRAM standby mode. The source terminal of the low Vtp PMOS transistor is raised to an intermediate supply voltage responsive to a transition from DRAM standby mode to either DRAM read mode, write mode, or refresh mode and prior to development of a differential voltage between the gate and drain terminals of the low Vtp PMOS transistor. The circuits and methods of the invention advantageously limit current loss through the low Vtp PMOS transistor when the differential voltage develops between the gate and drain terminals of that low Vtp PMOS transistor and in the event of a word line and digital line short-circuit.Type: ApplicationFiled: February 20, 2004Publication date: December 9, 2004Applicant: Micron Technology, Inc.Inventor: Yangsung Joo
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Publication number: 20040246791Abstract: A memory unit includes unit blocks laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells laid out to form a cell matrix and redundant lines including redundant memory cells each used for repairing an abnormal memory cell. Every plurality of unit blocks forms a two-dimensional group oriented in a first direction and a second direction, and the redundant lines connected in the first and second directions are shared by the unit blocks pertaining to the two-dimensional group. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs in storage means provided for each of the unit blocks as address pairs required for determining a redundant line to be used for repairing an abnormal memory cell and, then, finds a redundant line to be used for repairing an abnormal memory cell for each of the unit blocks pertaining to the two-dimensional group on the basis of the address pairs stored in the storage means.Type: ApplicationFiled: April 20, 2004Publication date: December 9, 2004Inventors: Kou Nagata, Hiroaki Kodama
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Publication number: 20040246792Abstract: An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy circuit and method for replacing a memory area.Type: ApplicationFiled: April 23, 2004Publication date: December 9, 2004Inventor: Peter Beer
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Publication number: 20040246793Abstract: The semiconductor memory device comprises a plurality of word lines including one or more redundant word lines; a plurality of pairs of bit lines; a plurality of memory cells connected to the above-mentioned plurality of word lines and the above-mentioned plurality of pairs of bit lines; a plurality of word-line drivers, each of which is connected to respective one ends of the above-mentioned plurality of word lines and controlled by a plurality of word-line control signals; and a plurality of first word-line control circuits respectively located at the other ends of the above-mentioned plurality of word lines, each of the above-mentioned plurality of first word-line control circuits receiving a signal level of a corresponding one of the above-mentioned plurality of word lines, wherein, in the case where the signal level of the above-mentioned corresponding word line is a first level at which corresponding ones of the above-mentioned plurality of memory cells connected to the above-mentioned corresponding worType: ApplicationFiled: April 28, 2004Publication date: December 9, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Yoshinobu Yamagami
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Publication number: 20040246794Abstract: An apparatus for mounting semiconductors contains a bonding station, whereby the bonding station comprises a wafer table for presenting the semiconductor chips, a substrate table and a Pick and Place system with a bondhead with a chip gripper. Part of the wafer table is located underneath the substrate table. The Pick and Place system has a first linear motor that comprises a rigidly arranged stator and a shuttle that can be moved in a first direction guided by first guide elements, and a second linear motor that comprises a rigidly arranged stator and a shuttle that can be moved in a second direction. The shuttle of the first linear motor has second guide elements that guide the shuttle of the second linear motor. The bondhead with the chip gripper is arranged on the shuttle of the second linear motor.Type: ApplicationFiled: June 3, 2004Publication date: December 9, 2004Inventor: Dieter Vischer
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Publication number: 20040246795Abstract: An active layer wafer having a larger diameter is placed over a stationary supporting substrate wafer having a smaller diameter. A pusher plate is pressed against an orientation flat of the larger wafer to move the wafer substantially in the horizontal direction. In the course of the pressing operation, the pusher plate is also pressed against the orientation flat of the smaller wafer so as to move the two wafers together. Then, as a result of each of the cut sections for alignment of the wafer being pressed against an aligning plate, the larger wafer and the smaller wafer can be bonded to each other with their centerlines and orientation flats aligned with respect to each other.Type: ApplicationFiled: June 8, 2004Publication date: December 9, 2004Inventor: Shinichi Tomita
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Publication number: 20040246796Abstract: A method for locating a repair solution for a memory that includes a memory array comprising a plurality of rows and a plurality of columns, N redundant rows, and M redundant columns is described. Both N and M are integers, where N is greater than or equal to zero and M is greater than or equal to zero. The N redundant rows and the M redundant columns are collectively referred to as redundant lines. The method includes generating a first defect matrix representing defects in the memory array. Additionally, the method includes recursively, until either the repair solution is found or the redundant lines are consumed: selecting a first line represented in the defect matrix and having at least one defect; generating a second defect matrix by eliminating at least the defects in the first line from the first defect matrix; and determining if the repair solution is found.Type: ApplicationFiled: July 2, 2004Publication date: December 9, 2004Inventors: Haluk Konuk, Jose L. Landivar, Zongbo Chen
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Publication number: 20040246797Abstract: A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode.Type: ApplicationFiled: January 13, 2004Publication date: December 9, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Jeung, Jong-Hoon Jung
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Publication number: 20040246798Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.Type: ApplicationFiled: March 24, 2004Publication date: December 9, 2004Inventors: Daniel C. Guterman, Yupin Kawing Fong
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Publication number: 20040246799Abstract: A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided. The precharge control circuit may be embodied as a delay circuit unit which receives and delays a precharge enable signal for a predetermined delay time; a NAND gate which receives the precharge enable signal and the output of the delay circuit; and an inverter which inverts the output of the NAND gate. The precharge control circuit may enable the word lines before disabling the precharge signal.Type: ApplicationFiled: February 20, 2004Publication date: December 9, 2004Inventor: Tae-joong Song
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Publication number: 20040246800Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.Type: ApplicationFiled: June 3, 2004Publication date: December 9, 2004Applicant: STMicroelectronics S.A.Inventors: Franck Genevaux, Francois Jacquet
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Publication number: 20040246801Abstract: Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.Type: ApplicationFiled: February 5, 2004Publication date: December 9, 2004Inventors: Jae-woong Lee, Chi-wook Kim, Sang-seok Kang
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Publication number: 20040246802Abstract: Methods and apparatus for refreshing a dynamic memory cell in a memory circuit are provided, wherein the required time between refresh operations may be increased by increasing the potential difference between a high charge potential and common center potential used during a refresh mode relative to the potential difference between the high charge potential and the common center potential used during read or write modes.Type: ApplicationFiled: April 2, 2004Publication date: December 9, 2004Inventor: Manfred Dobler
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Publication number: 20040246803Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.Type: ApplicationFiled: July 13, 2004Publication date: December 9, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
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Publication number: 20040246804Abstract: A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.Type: ApplicationFiled: February 6, 2004Publication date: December 9, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Woo-yeong Cho, Kyung-hee Kim
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Publication number: 20040246805Abstract: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.Type: ApplicationFiled: October 21, 2003Publication date: December 9, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Koji Nii
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Publication number: 20040246806Abstract: A semiconductor memory includes a plurality of memory array partitioned into first and second memory banks in correspondence with one of a plurality of mask options such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays. A first horizontal global row decoder is configured to receive a first subset of addresses for the first memory bank and in response provide a first plurality of predecoded row address signals on a first plurality of lines extending only across the at least one but less than all of the plurality of memory arrays. A second horizontal global row decoder is configured to receive a first subset of addresses for the second memory bank and in response provide a second plurality of predecoded row address signals on a second plurality of lines extending only across the corresponding remainder of the plurality of memory arrays.Type: ApplicationFiled: January 29, 2004Publication date: December 9, 2004Applicant: Winbond Electronics CorporationInventor: Chang Wan Ha
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Publication number: 20040246807Abstract: A multi-port memory device with stacked banks is provided. The multi-port memory device includes a number of ports, and a plurality of stacked banks, two or more of which share one data line sense amplifier. Each stacked bank includes a plurality of memory cells. Data line sense amplifiers are connected respectively between the stacked banks and read buffers to sense data read from memory cells of a selected bank among the stacked banks. The read buffers are connected respectively to the ports, store memory cell data output from the data line sense amplifiers, and output the stored data to the ports. Read data lines connect the data line sense amplifiers with the read buffers, respectively. Write buffers are connected respectively to the ports, and convert and store write data received in serial through the ports in a parallel form. Write data lines connect the data line drivers with the write buffers, respectively.Type: ApplicationFiled: June 1, 2004Publication date: December 9, 2004Inventor: Seung-hoon Lee
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Publication number: 20040246808Abstract: A writing driver circuit of a phase-change memory array comprising a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.Type: ApplicationFiled: April 22, 2004Publication date: December 9, 2004Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Beak-Hyung Cho, Woo-Yeong Cho, Hyung-Rok Oh
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Publication number: 20040246809Abstract: An integrated circuit comprises a first circuit that receives a clock signal. A first temperature sensor senses a first temperature. Non-volatile memory that communicates with the first temperature sensor outputs calibration data as a function of the first temperature. A semiconductor oscillator that communicates with the non-volatile memory and the first circuit generates the clock signal having a frequency that is related to the calibration data.Type: ApplicationFiled: July 16, 2004Publication date: December 9, 2004Applicant: Marvell World Trade Ltd.Inventor: Sehat Sutardja
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Publication number: 20040246810Abstract: An apparatus includes at least one logic storage unit which has a clock input. The apparatus also includes a logic circuit associated with the at least one logic storage unit. The logic circuit is capable of selectively preventing a clock signal from being applied to the clock input of the at least one logic storage unit.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Charles E. Dike, David J. Hawkins
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Publication number: 20040246811Abstract: Disclosed is a circuit for generating a clock signal to driver a plurality of memory components in a memory subsystem. The clock driver circuit comprises a clock generator for transmitting a clock signal to drive the plurality of memory components, a memory controller for controlling the plurality of memory components, and an adjustable impedance circuit residing within said memory controller such that the adjustable impedance circuit is programmable in accordance with a control input generated by the memory controller. The clock generator is configured to generate a clock signal with a voltage swing controlled by the impedance of the adjustable impedance circuit.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Scott C. Best, Frank Lambrecht
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Publication number: 20040246812Abstract: Circuits and methods for controlling data access operations in memory devices such as SRAM (static random access memory) devices. The circuits and methods provide timing and control for memory access operations by propagating a control pulse along a decode path from which a sequence of control pulses are generated at points in the decode path to synchronize activation of wordlines and sense amplifiers and precharge/equalization of bit lines. Preferably, an address gated pulse schema is implemented to synchronize and restrict switching activity spatially and temporally to only regions of a memory array that are being accessed, and for limited periods of time just sufficient to generate signals for read or write operations. Advantageously, the circuits and methods enable SRAM cell delays to track CMOS gate delays more closely at low voltages and reduce switching power by restricting switching transitions only to the regions of memory that are accessed.Type: ApplicationFiled: June 5, 2003Publication date: December 9, 2004Applicant: International Business Machines CorporationInventors: Azeez Bhavnagarwala, Stephen V. Kosonocky
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Publication number: 20040246813Abstract: A invention chemicals in the form of gases, into a fluid stream. The mixing system withdraws a side stream of fluid from a main fluid stream. The side stream is pressurized and directed through a convergent nozzle, producing a high-velocity jet. This jet is directed onto a deflector plate located on the center line of the conduit that carries the main fluid stream and is thereby diverted in the radial directions normal to the flow direction of the main fluid stream. The deflector is provided with an gas diffudion port for injecting the chemicals that are to be mixed into the main stream. The even distribution of the injected chemicals is ensured by the hydrodynamic forces generated by the flow of the high-velocity jet over the deflector.Type: ApplicationFiled: May 20, 2002Publication date: December 9, 2004Inventor: John Stewart Lang
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Publication number: 20040246814Abstract: The invention relates to a mechanical device with no moving parts that homogeneously mixes two or more liquids or liquids and gases. It is possible with the device to totally saturate liquids with gas droplets of less than one micron. The device comprises an inlet for partially mixed components leading to a plurality of passageways converging axially into a chamber which has radial openings into another chamber defined by a conical member converging in the axial direction and having an opening at its apex to exit the mixed components, the components exiting the radial openings collide with the walls of the conical member producing shear and turbulence and subsequently spinning within the conical member and are then subjected to increased pressure in the axial direction by the converging wall of the conical member.Type: ApplicationFiled: August 2, 2004Publication date: December 9, 2004Inventors: Weng Chuen Foong, Paul Woodley
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Publication number: 20040246815Abstract: A device and method for creating hydrodynamic cavitation in fluids is disclosed. The device can include a chamber formed by at least one wall. The wall can have a first orifice configured to permit the introduction of a first liquid stream into the chamber and an opposing second orifice configured to permit the introduction of a second liquid stream into the chamber. The first orifice can have a diameter sufficiently smaller than the second orifice to permit penetration of the first liquid stream into the second liquid stream.Type: ApplicationFiled: January 16, 2004Publication date: December 9, 2004Inventor: Oleg V. Kozyuk
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Publication number: 20040246816Abstract: Improved methods and apparatuses for directly monitoring well casing strain and structural integrity are disclosed that allows for monitoring of potentially damaging strain from any orientation or mode and over long stretches of well casing. In a preferred embodiment, optical fiber sensors are housed within a housing and attached to the exterior surface of the casing. The sensors may be aligned parallel, perpendicular, or at an appropriate angle to the axis of the casing to detect axial, hoop, and shear stresses respectively. The sensors are preferably interferometrically interrogatable and are capable of measuring both static and dynamic strains such as those emitted from microfractures in the well casing. Analysis of microfracture-induced acoustics includes techniques for assessment of relatively high frequencies indicative of the presence of microfractures.Type: ApplicationFiled: May 19, 2003Publication date: December 9, 2004Inventor: Peter C. Ogle
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Publication number: 20040246817Abstract: A method for performing amplitude variation with offset (AVO) analysis of a plurality of seismic data traces. The method includes fitting at least a two-term AVO equation to at least three seismic data traces having small angles of incidence using a curve fitting technique to generate an AVO intercept and an AVO gradient, computing a plurality of synthetic seismic data traces using the AVO intercept and the AVO gradient, subtracting the synthetic seismic traces from the plurality of seismic data traces to generate a plurality of higher-order seismic data traces characterized by a residual AVO equation, and fitting the residual AVO equation to the higher order seismic data traces having large angles of incidence using the curve fitting technique to generate a higher order AVO attribute.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventor: Subhashis Mallick
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Publication number: 20040246818Abstract: A weight block for a marine seismic cable comprises a heavy weight member with a soft, overlying layer. The weight block is bolted, hinged, or otherwise attached to the cable to provide desired ballast. The outer covering of the weight block is molded over the inner metal member with an injection molding machine or other standard techniques. The inner diameter of the molding on the block may have a plurality of ribs with a smaller diameter than the nominal diameter of the solid-filled or liquid filled cable.Type: ApplicationFiled: June 6, 2003Publication date: December 9, 2004Inventors: Michael L. Maples, David S. Lamance, Robert E. Foertsch
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Publication number: 20040246819Abstract: A system and method for dynamically adjusting expiration dates displayed on consumer products, the system and method utilizing an LCD display for displaying an expiration date and messages, sensors for monitoring environmental conditions, a clock for counting back the expiration date, and a controller for determining messages and adjustments to the displayed expiration date based on monitored environmental conditions.Type: ApplicationFiled: July 13, 2004Publication date: December 9, 2004Applicant: Pitney Bowes Inc.Inventor: Douglas B. Quine
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Publication number: 20040246820Abstract: The invention concerns a chronograph mechanism of the type comprising a chronograph train (22) including:Type: ApplicationFiled: July 13, 2004Publication date: December 9, 2004Inventor: Johnny Girardin
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Publication number: 20040246821Abstract: When a time keeping apparatus is in a power saving mode, performing time display is stopped, and the apparatus periodically receives a time data from outside and sets the data to a second time counter 98 and an hour-and-minute time counter 99. When the operation mode of the time keeping apparatus is switched from the power saving mode to the display mode, the apparatus resumes to display the current time based on the counted values in the second time counter 98 and the hour and minute time counter 99.Type: ApplicationFiled: May 21, 2004Publication date: December 9, 2004Inventor: Teruhiko Fujisawa
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Publication number: 20040246822Abstract: One embodiment of the present invention provides a system that provides a unified telephony solution. During operation, the system receives a request for a telephony service at a telephony controller. In response to this request, the system accesses a telephony service provided by an application server through a voice extensible markup language (VXML) browser. While performing the telephony service, the system interfaces to a public switched telephone network (PSTN) through a telephony gateway.Type: ApplicationFiled: August 14, 2003Publication date: December 9, 2004Inventor: Johnny Wong
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Publication number: 20040246823Abstract: A hybrid device having a plurality of task-handlers corresponding to a function key uses a user interface method. The user interface method includes receiving information necessary to change priorities of the task-handlers corresponding to the function key; changing the priorities of the task-handlers based on the received information; and storing information regarding the changed priorities according to a predetermined application type.Type: ApplicationFiled: April 22, 2004Publication date: December 9, 2004Applicant: Samsung Electronics Co., Ltd.Inventor: Seong-ho Kwon
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Publication number: 20040246824Abstract: A method for reading a table of content (TOC) of a multi-session optical medium is provided. This method includes providing a memory for storing the TOCs of sessions having stored said digital information therein, reading TOC stored in the memory out as the change of the digital information state is adding another session, and combining the stored TOCs with the TOC of the newly-added session together, and changing the digital information state of the latest-stored session at first, and then storing the changed digital information state of the latest-stored session into the memory as the change of the digital information state is not adding another session.Type: ApplicationFiled: June 9, 2003Publication date: December 9, 2004Applicant: MEDIA TEK INC.Inventors: Yuan-Ting Wu, Tun-Hsing Liu
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Publication number: 20040246825Abstract: A portable optical compact disk drive has a casing, a tray, an image capture unit and a control circuit. The casing has a tray-receiving cavity formed therein. The tray is capable of be accepted in the tray-receiving cavity via a free end of the casing, and, alternatively, being ejected from and placed into the casing. The tray has a disk-receiving window formed therein to carry the optical compact disk. The image capture unit is arranged in the casing, and records data stored on the surface of the optical compact disk loaded in the tray, while the tray is located in the tray-receiving cavity. The control circuit electrically connects the image capture unit to receive image information, and is capable of decoding the image information and transmitting the decoded image information to the peripheral circuit.Type: ApplicationFiled: May 26, 2004Publication date: December 9, 2004Inventor: Yu-Nung Shen
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Publication number: 20040246826Abstract: A tray for mounting a cartridge incorporating a flat information recording medium includes sliders sliding in a loading direction of the cartridge on a tray base in cooperation with the mounting action of the cartridge, and a slider moving mechanism for moving the slider between an initial position, and a plurality of stopping positions remote from the initial position by specific distances in the loading direction. The plurality of stopping positions are at least in two stopping positions, that is, a first stopping position remote from the initial position by a first distance in the loading direction, and a second stopping position remote from the initial position by a second distance longer than the first distance in the loading direction. Thereby, if a cartridge is mounted on a tray in a wrong direction, the user can easily recognize its wrong mounting.Type: ApplicationFiled: April 22, 2004Publication date: December 9, 2004Inventors: Goro Naoki, Yoshito Saji, Kozo Ezawa, Masahiro Inata
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Publication number: 20040246827Abstract: According to the invention, case members each include a main surface and side surfaces provided at ends of the main surface. At a corner where a pair of side surfaces in at least one of the case members adjoin, an integral part having at least one pair of continuously integrated side surfaces is provided. Therefore, the corners of the case members can be prevented from bending or deforming, and the mechanical strength of the main surface can be improved. Therefore, the shock resistance can be improved, and the thickness of the case members can be reduced in order to reduce the size and weight of the device.Type: ApplicationFiled: May 20, 2004Publication date: December 9, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masanari Esaki, Yuji Tanaka, Kazuo Matsumoto, Noriyuki Ide, Hirohisa Koizumi
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Publication number: 20040246828Abstract: A touching plate of the emergency mechanism, which is located near the front panel of a casing, is rotatably pivoted, an arm is protruded from the touching plate so that it is opposite to a lever protruded from the end of a slide bar, a nozzle having a prescribed length, which is located near the thin rod contact face of the touching plate, is protruded concentrically to a through-hole integrally from the inner face of the front panel, the thin rod passed through the through-hole is guided by the nozzle so that the tip of the thin rod is brought into contact with the thin rod contact face of the touching plate. In this way, by pushing in the touching plate about the pivoting shaft, the slide bar is slid through the arm and lever, thereby slightly moving the tray forward.Type: ApplicationFiled: May 21, 2004Publication date: December 9, 2004Applicant: FUNAI ELECTRIC CO., LTD.Inventor: Takashi Miyamoto
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Publication number: 20040246829Abstract: A high capacity motorized rack holds a plurality of DVD boxes or containers in holders flexibly inter-connectable with each other to form a rotatable continuous loop. The loop is rotatably retained within a vertical rack housing and is driven by a motor, disposed within the housing, under user control such that the loop is rotated until a desired DVD is moved to the top fan-out region of the belt. A rack may hold two or more such loops of inter-connected holders. A preferred embodiment employs inter-connectable holders that each retain two DVD boxes in a side-by-side configuration. A lamp and/or barcode scanner may be disposed on the housing for ease of DVD selection. User control can include voice commands to direct loop rotation and speed.Type: ApplicationFiled: June 30, 2004Publication date: December 9, 2004Inventors: Charles E. Taylor, Andrew J. Parker, Edward C. McKinney
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Publication number: 20040246830Abstract: An optical reproducing/recording apparatus (1) includes a chassis (11) with a first seat (17) and three second seats (16), a turntable (12), an optical pickup head (13) and a guide device (15). The turntable is located on the chassis for rotating an optical disk positioned thereon. The guide device has a first and second beams (151, 152). An end of the first beam is fixed on the first seat, the other end of the first beam and two ends of the second beam are respectively fixed on the second seats by an adjustable device (18). Each second seat has a groove for accommodating the beam and each adjustable device comprises an elastic element (182) and an adjustable element (181). The elastic element is positioned between the beam and a bottom of the groove and the adjustable element fixes the beam in the groove against a side of said groove.Type: ApplicationFiled: May 24, 2004Publication date: December 9, 2004Inventor: Wen-Jie Bao
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Publication number: 20040246831Abstract: The magnitude (Ga) of an impact applied to a lens holder is constantly monitored based on an output of an impact sensor. When it is determined that Ga exceeds Gth, focus servo is released, and the lens holder is provided with a force to make it move away from a disk. Upon recheck of Ga, when it is determined that Ga is now equal to or less than Gth, the force having been provided to the lens holder is cancelled, and the focus servo is resumed.Type: ApplicationFiled: June 3, 2004Publication date: December 9, 2004Inventor: Tadashi Tachibana
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Publication number: 20040246832Abstract: An optical disc drive according to the present invention can read and write data from/on an optical disc 100 including record tracks to write data thereon and guide tracks for guiding a light beam 40. The drive includes: an optical pickup 101 with a converging optical system to focus the light beam 40 and form a spot thereof on the optical disc 100 for reading or writing the data; a tracking control section for controlling the converging optical system of the optical pickup 101 such that the light beam spot 40 follows a selected track on the optical disc 100 rotating; and a control unit 35 for operating the tracking control section in a first mode or in a second mode. In the first mode, the tracking control section makes the light beam spot 40 follow the recording tracks. In the second mode, the tracking control section makes the light beam spot 40 follow the guide tracks.Type: ApplicationFiled: March 2, 2004Publication date: December 9, 2004Inventors: Tetsuya Shihara, Tatsuya Takeuchi, Kenji Fujiune
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Publication number: 20040246833Abstract: Track mis-registration (TMR) correction is conditionally made in a hard disk drive using servo data in a closed loop servo control scheme, along with one or more alternative sensing schemes when an external shock or vibration occurs. The alternative sensing schemes include measurement of spindle motor speed using a frequency of servo markers read from a rotating disk, voice control motor (VCM) back emf, spindle motor speed back emf, and accelerometer readings. The predicted TMR resulting from the signal generated by the alternative sensing scheme(s) is simulated based upon a model of the disk drive system, and corrections are applied only if the expected TMR due to the disturbances is large enough that application of the corrections using the alternative sensing scheme would be likely to reduce the overall TMR.Type: ApplicationFiled: June 4, 2004Publication date: December 9, 2004Inventor: Richard M. Ehrlich
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Publication number: 20040246834Abstract: An optical pickup, optical recording and/or reproducing apparatus including the same, and a method of realizing a tracking servo that is compatible between different types of optical data storage media. The optical recording and/or reproducing apparatus splits light from a light source into a main beam and four or more sub beams symmetrical with respect to the main beam, which are then emitted on an optical data storage medium, wherein the four or more sub beams include two first sub beams located close to the main beam and two second sub beams located away from the main beam, and detects a tracking error signal by a differential push-pull (DPP) method using detection signals of the main beam and the pair of first sub beams and of the main beam and the pair of second sub beams for ±R/RW and RAM type optical data storage media, respectively.Type: ApplicationFiled: April 13, 2004Publication date: December 9, 2004Applicant: Samsung Electronics Co., Ltd.Inventor: Pyong-yong Seong
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Publication number: 20040246835Abstract: In a rewritable compact disc having a wobble groove on a substrate, crystal and amorphous states of a phase-change recording layer are an unrecorded/erased state and a recorded state, respectively. When the recording layer is exposed to recording light, amorphous marks assuming the recorded state are formed. At any of 2-, 4- and 8-times velocities with respect to a reference velocity (1-times velocity) whose linear velocity is 1.2-1.4 m/s, modulation m11 of a recorded signal when the recording light of approximately 780 nm in wavelength irradiates the recording layer via an optical system with NA=0.5 or 0.55 is 60-80%. A topmost level Rtop of reflectivity of the eye pattern of the recorded signal during retrieving at the 1-times velocity is 15-25%, and a jitter of the individual length of marks and inter-mark spaces during retrieving at 1-times velocity is 35 ns or less.Type: ApplicationFiled: June 10, 2004Publication date: December 9, 2004Inventors: Natsuko Nobukuni, Takashi Ohno, Masae Kubo, Michikazu Horie
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Publication number: 20040246836Abstract: The present invention relates to a method for controlling recording optical power. When a recording operation is paused, a playback signal characteristic for recorded data is detected. The recording optical power is controlled based upon the detected playback signal characteristic and hence the recording operation is resumed at the controlled recording optical power. Therefore, even though a characteristic of an optical pickup or disc varies when the recording operation is paused and resumed, an optimum recording operation can be performed and a playback characteristic for recorded data can be improved.Type: ApplicationFiled: March 18, 2004Publication date: December 9, 2004Inventor: Young Do Choi