Abstract: A disk device having a read/write processing device to improve the efficiency of operations between write commands that have overlapping data, and to prevent delays in execution processing of starting commands. A read command advance processor unit that processes in advance the read commands for which there are unprocessed write commands in the command queue and a write command overlap data processor overwrites the existing write command write data overlap part when the new write command write data overlaps the write data from an existing write command.

Abstract: In a computer system having memory in a processor and a plurality of attached heterogeneous disk storage subsystems, a system and method for managing the storage subsystems is provided. A volume of data is copied from a first disk storage subsystem from a first vendor to a second disk storage subsystem from a second vendor, of equal or greater capacity than the first disk storage subsystem, without requiring specialized hardware. An application program is able to access the data on the first disk storage subsystem while the data is being copied. The volume of data on the second disk storage subsystem is identified, within the computer system, as the volume of data on the first disk storage subsystem after the data is copied.

Abstract: Provided are a method, system, program, and data structure for maintaining metadata in a storage system, wherein metadata provides information on customer data in the storage system. A first metadata structure includes a plurality of fields, each field having a field length and including information on a block of customer data. A second metadata structure is generated to include a same plurality of fields in the first metadata structure, each field having the same field length as in the first metadata structure, wherein both the first and second metadata structures provide metadata on a same block of customer data. Metadata is included in at least one field in the second metadata structure from at least one field in the first metadata structure. Metadata is included in at least one field in the second metadata structure that is not included in the first metadata structure.

Abstract: A redundant array of inexpensive disks (RAID) system includes a plurality of defect-adaptive memory devices for sequentially storing information needed for data recovery in a predetermined region of a recording medium in the form of block, and storing data in a region other than the predetermined region. A plurality of caches are connected to the adaptive memory devices to store information blocks needed for data recovery, the information blocks being read from a predetermined memory device. A controller is connected to each adaptive memory device and cache to control the writing and reading of data and information needed for data recovery in each memory device, calculate information needed for recovery of data read from each memory device, and store the information needed for recovery of data calculated in a predetermined cache.

Abstract: In the multiple access storage system, when there is a data access request designated by a data frame transmitted from a host computer to a storage blade SB#0 through a network for data, the data frame is transferred to SB#2 having possibility of presence of data corresponding to the data access request if the data is not found in SB#0. If the data is not found in SB#2 either and the number of transmission times of the data frame between SBs as counted in the data frame is not smaller than the threshold of the number of transmission times set as an equal value in each SB, SB#2 broadcasts the data frame to all SBs having possibility of presence of the data. If the number of transmission times is smaller than the threshold, SB#2 transfers the data frame to another SB having possibility of presence of the data.

Abstract: A semiconductor memory card stores a plurality of audio objects (AOBs) that compose a plurality of tracks and playlist information showing a reproduction order for the tracks. The semiconductor memory card also stores, as resume information (PLMG_RSM_PL), (1) a Playlist_Number showing which playlist information was used the last time playback was performed for the semiconductor memory card, (2) a Track_Number showing the last track to be played back, and (3) a Playback_Time showing a position at which where playback was stopped as a time expressed in relation to the start of the track.

Abstract: An n-way interleaved set-associative external cache utilizes standard burst memory devices such as DDR (double data rate) memory devices. The interleaved set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags. The contents of the memory level device locations associated with each tag are stored in an alternating pattern in contiguous memory locations.

Abstract: Methods and systems for efficiently managing an application's address space are provided. An application requests physical memory beyond what is permissibly provided by the operating system. The application's virtual memory addresses are efficiently managed so that when access to a memory buffer is desired by the application, the logic required to map the buffer into the application's address space has been substantially completed prior to the application's request. Additionally, a method and system efficiently flushes, in advance of a need by an application, a virtual memory address from the virtual-to-physical memory caches (e.g., TLBs) of multiple processors on which the application is running.

Abstract: A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line is specified similar to the conventional PREFETCH instruction. The REP PREFETCH instruction stops if the address of the current prefetch cache line misses in the TLB, or if the current processor level changes. Additionally, a line is prefetched only if the number of free response buffers is above a programmable threshold. The prefetches are performed at a lower priority than other activities needing access to the cache or TLB.

Abstract: A method, apparatus, and computer implemented instructions for managing a plurality of caches of data, wherein the data processing system includes a plurality of independent computers. In response to initiating a read operation to read data on a data block, an indication is posted on a directory of data blocks identifying the computer that now holds a copy of that block and a location in the memory of that computer where a flag associated with that block is held. Then in response to initiating a write operation on that data block, messages are sent to all the computers holding that block which resets the said flag, thus informing each computer that the data in that block is no longer valid. These messages are sent using means that perform that flag reset without, in the preferred embodiment, any overhead of interruption of processing on the computers where the flags reside.

Abstract: A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

Abstract: An assigning system and an assigning method are provided for assigning a storage device or a unitary logical unit of the storage device. A VLU-LU correspondence table is provided which shows a correspondence between virtual logical units (VLU) virtually set in a host computer and logical units (LU) of a plurality of storage devices connected to a network. This table stores evaluation items of each storage device such as a delay time and an access frequency. An evaluation unit calculates an evaluation value of each evaluation item in the table, and a unitary logical unit of the storage is assigned in accordance with the evaluation value.

Abstract: A processing system includes a cache controller for managing requests for data from a cache memory by a processor. The cache controller includes an access queue that holds requests for data pending asynchronous retrieval of the requested data from the cache memory, and an exit queue that holds the requested data retrieved from the cache memory until released to the processor. This queuing arrangement allows data lines to be retrieved from cache memory without a pipeline, while latencies are minimized.

Abstract: In a computing system having swappable and non-swappable address spaces, wherein the computing system includes an operating system that includes a Real Storage Manager (RSM), a Systems Resource Manager (SRM) and a Region Control Task (RCT), a method for recovering swappable fixed non-preferred memory is provided which includes receiving a request from the operating system to configure an area of real memory to create an intercepted swappable address space, wherein the intercepted swappable address space includes a flagged fixed frame element identified for configuration, examining the intercepted swappable address space so as to determine if the intercepted swappable address space will remain swappable, requesting the SRM to coordinate the swapping process, quiescing the intercepted address space, generating a first return code responsive to the intercepted swappable address space remaining swappable, communicating the first return code to the RCT so as to cause the RCT to respond to the first return code, in

Abstract: A method and apparatus for detecting a heap smashing condition. A call to a library function, such as a request to write a data block to the heap section of a memory, is intercepted from a program being executed. In an embodiment, a fault-containment wrapper module determines whether performing the write request would smash the heap. If it would smash the heap, an error handling procedure is executed instead of writing the data block. If it would not smash the heap, the fault-containment wrapper module causes the data block to be written to the memory as requested.

Abstract: A method and system are disclosed for managing an allocation of a portion of a memory associated with a central processing unit system that can be selectively coupled to a bus of the central processing unit system. In accordance with exemplary embodiments of the present invention, a first portion of the memory is allocated for a first range of addresses. The allocated first portion of the memory is selectively coupled to the bus of the central processing unit system. The selectively coupled first portion of the memory is decoupled from the bus of the central processing unit system. The decoupled first portion of the memory is reallocated for a second range of addresses.

Abstract: A system, method, and computer program product for detecting a first memory in a first node and detecting a second memory in a second node coupled to the first node. The system, method, and computer program product ensure that a first set of contiguous addresses is mapped to a portion of the first memory where the first set of contiguous addresses each have a value lower than a four gigabyte address, and ensure that a second set of contiguous addresses is mapped to a portion of the second memory where the second set of contiguous addresses each have a value lower than the four gigabyte address.

Abstract: A semiconductor device having a main processor and a coprocessor for data processing is disclosed, the device comprising a main program memory for storing main processor instructions and a first portion of coprocessor instructions, a coprocessor program memory for storing a second portion of coprocessor instructions, and a predecoder for predecoding at least one bit of each instruction fetched from the main program memory and for generating an active coprocessor control signal upon predecoding a coprocessor type instruction, wherein the second portion of coprocessor instructions are fetched directly from the coprocessor program memory and the first portion and the second portion of coprocessor instructions are processed by the coprocessor upon receipt of the active coprocessor control signal.

Abstract: Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions for a signal processor. The unified RISC/DSP pipeline controller is coupled to a program memory, a RISC control unit, and at least one signal processing unit. The program memory stores both DSP and RISC control instructions and the RISC control-unit controls the flow of operands and results between the signal processing unit and a data memory that stores data. The signal processing unit executes the DSP instruction. The unified RISC/DSP pipeline controller generates DSP control signals to control the execution of the DSP instruction by the signal processing unit and RISC control signals to control the execution of the RISC control instruction by the RISC control unit.

Abstract: A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable number of variable-length instructions which may be folded. Folding information for each of the respective set of entries, identifying a number of instructions therein which may be folded (if any) and a size of each instruction which may be folded, is produced by the fold decoders and stored in the first entry of the set, then transmitted to the main decoder for use in folding instructions during decoding.

Abstract: An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.

Abstract: A command processing device includes first and second storing circuits, a decode circuit and a generating circuit. The first storing circuit stores a command. The decode circuit decodes the command from the first storing circuit and outputs a decoded command and a control signal. The generating circuit receives the command from the first storing circuit, generates a new command in response to the control signal, and outputs the new command to the first generating circuit. The second storing circuit stores an original command. The generating circuit receives the original command from the second storing circuit and outputs the original command to the first storing circuit.

Abstract: A method and apparatus for manipulating work queue elements via a hardware adapter and a software driver. The software driver is configured to cause a plurality of work queue elements to be stored in a queue pair including a plurality of storage locations. Each of the plurality of storage locations includes an indicator indicating whether a corresponding work queue element has been completed. The hardware adapter is configured to select one of the plurality of storage locations and to service a corresponding one of the plurality of work queue elements, and in response to completion of a task associated with the corresponding work queue element, to cause the indicator to indicate that the corresponding work queue element has been completed. Additionally, the software driver is configured to cause a new work queue element to be stored in the selected storage location in response to detecting that the indicator indicates that the corresponding work queue element has been completed.

Abstract: A first resume process executed by the BIOS program is divided into two sections. When a resume sub-process, included in the first resume process, for resuming the operating environment of a system core necessary for operating the operating system, has been executed, system control is switched from the BIOS program to the operating system. After that, interrupt processes are inserted while the operating system is executing the second resume process. In the interrupt processes, the BIOS program executes the remaining sub-processes of the first resume process.

Abstract: A method and system of an automated computer video display driver management system in setting up a video driver for a corresponding video display controller adapter is disclosed. The process including the steps of executing an automated driver management program prior to replacing a new controller with an old controller in the system; copying a predetermined program for subsequent execution in a rebooting process to the computer system; invoking command keystrokes in accordance to the version of the operating system being executed in the computer system; setting up reboot registry in the computer system; rebooting the computer system; configuring the computer system with standard video graphics adapter driver upon installing a new video display controller; rebooting the computer system again; and scanning for a second predetermined program for selecting a corresponding software driver for the corresponding video display adapter.

Abstract: A system involving a central computer (2) and a remote computer (3), which can communicate over a link (1), is migrated from in-clear working to encrypted working automatically as the computers receive and install long term keys necessary for encrypted communication. When migration is required, the settings at both ends of the link need to be changed to “encrypt” simultaneously and, particularly, if there are numerous remote computers and the possibility of connection of a remote computer to different central computers, as is possible in virtual private network (VPN) scenarios, severe problems can ensue. Hence, as well as the normal two modes of working “in-clear” and “encrypt”, a third mode in which “initiate encryption” is set at one end of the link and “accept encryption” is set at the other end of the link is proposed.

Abstract: Methods and systems for selectively encrypting and decrypting messages transmitted on a channel of a communication network, such as a broadcast channel, are provided. Group encryption keys are provided for one or more services utilizing the broadcast channel to communicate messages. A message associated with a particular service first receives an error check value, such as a cyclical redundancy check (CRC) value generated from the unencrypted message. The message is then encrypted using the group encryption key for the service and the CRC is added to the encrypted message and transmitted with a broadcast address of the communication network. A receiver then receives the message and determines that the CRC indicates an error (as it is generated from the encrypted message rather than the unencrypted message). The receiver then decrypts the message using the group encryption key for the service (assuming the receiver is authorized to receive the service, i.e.

Abstract: A method of labelling an article, including a) choosing a first character string comprising an identification number chosen to represent an article or a given class of articles, the character string comprising two or more characters, b) expressing each character in said character string as a binary number having seven or more binary digits, c) storing a sequence of binary numbers corresponding to said character string in a data store, and d) attaching the data store to, or incorporating the data store in, an article. The sequence of binary numbers is preferably generated by multiplication of the identification number by an integer, followed by conversion of the resultant number into a base 84 number. The data store preferably comprises anisotropic magnetic particles having a permanent non-random orientation in predetermined spaced regions.

Abstract: A technique for integrating message authentication with encryption and decryption is disclosed. Intermediate internal states of the decryption operation are used to generate a validation code that can be used to detect manipulation of the encrypted data. The technique is optimized with respect to processing time, execution space for code and runtime data, and buffer usage. The technique is generally applicable to a variety of block ciphers, including TEA, Rijndael, DES, RC5, and RC6.

Abstract: A device, method, and system for authenticating devices in a computer system. The device includes a storage location for storing a GUID. The device is configured to provide the GUID to a master in the computer system during a trusted setup. The device is further configured to provide at least an indication of the GUID during a data transaction. The computer system includes a master device and a device comprising a storage location for storing a GUID. The device is configured to provide the GUID to the master device during a trusted setup. The device is further configured to provide at least an indication of the GUID during a data transaction. The method includes providing a GUID and receiving a request for a data transaction. The method also includes transmitting data in the data transaction and at least an indication of the GUID in the data transaction and authenticating the data using at least the indication of the GUID in the data transaction.

Abstract: A central access control system creates distribution CDs using an embedded data encryption process. A disc ID is also encrypted and recorded on each disc of each set of distribution CDs. The central access control system records the disc IDs and a remote location access rights list (ARL). A list of unique remote location IDs are also stored. The distribution CDs are delivered to one or more remote locations equipped with an information access system that includes its unique remote location ID a CD reader with an embedded decryption system, and a communication link to the central access control system. The information access system can send the disc ID and its unique remote location ID as an access request to the central access control system. If the access control system is able to verify and grant the request, a unique decryption key will be sent to access the particular distribution CD currently contained in the information access system.

Abstract: A system and method for enabling broadcast programs to be copied once only by consumer recorders includes writing a unique media identification on each blank disk to which content is to copied in a read-only area of the disk before it is initially recorded. Also, a one-way key management media key block is written to the disk. A content key is derived by combining a media key, derived from the media key block, with the media identification. Additionally, to facilitate copying the content one time only, an exchange key is established between the recorder and a sender such as a satellite receiver or a disk player that is associated with the recorder, and the exchange key is modified with special numbers representing control commands including copy once and copy no more. The exchange key is then encrypted using the content key and then hashed with a nonce to render a bus content key. The bus content key is then used to encrypt the data for copying the data to a disk.

Abstract: An “ownership tag” in a special area of memory of a computer system identifies an owner of the computer system by displaying the ownership tag during initialization of the computer system. The ownership tag may be presented during the installation and execution of the Basic Input Output System (BIOS) preferably during Power on Self Test (POST) process. An administrator may access the ownership tag by interrupting the process by pressing the an appropriate key, which transitions the computer to an administrator set up mode. An administrator able to enter the administrator password may then alter the contents of the protected memory, changing the ownership tag. The ownership tag is preferably stored in a region of memory not accessible to a typical user, but accessible to an administrator aware of the administrator password. The ownership tag is stored in a flash memory, which is very difficult to remove from the system board, or to modify without administrator-level security access.

Abstract: A user-configurable firewall and method in which a user-changeable security setting for a client computer is maintained by an access server through which a user accesses the public network. The user-changeable security setting can be used to specify which outside computers or network devices may access the client computer and what type of access to the client computer is allowed. If an attempt to access the client computer is made, the user-configurable security setting is checked to determine if the attempted access is allowed by the current security setting. If the attempted access is allowed by the current security setting, access is allowed to the client computer; otherwise, access is not allowed. If the user changes the user-configurable security setting, the changes to the user-configurable security setting are provided to the access server.

Abstract: IP security is provided in a virtual private network using network address translation (NAT) by performing one or a combination of the four types of VPN NAT, including VPN NAT type a source-outbound IP NAT, VPN NAT type b destination-outbound, VPN NAT type c inbound-source IP NAT, and VPN NAT type d inbound-destination IP NAT. This involves dynamically generating NAT rules and associating them with the manual or dynamically generated (IKE) Security Associations, before beginning IP security that uses the Security Associations. Then, as IP Sec is performed on outbound and inbound datagrams, the NAT function is also performed.

Abstract: A system for security and authorization processing in digital terminals. The processing load of a security processor (250) at the terminal (150) is reduced by configuring a multiple applications manager (MAM) (240) to determine if frequently-transmitted application data should be downloaded. The security processor is used by the MAM to build a local virtual application table (260) that indicates which applications are authorized for downloading. The security processor configures the terminal with an authorization state so that it knows which applications it is authorized to download, i.e., the applications (316′, 334′, 376′) whose required authorization state correlate with the terminal's configured authorization state. The security processor is accessed when the terminals authorization state changes, or when a required authorization state of an application changes. These events are typically relatively infrequent.

Abstract: A power supply unit controller for a rack enclosure in which a plurality of devices communicate via a backplane is disclosed. The controller reads signal(s) indicative of output supply level(s) being provided to the backplane by a power supply unit associated the the power supply unit controller and stores value(s) associated with the signal(s). The controller further stores a scaling value associated with a respective signal and dependent on the power supply unit, and a power supply unit serial number. The controller is responsive to a request from an SES processor to return a state of the associated power supply unit to the SES processor, the state including a combination of: a summary of the current status of the power supply unit, the value (s), the scaling value(s), and the power supply unit serial number, according to the SES processor request.

Abstract: A device on a source synchronous data bus includes a clock generation circuit which generates transmit and receive clock signals for transmitting and receiving data. The device sends data in quadrature phase relationship with the bus clock signal and receives data in phase with the bus clock signal.

Abstract: In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.

Abstract: A processor-based system such as a workstation or server, using a system clock provided through a phase-locked loop (PLL) to a clock gate and then to a clock tree, which distributes the core system clock to components in the processor-based system, including a host bridge circuit. The host bridge distributes control signals to a receiving device such as a memory module, which may use a continued clocking signal when the system enters a low-power mode. A feedback clock for the PLL is provided to the receiving devices during low-power mode to ensure continued clocking, when the clock gate output is low and the clock tree is thereby disabled. A skew compensation circuit coordinates clocking in the continued clock and the core system clock.

Abstract: An object of the present invention is to enable precise and easy adjustment of clock skew. A clock distribution circuit is designed and the placement and routing of the entire chip including the clock distribution circuit follows. Then the clock skew value is calculated and whether the calculated clock skew exceeds a target value is checked. When the clock skew exceeds the target value, the outputs of some driver elements are disconnected or connected to adjust the clock skew. The steps disconnecting or connecting the outputs of the drivers are repeated until the clock skew becomes equal to or smaller than the target value.

Abstract: A mechanism is provided for predicting cache array bit line or driver failures. This mechanism checks for five consecutive errors at different addresses within the same syndrome on invocation of event scan polling to characterize the failure. Once the failure is characterized, it is reported to the system for corrective maintenance including dynamic and/or boot time processor deconfiguration or preventive processor replacement.

Abstract: When performing mirrored disk restores, including both disk level mirrored restores and file level mirrored restores, rather than first restore data to a mirror disk and later move that data to the primary disk, the data on the primary disk is first copied to the mirror disk, and thereafter, the data is restored from the backup storage device to the primary disk, independent of the mirror disk.

Abstract: A system for indicating and determining a master unit from a plurality of logic units is described. The system includes a first logic unit configured to output a first obey signal and receive a first input signal, and a second logic unit configured to output a second obey signal and receive a second input signal. At least one of the first obey signal and the second obey signal is clocked, and a phase relationship of the second obey signal relative to the first obey signal is controllable by the first and second input signals. The system also includes a mastership determination logic unit configured to monitor the first and second obey signals. The mastership determination logic unit is configured to indicate that the first logic unit is the master unit when only the first obey signal is being clocked and to indicate that the second logic unit is the master unit when only the second obey signal is being clocked.

Abstract: Provided is a system and method for detecting marginal data transmissions from any of a number of security devices in a security system including a control unit in communication with the security devices over a serial data communications loop. First, the control unit receives a data transmission from a security device, wherein the data transmission includes a number of bit intervals in which a logic 1 level is assumed by the control unit unless a logic 0 level is detected by the control unit. The control unit samples the data transmission at a first predetermined time during the bit interval to obtain a first sample value, and then it samples the data transmission at a second predetermined time during the bit interval to obtain a second sample value (the second predetermined time being later than the first predetermined time). If the first sample value is a logic 1 and the second sample value is a logic 0, this indicates that the data transmission from the security device is marginally recoverable.

Abstract: A module is provided to support online cache diagnostics in a Linux operating system. The module is dynamically loaded to a kernel of the operating system. Upon activation, the module allocates memory for a user level program and a manager maps a contiguous buffer of memory from a kernel address space to a user process address space. The buffer is contiguous in both the physical and virtual address space. Physical memory displacement between access is controlled from the user level. Accordingly, the module enables allocation of contiguous lines of memory from the kernel to the user space in which control of the memory displacement occurs at the user level.

Abstract: A computer system includes instruction fetch circuitry, decode circuitry to decode instructions and identify any registers to be used and dispatch circuitry to dispatch instructions to one or more execution units, said system including emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions, the computer circuitry further comprising a register watch store for identifying one or more registers to be watched, comparator circuitry for comparing registers identified by said decode circuitry with registers identified in said register watch store and providing a hit signal for hits in the comparison, and instruction insertion circuitry responsive to hit signals to insert in the instruction sequence to an execution unit a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data regist

Abstract: A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.

Abstract: A method and apparatus for maintaining consistent data is described. A computer implemented method comprises generating a first command for a set of network data to be executed on a local memory, executing a second command for the set of network data on a remote memory in response to generation of the first command, determining whether the second command has been executed successfully on the remote memory, executing the first command on the local memory upon determining the second command is executed successfully, and generating an error upon determining the second command is not executed successfully.

Abstract: In an electronic control unit for an anti-lock brake control system, a microcomputer communicates data to a peripheral IC. The peripheral IC monitors a fault of the microcomputer based on data received from the microcomputer. The monitoring operation may be executed by measuring an interval of calculation, calculation result and sequence of data transmitted from the microcomputer.