Abstract: A system (10) for imaging a combustion turbine engine airfoil includes a camera (12) and a positioner (24). The positioner may be controlled to dispose the camera within an inner turbine casing of the engine at a first position for acquiring a first image. The camera may then be moved to a second position for acquiring a second image. A storage device (30) stores the first and second images, and a processor (32) accesses the storage device to generate a composite image from the first and second images. For use when the airfoil is rotating, the system may also include a sensor (40) for generating a position signal (41) responsive to a detected angular position of an airfoil. The system may further include a trigger device (42), responsive to the position signal, for triggering the camera to acquire an image when the airfoil is proximate the camera.

Abstract: In a first aspect, an apparatus is provided for detecting substrates. The apparatus includes (1) a transmitter/receiver unit adapted to transmit a light beam through a substrate located within a transfer chamber; (2) a reflector adapted to receive the light beam transmitted from the transmitter/receiver unit and to reflect the transmitted light beam toward the transmitter/receiver unit; and (3) a controller coupled to the transmitter/receiver unit and adapted to determine whether a substrate is positioned between the transmitter/receiver unit and the reflector based on an intensity of the reflected light beam received by the transmitter/receiver unit. At least one of the transmitted and reflected light beams is adapted to strike a substrate positioned between the transmitter/receiver unit and the reflector with non-normal incidence. Numerous other aspects are provided.

Abstract: This invention discloses novel device structures for full color flat panel displays utilizing pseudomorphically cladded quantum dot nanocrystals. Different colors are obtained by changing the core size and composition of the quantum dots while maintaining a nearly defect-free lattice at the core-cladding interface. Light emission from the quantum dot core is obtained either by injection or by avalanche electroluminescence. A nanotip emitter device is also presented. These generic devices can be addressed using a variety of conventional display drivers, including active and passive matrix configurations.

Abstract: Provided are a semiconductor device having a superlattice semiconductor layer and a method of fabricating the same. The semiconductor device includes a superlattice semiconductor layer in which first material layers and second material layers formed of different materials are alternately stacked. A plurality holes are formed in the first material layers and the second material layers forming a superlattice structure, and the holes are filled with materials of the adjacent material layers. The provided superlattice structure reduces a driving voltage by transferring charges through the holes in the first material layers and the second material layers while maintaining a predetermined optical confinement characteristic.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3–10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: A semiconductor optical device having a substrate having a surface of a first semiconductor having a first lattice constant; and a semiconductor lamination layer formed on the substrate, the semiconductor lamination layer having an active layer which contains quantum dots of a first kind made of a second semiconductor having a second lattice constant in bulk state smaller than the first lattice constant. The active layer may contain quantum dots of a second kind made of a third semiconductor having a third lattice constant in bulk state larger than the first lattice constant. The quantum dots of the first and second kinds are preferably disposed alternately along the thickness direction between the barrier layers having the first lattice constant.

Abstract: High quality epitaxial layers of piezoelectric monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the piezoelectric monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying piezoelectric monocrystalline material layer.

Abstract: A polymer-based field effect transistor photosensitive to incident light, which may enhance the transistor's characteristics and controlling parameters of the transistor state. The transistor is comprised of a metal-insulator-semiconductor structure with the insulating and semiconducting layers made of a polymeric media. The semiconducting polymer which also is photoconducting, forms the charge transport layer between the source and drain. The transistor exhibits large photosensitivity indicated by the sizable changes in the drain-source current, by a factor of 100–1000 even at low levels of light with illumination of approximately 1 mlux. The photosensitivity of the transistor is further enhanced with introduction of dilute quantity electron acceptor moieties in the semiconducting polymer matrix. Several applications of the light-responsive polymer-transistor are disclosed, such as use as a logic element and as a backbone of an image sensor.

Abstract: Disclosed are memory devices with high data reading and writing speed along with capabilities for long term storage and high information density. The memory devices allow storage of several bits of data, have fast resistance switching and require low operating voltage but at the same time allow to combine its manufacturing technology with the modern semiconductor manufacturing technology. An exemplary implementation option of the memory cell contains two continuous electrodes between which there is a multilayer functional zone consisting of one active layer, one barrier layer and one passive layer.

Abstract: An organic semiconductor device includes an organic semiconductor layer with carrier mobility which is deposited between a pair of electrodes facing each other. At least one of the electrodes includes a carrier relay layer which is in contact with the organic semiconductor layer and has a work function close or equal to an ionized potential of the organic semiconductor layer, and a conductive layer which is formed on the carrier relay layer and has lower resistivity than the carrier relay layer.

Abstract: An active matrix organic electroluminescence display device capable of maintaining the brightness of the organic light emitting diode. The active matrix organic electroluminescence display device comprises a thin film transistor and an organic light emitting diode. By improving the structure of the passivation layer of the thin film transistor to reduce the leakage current occurring in the TFT, the brightness of the organic light emitting diode can be stably maintained.

Abstract: An electronic device includes a substrate, a structure having openings, and a first electrode overlying the structure and lying within the openings. From a cross-sectional view, the structure, at the openings, has a negative slope. From a plan view, each opening has a perimeter that may or may not substantially correspond to a perimeter of an organic electronic component. The portions of the first electrode overlying the structure and lying within the openings are connected to each other. In a process for forming the electronic device, an organic active layer may be deposited within the opening, wherein the organic active layer has a liquid composition.

Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.

Abstract: Image display panel of the “top-emitting” OLED type having, on the internal face of the front plate, which plate faces the observer, an array of cavities or grooves that are distributed between the light-emitting cells and contain an absorbent agent intended to absorb, in particular, traces of oxygen and/or water vapor liable to degrade the organic electroluminescent cells. The lifetime of the panels is thereby improved.

Abstract: Disclosed are a GaN based compound semiconductor light emitting diode (LED) and a manufacturing method therefor. In the LED, a combination of a light extraction layer and an adaptive layer is formed over a multi-layer epitaxial structure,wherein the light extraction layer is a light transmissible impurity doped metal oxide and the adaptive layer is a Ni/Au layer used to enhance ohmic contact between the light extraction layer and the multi-layer epitaxial structure.

Abstract: A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a method for manufacturing an active matrix type light emitting device and the configuration of such an active matrix type light emitting device having high reliability. In the method, a contact hole extending to a source region or a drain region is formed, and then an interlayer insulation film made of a photosensitive organic insulating material is formed on an interlayer insulation film. The interlayer insulation film has a curved surface on its upper end portion. Subsequently, an interlayer insulation film provided as a silicon nitride film having a film thickness of 20 to 50 nm is formed by a sputtering method using RF power supply.

Abstract: A number of red LEDs, green LEDs, and blue LEDs are mounted on one surface of a polygonal flexible multilayer substrate. The LEDs are connected in series according to color. A red feeder terminal, a green feeder terminal, a blue feeder terminal, and a common terminal are provided on each of at least three sides of the periphery of the flexible multilayer substrate. Circuit patterns for connecting LEDs at the high-potential end of the red, green, and blue series-connected LEDs respectively to the red feeder terminals, green feeder terminals, and blue feeder terminals are provided to the flexible multilayer substrate. Also, a circuit pattern for connecting LEDs at the low-potential end of the red, green, and blue series-connected LEDs all to the common terminals is provided to the flexible multilayer substrate.

Abstract: A high performance, highly reflective ohmic contact, in the visible spectrum (400 nm–750 nm), has the following multi-layer metal profile. A uniform and thin ohmic contact material is deposited and optionally alloyed to the semiconductor surface. A thick reflector layer selected from a group that includes Al, Cu, Au, Rh, Pd, Ag and any multi-layer combinations is deposited over the ohmic contact material.

Abstract: A guide plate 30 has a back face 34 provided with a great number of micro-reflectors 90 which has a guide portion and a conversion output portion including a valley. The conversion output portion reflects twice input light P at inner slopes, generating inner output light Q directed obliquely as to be distant from an incidence end face 32. Inner output light Q is inner-incident to a slope of projection row PR on an emission face 33, with the result that some of the inner-incident light becomes a direct escaping light and much of the other reaches the emission face 33 again after travelling along various paths. At the second time or later chances of escaping, an actual escaping occurs to generate an indirect escaping light. A mixed emission suitably blended of the direct and indirect light is directed to directions, which are modified to directions around a roughly frontal direction by prism sheet PS before being supplied to a LCD panel or the like to be illuminated.

Abstract: A front substrate for a plasma display panel (PDP) and an associated fabrication method are provided. An upper dielectric layer of the front substrate includes a colorant, which causes the dielectric layer to also act as a color filter. The resulting front substrate enhances at least one of color temperature, color purity, or contrast of the PDP without increasing complexity or cost.

Abstract: A heterojunction bipolar transistor (HBT), comprises a collector formed over a substrate, a base formed over the collector, an emitter formed over the base, and a tunneling suppression layer between the collector and the base, the tunneling suppression layer fabricated from a material that is different from a material of the base and that has an electron affinity equal to or greater than an electron affinity of the material of the base.

Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.

Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

Abstract: A semiconductor device includes spaced-apart first and second element formation regions which are formed in a main surface of a semiconductor substrate, a dielectric film which is formed on the main surface of the semiconductor substrate at a location between the first and second element formation regions, first electrode patterns which are formed above the first and second element formation regions respectively and each of which has an end portion extended to overlie the dielectric film, the first electrode patterns being formed by patterning of a first electrode layer, second electrode patterns formed above the first electrode patterns respectively, and a passivation film which is formed above the first electrode patterns to be positioned adjacent to the second electrode patterns while covering part of the dielectric film which is exposed during patterning of the first electrode layer.

Abstract: There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.

Abstract: A magnetic memory device, in which a tunnel magneto resistance element that establishes a connection between a write word line (first interconnection) and a bit line (second interconnection) is provided within a region in which the write word line and the bit line cross in a grade-separated manner. The magnetic memory device comprises a through hole that is provided in such a manner that is insulated from the write word line and also extending through the write word line so as to establish a connection between the tunnel magneto resistance element and a second landing pad (interconnection layer) lower than the write word line, and a contact that is formed in the through hole through a side wall barrier film so as to establish a connection between the tunnel magneto resistance element and the second landing pad.

Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

Abstract: The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

Abstract: An integrated semiconductor memory is disclosed having selection transistors which can be formed at a respective ridge. The ridge can be arranged on an insulation layer. In the ridge the first source/drain region can be formed at one lateral end of the ridge and the second source/drain region can be formed at another lateral end of the ridge. The longitudinal sides of the ridge and a top side of the ridge can be covered with a layer stack including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.

Abstract: A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

Abstract: The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate 10; first insulation films 42 covering the top surfaces and the side surfaces of gate electrodes 20 of the memory cell transistors; through-holes 40 opened on first diffused layers 24; a second insulation film 36 with through-holes 40 opened on first diffused layers 24 and through-holes 38 opened on second diffused layers 26 formed in; capacitors formed on the inside walls and the bottoms of the through-holes 40 and including capacitor storage electrodes 46, connected to the first diffused layers 24; capacitor dielectric films 48 covering the capacitor storage electrodes 46, and capacitor-opposed electrodes 54 covering at least a part of the capacitor dielectric films 48; and, contact conducting films 44 formed on the inside walls and bottoms of the through-holes 38, and connected to the second diffused layers.

Abstract: Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Abstract: A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.

Abstract: This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step.

Abstract: A self-aligned source structure is disclosed by the present invention, in which a p-body diffusion region is formed in an n? epitaxial silicon layer on an n+ silicon substrate through a patterned window; a p+ diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sidewall dielectric spacer being formed over and on a silicon nitride layer; an n+ source diffusion ring is formed in a surface portion of the p-body diffusion region and on an extended portion of the p+ diffusion region through a second self-aligned implantation window formed between the silicon nitride layer and a masking layer surrounded by the first sidewall dielectric spacer; and a self-aligned source contact window is formed on the n+ source diffusion ring surrounded by a second sidewall dielectric spacer and on the p+ diffusion region surrounded by the n+ source diffusion ring.

Abstract: A finFET (100) having sidwall spacers (136, 140) to suppress parasitic devices in the upper region of a channel and at the bases of source(s) and drain(s) that are artifacts of the fabrication techniques used to make the finFET. The FinFET is formed on an SOI wafer (104) by etching through a hardmask (148) so as to form a freestanding fin (120). Prior to doping the source(s) (124) and drain(s) (128), a layer (156) of thermal oxide is deposited over the entire finFET. This layer is etched away so as to form the sidewall spacers at each reentrant corner formed where a horizontal surface meets a vertical surface. Sidewall spacers (136) inhibit doping of the upper region of source(s) and drain(s) immediately adjacent the gate. Sidewall spacers (140) fill in any undercut regions (144) of BOX layer (116) that may have been formed during prior fabrication steps.

Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.

Abstract: In an I/O circuit unit located in the periphery of a semiconductor chip, a plurality of ESD protection transistors are provided in each I/O cell. An electrode pad cell has a two-layer structure including a lower electrode pad and an upper electrode pad. The electrode pad cell is arranged so as to be present over a connection line of ESD protection transistors of an associated I/O cell. With part of the first pad portion of an adjacent electrode pad located in an end portion of the second pad portion of the electrode pad, the second pad portion can not extend further onward but the third pad portion having a smaller width than that of the second pad portion is arranged onward. Thus, destruction of the ESD protection transistors is not caused, so that an internal circuit is protected from an electrostatic discharge which comes into electrode pads.

Abstract: A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSiy film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0?y<1.

Abstract: Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.

Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. At least one free layer has a high perpendicular anisotropy. The high perpendicular anisotropy has a perpendicular anisotropy energy that is at least twenty and less than one hundred percent of the out-of-plane demagnetization energy.

Abstract: Provided is a light coupling apparatus that forms an etch structure complex comprising a total reflection surface/an anti-reflection surface within a substrate to improve coupling efficiency with incident light and responsivity of a photodetector device, whereby a surface-illuminated photodetector or an edge-coupled photodetector are all integratable, and it is possible to reduce the degree of difficulty during packaging and to improve the responsivity of the photodetector at low costs.

Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

Abstract: A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed within an epitaxial tub of a first conductivity type formed within a dielectric material and comprises a surface diffusion region of a second conductivity type, opposite that of the first conductivity type, extending into the epitaxial tub, a trench surrounding and electrically isolating the epitaxial tub, a metallization line coupled to the surface diffusion traversing the semiconductor device and the trench, a first field limiting diffusion region of the second conductivity type disposed between the surface diffusion region and the trench and below the metallization line, a poly field plate positioned over the trench and beneath the metallization line, and a first contact coupled to the field limiting diffusion region, the first contact extending below the metallization line and overlapping the poly field plate.

Abstract: A dielectric separation type semiconductor device having high voltage withstanding capability includes a primary dielectric layer (3-1) on a first surface of a semiconductor substrate (1), a first conductivity type first semiconductor layer (2) disposed oppositely to the substrate (1) with the primary dielectric layer (3-1) sandwiched, a first conductivity type second semiconductor layer (4) on the first semiconductor layer (2), a second conductivity type third semiconductor layer (5) surrounding peripherally the first semiconductor layer (2), a ring-like insulation film (9) surrounding peripherally the third semiconductor layer (5), a first electrode (6) on the second semiconductor layer (4), a second electrode (7) on the third semiconductor layer (5), a back-surface electrode (8) deposited on a second surface of the substrate (1), and a first auxiliary dielectric layer (3-2) disposed immediately below the second semiconductor layer (4), being junctioned to the second surface.

Abstract: A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer).