Abstract: A method of forming a memory array includes forming a stack of two or more layers of memory material on a substrate, each layer of memory material having an array of memory cells, and forming one or more contacts that pass through each of the layers of memory material.

Abstract: It is an object of the present invention to eliminate a color deviation possibly caused by a film formation failure in an organic layer of organic EL devices, thereby improving product yield. A method of manufacturing organic EL devices according to the invention comprises: a pre-treating step for forming lower electrodes and the like on a substrate, a film formation step to be performed after the pre-treating step for forming on the lower electrodes an organic layer containing at least an organic luminescent layer and also forming upper electrodes thereon, and a sealing step to be performed after the film formation step for sealing up the organic layer and the upper electrodes, characterized in that an inspection step is performed after the pre-treating step but before the formation of the upper electrodes.

Abstract: On the surface of a substrate 1, a precursory buffer layer 2? composed of an In-base compound or a Zn-base compound, not contained in the substrate 1, is formed so as to be stacked thereon as a polycrystal layer or an amorphous layer. Before a light emitting region is formed, the precursory buffer layer 2? is annealed for re-crystallization to thereby convert it into a buffer layer 2. This successfully provides a Zn-base semiconductor light emitting device which can readily be fabricated and capable of improving quality of the light emitting region, and a method of fabricating the same.

Abstract: A method is provided to control the height of bump electrodes and increase a clearance between edge sections of a semiconductor chip and lead terminals of a tape substrate. By applying suction to a tape substrate through a suction groove, boundary portions of a semiconductor chip mounting region are drawn into the suction groove, and curved sections are formed in the tape substrate at locations corresponding to edge sections of a semiconductor chip.

Abstract: An elongated strip of a sheetlike substrate bearing microelectronic elements such as semiconductor chips is advanced in a downstream direction through one or more folding stations where successive portions of the substrate are folded so as to form a strip including a plurality of fold packages, each including confronting top and bottom runs and a fold region with one or more of the runs bearing one or more microelectronic elements. The strip incorporating the plural fold packages can be wound on a reel or otherwise handled, stored and shipped to a subsequent manufacturing operation, where individual fold packages can be severed from the strip.

Abstract: Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of microelectronic dies on and/or in the substrate. The individual dies include integrated circuitry and pads electrically coupled to the integrated circuitry. The method then includes depositing an underfill layer onto a front side of the substrate. The method also includes selectively forming apertures in the underfill layer to expose the pads at the front side of the substrate. The method further includes depositing a conductive material into the apertures and in electrical contact with the corresponding pads. In one aspect of this embodiment, the underfill layer is a photoimageable material.

Abstract: A substrate sheet material for semiconductor device and manufacturing method thereof and a manufacturing method of a semiconductor device using the substrate sheet material can suppress and reduce a warp which may occur in the substrate sheet material even when a plurality of semiconductor chips formed in the substrate sheet material are molded all at once. A plurality of substrates to be used for producing semiconductor packages are formed in the substrate sheet material. An outer configuration of the substrate sheet material is made into a circular shape.

Abstract: A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and readouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.

Abstract: The present invention provides an epoxy resin composition for packaging a semiconductor device, characterized in having improved mold releasability during a molding process, continuous-moldability and improved solder resistance. According to the present invention, there is provided an epoxy resin composition for packaging the semiconductor element, obtained by formulating: (A) an epoxy resin; (B) a phenolic resin; (C) a curing accelerator; (D) an inorganic filler; and (E) an oxidized polyethylene wax having a drop point within a range of from 60 to 140 degree C., an acid value within a range of from 10 to 100 (mg KOH/g), a number average molecular weight within a range of from 500 to 20,000, and a mean particle size within a range of from 5 to 100 ?m, wherein at least one of (A) epoxy resin and (B) phenolic resin is a novolac structured resin having biphenylene structure, and wherein content of (E) oxidized polyethylene wax in epoxy resin composition is within a range of from 0.01 to 1 % wt.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: An active matrix substrate includes a substrate composed of resin, and a polysilicon thin film diode formed on the substrate. The polysilicon thin film diode may be a lateral diode centrally having a region into which impurity is doped. As an alternative, the polysilicon thin film diode may be comprised of two lateral diodes electrically connected in parallel to each other and arranged in opposite directions.

Abstract: To provide a manufacturing method for a field-effect transistor, such as a thin-film transistor, enabling reductions in the number patterning steps and the number of photomasks and improvements in the throughput and the yield. In the method, an oxide film is formed by processing the surface of a crystalline semiconductor with ozone water or hydrogen peroxide water. Using the oxide film thus formed as an etch stop, a gate electrode, a source electrode, and a drain electrode of the field-effect transistor are simultaneously formed from a same starting film in one patterning step by use of one photomask. After forming the gate electrode, the source electrode, and the drain electrode, heating is performed thereon at 800° C. or higher for a predetermined time. Thereby, the contact resistances between the source electrode and the crystalline semiconductor and between the drain electrode and the crystalline semiconductor are reduced, whereby improving the electrical conductivity.

Abstract: A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on a periphery area of the semiconductor substrate, stacking first to third insulating layers over the substrate, forming a spacer on a sidewall of the third conductor pattern in the exposed periphery area, removing the third insulating layer, and forming first and second spacers on sidewalls of the first and second conductor patterns.

Abstract: A high-precision patterning is conducted with a half-tone resist thickness being prevented from varying due to the presence/absence of a base film. A transmitting portion and two kinds of semi-transmitting portions, providing different quantities of transmitted light, are provided in a photomask for exposing a resist, and a smaller-transimitting-light-quantity semi-transmitting portion is used in a base film-present area and a large-transmitting light-quantity semi-transmitting portion is used in a base-film-free area to regulate luminous exposure while exposing, thereby forming a half-tone resist having uniform thickness.

Abstract: A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed.

Abstract: A semiconductor device including an NMOSFET which has an n-type source/drain main region containing arsenic and an n-type source/drain buffer region having arsenic and phosphorous of which a concentration is lower than that of the source/drain main region, and the concentration of the phosphorous in the source/drain buffer region is smaller than the concentration of the arsenic therein. The semiconductor device has a suppressed reverse short channel effect and reduced p-n junction leakage current. Further, the semiconductor device has a larger margin to a certain gate length and a specified threshold voltage to elevate a production yield.

Abstract: Fabrication methods for thin film transistors. A metal gate stack structure is formed on an insulating substrate. The substrate is performed using thermal annealing to create an oxide layer on the sidewalls of the metal gate stack structure. A gate insulating layer is formed on the substrate covering the metal gate stack structure. A semiconductor layer is formed on the gate insulating layer. A source/drain layer is formed on the semiconductor.

Abstract: Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

Abstract: A method for fabricating a semiconductor memory device in which a logic circuit and a nonvolatile memory are provided on a semiconductor substrate includes the steps of: forming an isolation region; forming a protective film made of an insulating material over the semiconductor substrate in a logic circuit region and a nonvolatile memory region; selectively introducing impurity ions in part of the semiconductor substrate in the logic circuit region; and removing the protective film formed over the logic circuit region. The step of introducing the impurity ions is performed before the step of removing the protective film is performed.

Abstract: A process of the invention for fabricating a capacitor element includes the steps of forming a dielectric coating on a surface of an anode body and a surface of lower part of a projecting portion of an anode lead member implanted in the anode body, forming a precoat layer of an electrically conductive high polymer on the dielectric coating, exposing an area of the surface of the lower part in an annular form by partly removing the dielectric coating and the precoat layer, forming an electrically conductive high polymer layer on the precoat layer using an electrolytic polymerization process by immersing the anode body in a solution of a monomer so as to position said area of the surface of the lower part at the liquid level of the solution, and deburring the conductive high polymer formed on said area of the surface of the lower part.

Abstract: The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench formed in a semiconductor, the a-Si or polysilicon is exposed to hydrogen at an elevated temperature.

Abstract: The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

Abstract: A semiconductor device comprising: a first insulation film 60 formed above a base substrate 10; a second insulation film 61 formed on the first insulation film and having different etching characteristics from the first insulation film; and a capacitor 79 including a storage electrode 68 formed on the second insulation film, projected therefrom, the storage electrode being formed, extended downward from side surfaces of the second insulation film. The lower ends of the storage electrodes are formed partially below the etching stopper film, whereby the storage electrodes are fixed by the etching stopper film. Accordingly, the storage electrodes are prevented from peeling off in processing, such as wet etching, etc. The semiconductor device can be fabricated at high yields.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: Disclosed is a method for manufacturing a flash memory cell. A structure in which a floating gate, an ONO dielectric film and a control gate are stacked is formed by means of a gate mask process and an etch process. After a rapid thermal nitrification process is performed, a re-oxidization process is performed. Therefore, Si-dangling bonding broken during the gate etch process becomes a Si—N bonding structure by means of a rapid thermal nitrification process. As such, as abnormal oxidization occurring at the side of an ONO dielectric film during a re-oxidization process is prohibited, a smiling phenomenon of the ONO dielectric film is prevented.

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

Abstract: A method of manufacturing a flash memory device, including the steps of forming a floating gate electrode that is a doped polysilicon film on a semiconductor substrate, forming a polysilicon layer in the pattern of HSG on the doped polysilicon film, conducting a nitrifying process after forming the HSG polysilicon layer, forming an Al2O3 film on the resultant structure treated by the nitrifying process, and forming a control gate electrode on the Al2O3 film.

Abstract: The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

Abstract: The method of manufacturing a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate through a gate insulated film; forming source/drain regions to be adjacent to the gate electrode forming an Al wiring through an interlayer insulating film covering the gate electrode; and implanting impurity ions into a surface of the semiconductor substrate using as a mask the Al wiring and a photoresist formed thereon, thereby writing information into each of elements constituting a mask ROM and changing an outputting manner at an output port.

Abstract: Consistent with an example embodiment according to the invention, a material for the intermediate layer is chosen which can be selectively etched with respect to the dielectric layer. Before the deposition of the first conductor layer, the intermediate layer is removed at the location of the first channel region, and after the deposition of the first conductor layer and the removal thereof outside the first channel region and before the deposition of the second conductor layer, the intermediate layer is removed at the location of the second channel region. Thus, field effect transistors (FETs) are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer is deposited on the intermediate layer which can be selectively etched with respect thereto.

Abstract: A method for making a power device produces a power device comprising active cells having designs that vary depending on where they are located in the active area. Design variations include structural variations and variations in the material used to produce the cells.

Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

Abstract: A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.

Abstract: A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.

Abstract: A thyristor-based memory device may comprise a commonly-implanted base region, in which a common emitter region may be implanted for the left and the right thyristors in a mirror-image pair. The implanting of the base region may include directing the dopant toward a semiconductor material through a window defined by sidewalls formed in a conditioned masking material over the semiconductor material. The resulting base and emitter regions may be substantially symmetrical about a central boundary plane. In relation to the symmetry, one thyristor may be operable with a minimum holding current within about 10 percent of that for the other thyristor in the mirror-image pair.

Abstract: A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.

Abstract: A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16) of the regions of sacrificial material. A discrete charge storage layer (28) overlies the substrate and is between the regions of sacrificial material. In one form a control electrode (34) is formed per memory cell overlying the substrate with an underlying substrate diffusion and laterally adjacent one of the regions of sacrificial material. A third substrate diffusion (60) is positioned between the two control electrodes. In another form two control electrodes are formed per memory cell with a substrate diffusion underlying each control electrode. In both forms a select electrode (64) overlies and is between both of the two control electrodes.

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Abstract: After a capacitor device including a lower electrode, a capacitor dielectric film made from a ferroelectric film and an upper electrode is formed on a substrate, an insulating film covering the capacitor device is formed. Subsequently, the capacitor device covered with the insulating film is annealed for crystallizing the ferroelectric film.

Abstract: A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1?x?yCy, where 0.70<x<0.95 and y<0.05. Next, at the location of the field isolation regions to be formed, windows (9) are formed in the auxiliary layer and trenches (11) are formed in the silicon body. Next, on the walls (12) of the trenches, a silicon oxide layer (13) is provided and on the walls (10) of the windows a silicon oxide layer (14) is provided, both being formed by an oxidation treatment. The auxiliary layer is not oxidized throughout its thickness.

Abstract: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract: A method for producing an ultra-thin semiconductor chip and an ultra-thin back-illuminated solid-state image pickup device utilizing a semiconductor layer formed on a support substrate via an insulating layer to improve separation performance of a semiconductor layer from a support substrate and thereby improve the productivity and quality. The method uses two porous peeling layers on opposite sides of a substrate to produce an ultra-thin substrate.

Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

Abstract: Disclosed is a method for gettering a transition metal impurity diffused in a silicon crystal at ultra high-speeds to form deep impurity levels therein. The method comprises codoping two kinds of impurities: oxygen and carbon, into silicon, and thermally annealing the impurity-doped silicon to precipitate an impurity complex of an atom of the transition metal impurity, the C and the O, in the silicon crystal, so that the transition metal impurity is confined in the silicon crystal to prevent the ultra high-speed diffusion of the transition metal impurity and electrically deactivate deep impurity levels to be induced by the transition metal impurity.

Abstract: An implant is performed in the P channel regions, while masking the N channel regions, to deeply amorphize a layer at the surface of a semiconductor layer. After this amphorization step, germanium is implanted into the amorphized layer. The germanium is implanted to a depth that is less than the amorphization depth. This germanium-doped layer that is amorphous is heated so that it is recrystallized. The recrystallization results in a semiconductor layer that is silicon germanium (SiGe) and compressive. P channel transistors are then formed in this recrystallized semiconductor layer. This process can also be applied to the N channel side while masking the P channel side. In such case the implant would preferably be carbon instead of germanium.

Abstract: Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.