Abstract: Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film pattern stacked sequentially; forming an ion implantation buffer film on an exposed surface of the semiconductor substrate and the gate conductive film pattern; performing a first ion implantation process for injecting fluorine ions into the semiconductor substrate; performing a second ion implantation process for implanting p-type halo ions into the semiconductor substrate; performing a third ion implantation process for implanting n-type impurity ions into the semiconductor substrate; and diffusing the p-type halo ions and the n-type impurity ions using a thermal process.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).

Abstract: A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: An integrated circuit package is processed by electroplating the integrated circuit package. The electroplating is performed without forming plating traces on a conductive surface of a pad side of the integrated circuit package. Pad areas of the integrated circuit package are thus plated with one or more materials. An integrated circuit may be electrically coupled to pad areas on the integrated circuit package. The integrated circuit package can be electroplated by using the one or more current sources coupled to a back plane of the integrated circuit package. The back plane is patterned, wherein the patterning of the back plane occurs after the step of electroplating.

Abstract: An electronic circuit unit contains electrodes to which bumps of a semiconductor chip are adhered. The electrodes are arranged on an upper surface of a circuit board. Land units to which chip parts is soldered are arranged on a rear surface of the circuit board. such that an insulating plate which is on the rear surface of the circuit board is supported by a supporting jig during a mounting process of the semiconductor chip, and the circuit board is not tilted. Therefore, an electronic circuit unit ensuring that the semiconductor chip is mounted with a reliable mounting capability can be obtained.

Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Abstract: Metal traces and solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste material. The solder paste material is then formed into precisely controlled ball shapes and metal trace geometries.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one aspect, the present invention provides a semiconductor device having a dielectric layer located over a conductive feature and a conductive via located within the dielectric layer and contacting the conductive feature. The semiconductor device, among other elements, may further include a dummy conductive via located proximate the conductive via and contacting the conductive feature. One of the intents of the dummy conductive via is to attempt to trap vacancies associated with the conductive feature or the conductive via.

Abstract: Various methods are provided for forming metal interconnection layers of semiconductor devices.

Abstract: A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

Abstract: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering ±40° C. of a temperature at which a stress migration is most accelerated.

Abstract: There is provided a method of manufacturing a semiconductor device that can reduce the number of processes, and decrease contact resistance between plugs. The method comprises forming a first interlayer dielectric film having a first opening where a contact plug is to be formed; uniformly forming a first conductive layer on the first interlayer dielectric film and in the first opening; forming a resist defining an interconnect pattern by a lithography process on a region excluding the first opening; performing first anisotropic etching to remove a region of the first conductive layer not covered with the resist until an upper face of the first interlayer dielectric film is exposed, thus to form an interconnect and the contact plug.

Abstract: A semiconductor device includes a highly reliable multi-level interconnect structure having a low effective dielectric constant and which can be easily manufactured with a relatively inexpensive process, and a method for manufacturing the semiconductor device. The semiconductor device includes a lower-level interconnect and an upper-level interconnect, each surrounded by a barrier layer, and a via plug surrounded by a barrier layer and electrically connecting the lower-level interconnect and the upper-level interconnect.

Abstract: A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

Abstract: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material.

Abstract: A semiconductor device and method of manufacture thereof. A porous dielectric material is deposited over a workpiece. The porous dielectric material is patterned, and a photosensitive material is spun-on over the patterned porous dielectric material. A portion of the photosensitive material is formed over, and/or soaks into sidewalls of the porous dielectric material pattern, forming a barrier region of photosensitive material. The photosensitive material is developed, leaving the sidewalls of the porous dielectric material pattern sealed by the barrier region of photosensitive material. A liner is deposited over the porous dielectric material, and a conductive material such as copper is used to fill the pattern in the porous dielectric material. Diffusion of copper into the pores of the porous dielectric material is prevented by the barrier region.

Abstract: A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and embedded SiGe in source and drain regions. Second sidewall spacers are formed on the first sidewall spacers, these second sidewall spacers consisting of a material different from the cap material. The cap is stripped from the top of the gate with an etchant that selectively etches the cap material and not the second sidewall spacer material.

Abstract: A process for photoresist layer removal from a semiconductor wafer comprises exposing at relatively high temperature the wafer to an RIE-free microwave-energy-generated plasma of a primary gas mixture, the exposing causing photoresist removal such as by ashing. The method also comprises determining an endpoint to the removal by a determined change in the visible light emanating from a chamber containing the wafer. A multi-step process of the present invention comprises the above method and a preliminary RIE-free microwave-energy-generated plasma that solubilizes polymer on walls of vias of the wafer. This multi-step process also comprises, following the exposing step, a cooling step, a cooling step with a temperature check, and a deglazing step. The deglazing step also uses an RIE-free microwave-energy-generated plasma. Specific gas mixtures for the respective plasmas are exemplified. Other embodiments of methods of the present invention are comprised of less steps, or a consolidation of such steps.

Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar.

Abstract: A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed with a smoothing agent. A layer of strained silicon is formed on the silicon germanium layer. In various embodiments, the entire method is conducted in a single processing chamber, which is kept under vacuum.

Abstract: A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Abstract: The present invention provides a method for expanding a trench in a semiconductor structure. A trench is provided in a semiconductor substrate, hydrogen-terminated silicon surfaces are provided in the trench, anisotropic wet etching of the silicon surfaces in the trench with an alkaline etchant occur, and the trench is rinsed with a proton-containing neutralizing agent for the removal of the alkaline etchant. Between the wet etching step and the rinsing step, an anodic passivation of the etched silicon surfaces in the trench is carried out, in the course of which an etching stop layer is formed on the etched silicon surfaces in the trench.

Abstract: After cleaning a surface of a silicon substrate (1), impurities and natural oxide film existing on the silicon substrate (1) are removed by soaking the silicon substrate (1) in a 0.5%-by-volume HF aqueous solution for 5 minutes. The silicon substrate (1) is rinsed (cleaned) with ultrapure water for five minutes. Then, the silicon substrate (1) is soaked for 30 minutes in azeotropic nitric acid heated to an azeotropic temperature of 120.7° C. In this way, an extremely thin chemical oxide film (5) is formed on the surface of the silicon substrate (1). Subsequently, a metal film (6) (aluminum-silicon alloy film) is deposited, followed by heating in a hydrogen-containing gas at 200° C. for 20 minutes. Through the heat processing in the hydrogen-containing gas, hydrogen reacts with interface states and defect states in the chemical oxide film (5), causing disappearance of the interface states and defect states. As a result, the quality of the film can be improved.

Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.

Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.

Abstract: A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and forming the layer of photoresist 28 over the layer of pre-wet solvent 52. Also, a layer of photoresist 28 formed by this method.

Abstract: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.

Abstract: A unique and novel durable environmentally stabilized, waterproof, and moisture vapor permeable composite sheet material is described that includes a moisture permeable monolithic film, coating, or film/nonwoven laminate, that is held in close proximity to one or more layers of durable strength enhancing fabrics. The strength enhancing fabrics can include cotton, polyester, cotton/polyester blends, acrylic, and other synthetic materials and blends. The breathable monolithic film or coating is preferably polyester or polyurethane based. The breathable and durability enhancing layers are preferably laminated using hot melt adhesives such as polyester-based powder bond adhesives or using solvent-based polyurethane adhesives.

Abstract: The present invention is directed to ion triggerable, water-dispersible cationic polymers. The present invention is also directed to a method of making ion triggerable, water-dispersible cationic polymers and their applicability as binder compositions. The present invention is further directed to fiber-containing fabrics and webs comprising ion triggerable, water-dispersible binder compositions and their applicability in water-dispersible personal care products, such as wet wipes.

Abstract: An infrared-transmitting glass material consists essentially of 35.3% wt. arsenic and 64.3% wt. selenium and has an expansion coefficient of 27×10?6/° C.

Abstract: An optical glass being free of lead and fluorine, having a low glass transition temperature permitting press-molding with a mold formed of stainless steel and having high climate resistance includes an optical glass comprising, by mol %, 25 to 44% of P2O5, 10 to 40% of a total of Li2O, Na2O and K2O, 5 to 40% of ZnO, 1 to 35% of BaO and at least one components selected from Nb2O5, Bi2O3 and WO3, having a glass transition temperature (Tg) of 370° C. or lower and being free of lead and fluorine and an optical glass which is free of lead and fluorine, has a mass loss ratio of less than 0.25% when immersed in pure water, and has a glass transition temperature (Tg) of 370° C. or lower.

Abstract: An alkali-free aluminoborosilicate glass having a coefficient of thermal expansion ?20/300 of between 2.8×10?6/K and 3.8×10?6/K, which has the following composition (in % by weight, based on oxide): silicon dioxide (SiO2)>58–65, boric oxide (B2O3)>6–11.5, magnesium oxide (MgO) 4–8, barium oxide (BaO) 0–<0.5, zinc oxide (ZnO) 0–2 and aluminum oxide (Al2O3)>14–25, calcium oxide (CaO) 0–8, strontium oxide (SrO) 2.6–<4, with barium oxide (BaO)+strontium oxide (SrO)>3, or aluminum oxide (Al2O3)>14–25, calcium oxide (CaO) 0–<2, strontium oxide (SrO)>0.5–<4, or aluminum oxide (Al2O3)>21–25, calcium oxide (CaO) 0–8, strontium oxide (SrO)>2.6–<8, with barium oxide (BaO)+strontium oxide (SrO)>3, and which is highly suitable for use as a substrate glass both in display technology and in thin-film photovoltaics.

Abstract: A slip-casted article former containing ternary ceramics, particularly of carbide and nitride materials, having the formula M.sub.n+1AX.sub.n (MAX), where M is a transition metal, A is an element from Groups IIIA and IVA of the periodic table, X is nitrogen or carbon and n is 1, 2, or 3. The ternary ceramic article may be a glove or condom former. A process for making a ternary ceramic article employing a slip cast method.

Abstract: A silicon nitride based ceramic, that is highly effective for use as a cutting tool for the high speed machining of cast irons, that is essentially a homogeneous mixture consisting of both crystalline and whisker forms of beta silicon nitride that are interstitially bonded by a stoichiometrically balanced glass mixture of magnesia, silica, yttria and zirconia, where the ratios of each have been controlled to increase the eutectic point and refractoriness of the mixed glass.

Abstract: A crucible comprising Al2O3 and at least one selected from rare earth oxides inclusive of Y2O3 as main components and characterized by firing at 500–1,800° C., the distribution of the rare earth oxide at a higher proportion in a fine particle portion having a particle size of up to 0.5 mm than in a coarse particle portion having a particle size in excess of 0.5 mm, and the substantial absence of the reaction product of the rare earth oxide with Al2O3 is suitable for the melting of a rare earth alloy.

Abstract: A method of production of a reduction resistant dielectric ceramic composition having a superior low frequency dielectric characteristic and further improved in accelerated lifetime of insulation resistance, specifically a method of production of a dielectric ceramic composition containing a main component including a dielectric oxide of a specific composition, a first subcomponent including a V oxide, a second subcomponent containing an Al oxide, a third subcomponent containing an Mn oxide, and a fourth subcomponent containing a specific sintering aid in a specific ratio, including a step of mixing at least part of the materials of the subcomponents excluding one or both of at least the material of the third subcomponent and material of the fourth subcomponent with the starting materials prepared for obtaining the material of the main component to prepare the pre-reaction material, a step of causing the prepared pre-reaction material to react to obtain a reacted material, and a step of mixing the materials o

Abstract: A process is described for the synthesis of mesitylene, characterized in that mesitylene is obtained starting exclusively from pseudocumene, without the use of any other chemical compound, operating in continuous, at a temperature ranging from 225 to 400° C., at a pressure ranging from 1 to 50 bar, at a weight space velocity ranging from 0.1 to 10 hours?1, and in the presence of a catalyst containing a zeolite selected from ZSM-5 zeolite having a crystal lattice based on silicon oxide and aluminum oxide, and ZSM-5 zeolite modified by the partial or total substitution of Si with a tetravalent element such as Ti or Ge and/or the partial or total substitution of Al with other trivalent elements, such as Fe, Ga or B.

Abstract: The invention relates to a method for producing special transition metal compounds, to novel transition metal compounds and to the use thereof for polymerizing olefins.

Abstract: In one embodiment the invention is a polymerizable composition comprising a) an organoborane amine complex; b) one or more of monomers, oligomers or polymers having olefinic unsaturation which is capable of polymerization by free radical polymerization; c) one or more compounds, oligomers or prepolymers having a siloxane backbone and reactive moieties capable of polymerization; and d) a catalyst for the polymerization of the one or more compounds, oligomers or prepolymers having a siloxane backbone and reactive moieties capable of polymerization. This composition may further comprise a compound which causes the organoborane amine complex to disassociate.

Abstract: New compositions, titanium-ligand complexes and arrays with pyridyl-amine ligands are disclosed that catalyze the polymerization of monomers into polymers. These catalysts with titanium metal centers have high performance characteristics, including high styrene incorporation into ethylene/styrene copolymers.

Abstract: A catalyst for the hydroprocessing of organic compounds, composed of an interstitial metal hydride having a reaction surface at which monatomic hydrogen is available. The activity of the catalyst is maximized by avoiding surface oxide formation. Transition metals and lanthanide metals compose the compound from which the interstitial metal hydride is formed. The catalyst's capabilities can be further enhanced using radio frequency (RF) or microwave energy.

Abstract: The present invention provides a bimodal porous carbon capsule with a hollow core and a mesoporous shell structure, which can be employed as an electrocatalyst support for a fuel cell; electrocatalysts for the fuel cell using the bimodal porous carbon capsule, and a method of preparing the same. The electrocatalyst according to the present invention has higher catalysis activity as compared with the Pt—Ru or Pt catalyst supported by the conventional carbon black, so that the performance of the fuel cell is enhanced, and it can be easily prepared in an aqueous solution state. According to the present invention, the porous carbon support employed as the support for the catalyst has excellent conductivity and a high surface area, so that the loaded catalyst can be prepared with a smaller amount than that of the conventional carbon black.

Abstract: A process for preparing a vanadium, phosphorus, and oxygen catalyst precursor for preparing maleic anhydride by heterogeneously catalyzed gas-phase oxidation of a hydrocarbon having at least four carbon atoms, by reacting vanadium pentoxide (I) in the presence of a primary or secondary, noncyclic or cyclic, unbranched or branched, saturated alcohol having from 3 to 6 carbon atoms (II) with a pentavalent or trivalent phosphorus compound (III) in a temperature range from 80 to 160° C. with stirring and subsequently filtering the resultant suspension, in which (a) the way in which the phosphorus compound (III) and the vanadium pentoxide (I) are combined in the presence of the alcohol (II), (b) the action of a stirring power of from 0.01 to 0.6 W/kg suspension, and/or (c) the filtration at a temperature from 65° C. to 160° C.

Abstract: The present invention relates to a catalyst for preparing hydrocarbons of carbon dioxide and more particularly, the Fe—Cu—K/?—Al2O3 catalyst prepared by impregnation which enables producing hydrocarbons in high yield for more than 2000 hours due to its excellent activity and stability.

Abstract: An exhaust emission control system for an internal combustion engine is provided. The exhaust emission control system (4) includes a monolith catalyst (MC) that includes an oxygen storage agent and a noble metal-based three-way catalyst including Pd, Rh, and Pt disposed at an upstream location in the exhaust gas flow in the internal combustion engine (2), and a perovskite-type double oxide having a three-way catalytic function disposed at a downstream location in the exhaust gas flow. The amount C1 of Pd carried is 0.97 g/L?C1?1.68 g/L, the amount C2 of Rh carried is 0.11 g/L?C2?0.2 g/L, the amount C3 of Pt carried is 0.06 g/L?C3?0.11 g/L, the amount C4 of the oxygen storage agent carried is 25 g/L?C4?75 g/L, and the amount C5 of the perovskite-type double oxide carried is 5 g/L?C5?15 g/L.

Abstract: Catalysts or carriers which consist essentially of monoclinic zirconium dioxide are prepared by pecipitation of zirconium salts with ammonia, by adding a zirconyl nitrate or zirconyl chloride solution to an aqueous ammonia solution at a decreasing pH from 14 to 6 and drying, calcining and pelletizing the product.