Patents Issued in January 2, 2007
  • Patent number: 7157910
    Abstract: A magnetic resonance imaging apparatus includes an RF coil system with M RF coils (11–18) for detecting RF signals from a region of interest, M being an integer larger than 2, and N receiver channels (C1–C4) for receiving and processing the detected RF signals, N being an integer larger than 1 and smaller than M. At least two RF coils (12, 16; 14, 18) are combined for reception of RF signals of said RF coils with a single receiver channel. The at least two RF coils are selected so as to provide maximum spatially varying coil sensitivities along the principal axis for coil sensitivity encoding. The proposed MRI apparatus provides an optimal solution enabling it to be used with the SENSE method. The individuality is maximized along the preferred or actual sense reduction direction as is spatial distinctness along the axes of primary clinical interest.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: January 2, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Johan Samuel Van Den Brink
  • Patent number: 7157911
    Abstract: An eddy current induced in an RF shield by an X-axis gradient coil, a Y-axis gradient coil, and a Z-axis gradient coil respectively is homogeneously released to an earth ground simultaneously with induction. An RF shield is connected to a magnet via capacitors at four points whose angles are different from one another by 90°. The magnet is connected to the earth ground. An eddy current induced in the RF shield can be prevented from degrading MRI image quality.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: January 2, 2007
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Tsunemoto Suzuki, Yasushi Kato, Nozomu Uetake
  • Patent number: 7157912
    Abstract: At least one superconducting shim coil is wound around a cylinder member disposed approximately coaxially with a group of superconducting main coils, and the positions in the winding center locus in an axial direction change approximately in accordance with a function where a sine or cosine function with a cycle of (360/m) degrees (m; an integer of one or more) in a circumferential direction is mixed with a sine or cosine function with a cycle of (360/(m+2)) degrees.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 2, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Kohji Maki, Tsuyoshi Wakuda
  • Patent number: 7157913
    Abstract: A device in which the receiver coil of a pulse inductive metal detector is capable of switching between a differential configuration (i.e., gradiometer configuration) to a non-differential or summing configuration under control of the operator or computer.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: January 2, 2007
    Assignee: The Johns Hopkins University
    Inventor: Carl V. Nelson
  • Patent number: 7157914
    Abstract: An airborne time domain electromagnetic surveying system is provided. The system includes a tow assembly with a flexible support frame. The flexible support frame spaced apart from the aircraft includes a transmitter section with a transmitter loop and a receiver section with a sensor aligned with the central axis of the transmitter section. The flexible support frame has a lightweight modular structure that enables the surface area of the transmitter section to be increased and decreased to suit particular survey applications. The transmitter loop sends a pulse in an “ON” interval, and in an “OFF” interval the sensor measures the earth response to the pulse. The tow assembly also includes a sensor for generating selected survey data in the “ON” interval. A transmitter driver enables the creation of earthbound pulse. The system components are linked to a computer and control computer program linked thereto for controlling the functions thereof.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: January 2, 2007
    Inventors: Edward Beverly Morrison, Petr Valentinovich Kuzmin, Pavel Tishin
  • Patent number: 7157915
    Abstract: A method of determining the distribution of shales, sands and water in a reservoir including laminated shaly sands using vertical and horizontal conductivities derived from nuclear, NMR, and multi-component induction data such as from a Multicomponent Induction Logging Tool
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: January 2, 2007
    Assignee: Baker Hughes Incorporated
    Inventors: Juergen S. Schoen, Otto N. Fanini, Daniel Georgi
  • Patent number: 7157916
    Abstract: There is provided a test apparatus including: a test module operable to supply test patterns to the electronic device; a main signal source operable to generate a first timing signal in accordance with a phase of the supplied timing signal and supply it to the test module; and a sub-signal source operable to receive the timing signal from the main signal source, generate a second timing signal for controlling timing at which the test module supplies the test patterns to the electronic device, and supply it to the test module. The sub-signal source includes a phase adjustment circuit that substantially uniforms the timing at which the main signal source outputs the first timing signal and the timing at which the sub-signal source outputs the second timing signal by delaying the timing signal received from the main signal source.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: January 2, 2007
    Assignee: Advantest Corporation
    Inventor: Hiroshi Satou
  • Patent number: 7157917
    Abstract: A cable includes a first connector half holding a conductor terminal, a second connector half holding a conductor terminal, an electric cord electrically connecting the conductor terminal of the first connector half to the conductor terminal of the second connector half, and a waveform shaping circuit performing waveform shaping of a signal passing through the electric cord, and the first and second connector halves are structured to allow attachment to and detachment from each other.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: January 2, 2007
    Assignee: Omron Corporation
    Inventors: Naoya Nakashita, Hirotaka Nakashima, Hitoshi Oba, Masahiro Kawachi, Kizuku Fujita, Kohei Tomita
  • Patent number: 7157918
    Abstract: A method and system of calibrating first and second adapters comprises the steps of calibrating coaxial ports of a vector network analyzer to traceable standards and connecting a symmetrical through circuit path between the coaxial ports. The through circuit path comprises a cascaded combination of the first and second adapters. The first adapter is passive and substantially identical to the second adapter and uncascaded first and second adapters comprise a measurement device path. The through circuit path and the measurement device path have substantially equivalent S-parameters. S-parameters of the through circuit path are measured and then the first and second adapters are characterized based upon the measured S-parameters. The method and system may be applied to two port adapters and devices under test and may also be scaled for multi-port adapters and devices under test.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: January 2, 2007
    Assignee: Agilent Technologies, Inc.
    Inventor: Vahe′ A. Adamian
  • Patent number: 7157919
    Abstract: A system and method for detecting soot and or ash loading within a filter is provided. The method comprises the steps of transmitting a source RF signal through a filter, measuring a reflected RF signal, measuring a transmitted RF signal, calculating reflected power by comparing the source RF signal with the reflected RF signal, calculating attenuated power by comparing the source RF signal with the transmitted RF signal, and determining soot loading based on reflected power and transmitted power. The system and method may also determine ash loading.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: January 2, 2007
    Assignee: Caterpillar inc.
    Inventor: Frank B Walton
  • Patent number: 7157920
    Abstract: A component which is known to have particular degradation characteristics is instrumented to provide an electrical potential across a section in which a degradation is likely to occur. The potential drop across the component is then monitored to determine when, and the degree to which, the degradation occurs. Predetermined limits are established such that when the degradation level reaches a limit, the component is repaired or replaced.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 2, 2007
    Assignee: United Technologies Corporation
    Inventors: Brent W. Barber, Jerrol W. Littles
  • Patent number: 7157921
    Abstract: A TFT array inspection apparatus inspects a TFT array by irradiating an electron beam on a TFT substrate to obtain potential information. The TFT array inspection apparatus includes a scanning device for scanning the TFT substrate with an electron beam; a defect detecting device for detecting a defective site on the TFT substrate from a scanning signal of the TFT substrate; an irradiating device for irradiating the electron beam on the detected defective site; and a defect analyzing device. The defect analyzing device analyzes at least a type and/or an extent of the defect of the defective site based on a waveform change of a secondary electron signal detected through the electron beam irradiation and a driving state of the TFT.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: January 2, 2007
    Assignee: Shimadzu Corporation
    Inventor: Makoto Shonohara
  • Patent number: 7157922
    Abstract: An opening 5a is formed in a part of a high strength base plate 5 for providing electroconductive contact units, and a holder hole forming member 7 made of plastic material is filled into the opening via an insulating film 6. Holder holes 2 are formed in the holder hole forming member, and a coil spring 8 and electroconductive needle members 9 and 10 are installed in each holder hole. Because the proportion of the reinforcing material in the thickness of the holder is so high that the contact probe holder can be made almost as strong as the high strength base plate. Thus, even when the thickness of the holder is minimized, the mechanical strength of the holder can be ensured as opposed to the conventional arrangement including a simply insert molded metallic member, and the holder can be made even thinner.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: January 2, 2007
    Assignee: NHK Spring Co., Ltd.
    Inventor: Toshio Kazama
  • Patent number: 7157923
    Abstract: A technique to simplify the cost and complexity of performing a full wafer test or probe of semiconductor wafers. A probe card connection layer is disposed on a surface of the wafer. The probe card connection layer comprises a plurality of probe contact connection points on a top surface of the probe card connection layer and a plurality of conductive traces on a bottom surface of the probe card connection layer. Each conductive trace is electrically connected to a corresponding probe contact connection point and electrically connected to a similar function connection point on each of a plurality of chips. Each conductive trace carries a test signal supplied to a corresponding probe contact connection point to the similar function connection points of the chips to which it is connected.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: January 2, 2007
    Assignee: Infineon Technologies AG
    Inventors: Peter Schneider, Klaus Nierle
  • Patent number: 7157924
    Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Ali Muhtaroglu, Kent Callahan, Tawfik Arabi, Greg F. Taylor
  • Patent number: 7157925
    Abstract: A test structure, having: a first member having: a roughly a rectangular shape; a first width dimension; and a first length dimension that is greater than the first width dimension; and a second member having: a roughly a rectangular shape; a second width dimension; and a second length dimension that is greater than the second width dimension combined with the first member to form a roughly symmetrical cross-shaped test structure. Also a method of using the test structure to test for voids.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: January 2, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chien-Jung Wang
  • Patent number: 7157926
    Abstract: A universal, substrate Padset for de-embedding pad and signal line parasitics has an input pad group including a first input signal pad and a first ground pad; an output pad group including a first output signal pad and a second ground pad; a first input-signal-routing network for routing the first input signal pad to a first input node of a first predetermined test device; a first output-signal-routing network for routing the first output signal pad to a first output node of the first predetermined test device; a second input-signal-routing network for routing the first input signal pad to a second input node of a second predetermined test device; and a second output-signal-routing network for routing the first output signal pad to a second output node of the second predetermined test device. The layout configuration of the first test device is different from the layout configuration of the second test device.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: January 2, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Michael Hargrove, Michael Starego
  • Patent number: 7157927
    Abstract: A test pattern includes a test wiring pattern on a lower surface of a substrate. First, second, third and fourth upper patterns are formed on an upper surface of the substrate. First, second, third and fourth electrodes are formed respectively on the first, second, third and fourth upper patterns. The first and second electrodes are for connection to first and second test probes. First and second via-holes are formed through the substrate respectively to connect the first and second upper patterns electrically to one end of the test wiring pattern. Third and fourth via-holes are formed through the substrate respectively to connect the third and fourth upper patterns electrically to another end of the test wiring pattern.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: January 2, 2007
    Assignee: Oki Electric Industry Co., Ltd
    Inventor: Takehiko Okajima
  • Patent number: 7157928
    Abstract: One embodiment of this invention pertains to a high throughput screening technique to identify current leakage in matrix-structured electronic devices. Because elements that are likely to develop a short have relatively high leakage current at zero operation hours, by identifying elements with the relatively high leakage current, the electronic devices that are more likely to later develop a short can be differentiated. The screening technique includes performing the following actions: selecting one of multiple first lines; applying a first voltage to the selected first line; applying a second voltage to the one or more of the first lines that are not selected; floating the multiple second lines; and measuring the voltages on the second lines, either sequentially one line at a time or measuring all the lines at the same time.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 2, 2007
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Franky So, Florian Pschenitzka, Egbert Hoefling
  • Patent number: 7157929
    Abstract: A system for testing a flat panel display device includes a support plate and an electrical connector set. The support plate includes a plate body having a through hole, and is adapted to support the display device thereon such that a screen of the display device faces an upper surface of the plate body. The electrical connector set is mounted on the support plate, and is adapted to connect electrically with the display device on the support plate so as to enable activation of the display device to radiate light from the screen of the display device through the through hole. One of a light-directing component and an image-capturing unit is disposed under and is spaced apart from the support plate, to receive the light from the display device that passes through the through hole.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: January 2, 2007
    Assignee: Hannspree, Inc
    Inventors: Shih-Chung Kuo, Makoto Huang
  • Patent number: 7157930
    Abstract: There is provided a flip flop circuit with a scan structure which is formed by an input section of a dynamic circuit and an output section of a static circuit wherein data is taken in within an interval of a short pulse width as compared with a clock cycle. In the dynamic circuit of the input section, the number of serially-connected MOS transistors to which a data signal is input is smaller than the number of serially-connected MOS transistors to which a test input signal is input. With this structure, the speed of operation is increased at the time of data storage for a data signal input, and the number of MOS transistors is reduced.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: January 2, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Akio Hirata
  • Patent number: 7157931
    Abstract: A termination circuit for a transmission line may include an input node, a pull-down circuit, and a pull-up circuit. The input node receives an input signal over the transmission line. The pull-down circuit is coupled between the input node and a first reference voltage, and the pull-down circuit may be configured to provide an electrical path between the first reference voltage and the input node responsive to the input signal having a first voltage level. The pull-up circuit is coupled between the input node and a second reference voltage, and the pull-up circuit is configured to provide an electrical path between the second reference voltage and the input node responsive to the input signal having a second voltage level. More particularly, the first reference voltage is less than the second reference voltage, and the first voltage level is greater than the second voltage level. Related methods are also discussed.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: January 2, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-young Song
  • Patent number: 7157932
    Abstract: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: January 2, 2007
    Assignee: Agere Systems Inc.
    Inventors: Tony S. El-Kik, Anthony W. Seaman, Stefan A. Siegel
  • Patent number: 7157933
    Abstract: Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The first configurable IC includes several configurable logic circuits. Each configurable logic circuit can configurably perform a set of functions. The IC also includes several configurable interconnect circuits that configurably couple the logic circuits. At least several configurable circuits can reconfigure faster than the particular design rate.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 2, 2007
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Patent number: 7157934
    Abstract: High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the designer needing to be explicitly aware of all pipelining details. The FPGAs include arrays of logic blocks or cells that include function units, conditional units and other elements, each of which is constructed using basic asynchronous pipeline stages, such as a weak condition half buffer and a precharge half buffer.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: January 2, 2007
    Assignee: Cornell Research Foundation, Inc.
    Inventors: John R. Teifel, Rajit Manohar
  • Patent number: 7157935
    Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 2, 2007
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Ashish K. Goel, Davinder Aggarwal
  • Patent number: 7157936
    Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: January 2, 2007
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Rajat Chauhan, Rajesh Kaushik
  • Patent number: 7157937
    Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: January 2, 2007
    Assignee: eASIC Corporation
    Inventors: Adrian Apostol, Petrica Avram, Romeo Iacobut, Adam Levinthal, Zvi Or-Bach, Ze′ev Wurman, Richard Zeman, Alon Kapel, George C. Grigore
  • Patent number: 7157938
    Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: January 2, 2007
    Assignee: Actel Corporation
    Inventors: Sheng Feng, Jung-Cheun Lien, Eddy C. Huang, Chung-Yuan Sun, Tong Liu, Naihui Liao, Weidong Xiong
  • Patent number: 7157939
    Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: January 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7157940
    Abstract: A method for driving a data signal across a data bus consists of charging the data bus to a first voltage level prior to driving the signal, maintaining the data bus at the first voltage level when a first type of data signal is to be driven, and pulling the data bus to a second voltage level when a second type of data signal is to be driven. A system for driving a data signal consists of a data bus, a charging circuit coupled to the data bus configured to charge the data bus to a first voltage level, a keeper circuit coupled to the data bus configured to maintain the data bus at the first voltage level after the charging circuit has charged the data bus, and a pull-down circuit coupled to the data bus configured to pull the data bus to a second voltage level.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: January 2, 2007
    Assignee: Inapac Technology, Inc
    Inventor: Adrian E. Ong
  • Patent number: 7157941
    Abstract: A differential switching circuit has a first transistor connected between a first output node and a common node and a second transistor connected between a second output node and the common node. A switching driver generates first and second driving signals in response to an input data signal so as to complementarily drive the first and second transistors. A voltage level of at least one of the first and second driving signals is maintained so as to cause at least one of the first and second transistors to operate in a saturation region regardless of a voltage variation of at least one of the first or second output nodes when the at least one of the first and second transistors is turned on. Output impedance of the device is enhanced because the first and second transistors operate in the saturation region.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: January 2, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyung-Woan Koo
  • Patent number: 7157942
    Abstract: A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: January 2, 2007
    Assignee: Seiko Epson Corporation
    Inventor: David Meltzer
  • Patent number: 7157943
    Abstract: A switch mode power converter that limits the in-rush current at start-up and reduces the occurrence of output voltage overshoot over a range of switching frequencies. The converter includes at least one Soft-Start (SS)/Frequency-Select(FS) input, at least one oscillator enable input, and an oscillator having at least one control input. Soft-start programming is linked to the frequency selection of the converter. An external capacitor connected between the SS/FS input and ground is employed to program the soft-start time, and the switching frequency generated by the oscillator is selected via the state of the SS/FS input.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: January 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher J. Sanzo
  • Patent number: 7157944
    Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: January 2, 2007
    Assignee: Altera Corporation
    Inventors: Shoujun Wang, Bill Bereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei
  • Patent number: 7157945
    Abstract: A window comparator comprising a single comparator circuit that has a positive input, a differential negative input, and an output, wherein limits of a window are defined by a reference voltage and a window condition is defined for a differential voltage between a positive input voltage and a negative input voltage so that the differential voltage is within the limits of the window; including a common mode voltage, a first set of two switched capacitors connected to the positive comparator input, a second set of two switched capacitors connected to the negative comparator input, a switching array capable of assuming a plurality of different switching conditions, and detecting the output of the comparator in relation to the switching conditions of the switching array.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Frank Ohnhauser, Mikael Badenius
  • Patent number: 7157946
    Abstract: The conventional chopper comparator circuit has had high power consumption because the gain thereof used to be set high, so that there has been the need for cutting down on power consumption.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: January 2, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuru Arai, Mamoru Kondo
  • Patent number: 7157947
    Abstract: In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Chaiyuth Chansungsan, Keith Self
  • Patent number: 7157948
    Abstract: A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: January 2, 2007
    Assignee: LSI Logic Corporation
    Inventors: Gary P. McClannahan, Daniel P. Wetzel, Gary M. Lippert
  • Patent number: 7157949
    Abstract: A DLL capable of preventing false lock includes a false-lock detector, a delay line coupled for using at least one delay lag of the delay line to delay an incoming clock signal and produce at least one delay clock, and a charge pump coupled to the false-lock detector for adjusting a control voltage according to an upward or downward adjustment signal. The false-lock detector includes a first phase detector coupled to a first clock signal and a second clock signal for comparing phases of the first clock signal and the second clock signal to produce a phase difference signal; an average circuit coupled to the first phase detector for generating an average signal corresponding to an average of the phase difference signal; and a comparator circuit coupled to the average circuit for comparing the average signal with at least one reference signal to produce the upward or downward adjustment signal.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: January 2, 2007
    Assignee: Mediatek Incorporation
    Inventors: Chien-Ming Chen, Ching-San Wu
  • Patent number: 7157950
    Abstract: Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Hon-Mo Raymond Law, Rachael J. Parker
  • Patent number: 7157951
    Abstract: A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: January 2, 2007
    Assignee: Xilinx, Inc.
    Inventors: Shawn K. Morrison, Raymond C. Pang
  • Patent number: 7157952
    Abstract: Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 2, 2007
    Assignee: L-3 Integrated Systems Company
    Inventors: Bradley S. Avants, Arturo Yanez
  • Patent number: 7157953
    Abstract: The circuits and methods of the present invention relate to circuits for generating a multiplied clock signal based upon a reference clock signal, and circuits using the clock signal to deserialize data. According to one embodiment of the invention, a circuit comprising a counter is coupled to generate a count representative of the period of the input clock signal. A divider circuit coupled to the counter generates a divided count. Finally, a clock generator coupled to the divider circuit outputs an output clock signal having a period which is based upon the divided count. According to other embodiments, circuits and methods disclose receiving serial data using the output clock signal, and outputting the data as parallel data using the reference clock.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: January 2, 2007
    Assignee: Xilinx, Inc.
    Inventor: Andy T. Nguyen
  • Patent number: 7157954
    Abstract: There is described a semiconductor Type Two phased locked loop filter having a passive capacitor part and a variable active resistor part, the variable active resistor part being integrated with the passive capacitor part. Integrating an active variable resistor will apply the same change to both poles and has no effect on the loop gain. The variable active resistor part is controlled by a resistor regulator circuit operating from a voltage that follows the type two phased locked loop voltage. The resistor regulator circuit is bootstrapped to the phased locked loop voltage using a voltage follower configured op-amp.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: January 2, 2007
    Assignee: International Business Machines Corporation
    Inventor: James Stephen Mason
  • Patent number: 7157955
    Abstract: A switched capacitor sampler circuit (220) includes an input terminal (224) for receiving an input voltage, an output terminal (226), a capacitor (222) having first and second terminals, and a switching circuit (230). The switching circuit (230) is coupled to the input terminal (224), the output terminal (226), and the first and second terminals of the capacitor (222). The switching circuit (230) stores a charge on the capacitor (222) proportional to the input voltage during a sample period, and transfers the charge from the capacitor (222) to the output terminal (226) during a transfer period subsequent to the sample period. The switching circuit (230) transfers the charge in a plurality of charge portions corresponding to a like plurality of phases of the transfer period.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: January 2, 2007
    Assignee: Silicon Laboratories, Inc.
    Inventor: Derrick Chunkai Wei
  • Patent number: 7157956
    Abstract: A switched capacitor input circuit (200) includes an input buffer (210), a switched capacitor sampler circuit (220), and an integrator (250). The input buffer (210) has an input terminal for receiving an input voltage, and an output terminal. The switched capacitor sampler circuit (220) has an input terminal coupled to the output terminal of the input buffer (210), and an output terminal. The switched capacitor sampler circuit (220) includes a capacitor (222) and stores a charge proportional a voltage at the output terminal of the input buffer (210) in the capacitor (222) during a sample period, and transfers the charge from the capacitor (222) to the output terminal thereof during a transfer period subsequent to the sample period in a plurality of charge portions corresponding to a like plurality of phases of the transfer period. The integrator (250) has an input terminal coupled to the output terminal of the switched capacitor sampler circuit, and an output terminal for providing an output voltage signal.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: January 2, 2007
    Assignee: Silicon Laboratories, Inc.
    Inventor: Derrick Chunkai Wei
  • Patent number: 7157957
    Abstract: Provided is concerned with a high voltage switch circuit for a semiconductor device, which rapidly discharges a gate voltage of a pass transistor through an additional discharge transistor during inactivation of itself in the circuit structure with a positive feedback loop for transferring an internal high voltage without a voltage drop by applying an enough voltage to the gate of the pass transistor. The high voltage switch circuit prevents the internal high voltage from decreasing.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: January 2, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Doe Cook Kim
  • Patent number: 7157958
    Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: January 2, 2007
    Assignee: Atmel Corporation
    Inventors: John L. Fagan, Mark A. Bossard
  • Patent number: 7157959
    Abstract: In one embodiment, a self-gated transistor includes a sensing portion that generates a sense signal that is used to drive the self-gated transistor.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 2, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Alan R. Ball, Paul J. Harriman, Stephen Meek, Suzanne Nee