Abstract: The present invention provides a magnetic memory device capable of stably writing information by efficiently using a magnetic field generated by current flowing in a conductor, which can be manufactured more easily, and a method of manufacturing the magnetic memory device. The method includes: a stacked body forming step of forming a pair of stacked bodies S20a and S20b on a substrate 31; a lower yoke forming step of forming a lower yoke 4B so as to cover at least the pair of stacked bodies S20a and S20b; and a write line forming step of simultaneously forming a pair of first parts 6F and write bit lines 5a and 5b so as to be disposed adjacent to each other in a first level L1 via an insulating film 7A as a first insulating film on the lower yoke 4B. Thus, the manufacturing process can be more simplified.

Abstract: An intermediate product for an integrated circuit is disclosed. The intermediate product comprises a first portion of a conductive layer, preferably a layer of noble metal, which will form an upper electrode of a capacitor or a patterned wiring. The intermediate product also comprises an adjacent second portion of the conductive layer, the second portion being a removable silicide of the conductive layer.

Abstract: Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the peripheral circuit region. A cell gate pattern that includes a plurality of conductive layers crosses over the cell active region, and a peripheral gate pattern that includes a plurality of conductive layers crosses over the peripheral active region. A lowermost layer of the peripheral gate pattern has first and second sidewalls that are aligned with respective of either the first and second sidewalls of the second device isolation layer or a vertical extension of the first and second sidewalls of the second device isolation layer. Further, the lowest layer of the cell gate pattern and the lowest layer of the peripheral gate pattern comprise different conductive layers.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A semiconductor device having an isolation pattern inside an interlayer insulating layer between capacitor contact plugs and methods of fabrication the same: The semiconductor device includes an interlayer insulating layer covering a semiconductor substrate. At least two contact plugs passing the interlayer insulating layer and connected to the semiconductor substrate. An insulating layer pattern, which is formed of a material having an etch rate lower than that of the interlayer insulating layer, covers the interlayer insulating layer between the neighboring contact plugs. An isolation pattern, which is formed of a material having an etch rate lower than that of the interlayer insulating layer, is extended from the insulating layer pattern and located inside the interlayer insulating layer between the neighboring contact plugs. A charge storage electrode contacts the contact plug.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P31 pocket regions 17 and N31 pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P31 pocket regions 17 and the N31 pocket regions 27.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the substrate, and a tunnel barrier arrangement, via which charging or discharging of the floating gate can be performed. It is possible to alter the conductivity of a channel between source and drain regions by charging or discharging the floating gate. A source line is electrically conductively connected to the source region and controls the charge transmission of the tunnel barrier arrangement.

Abstract: In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.

Abstract: A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator.

Abstract: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.

Abstract: EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating gate memory cells to form NOR and NAND architecture memory cell strings, segments, and arrays. These memory cell architectures allow for improved high density memory devices or arrays with integral select gates that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and allow for appropriate device sizing for operational considerations. The memory cell architectures also allow for mitigation of disturb and overerasure issues by placing the floating gate memory cells behind select gates that isolate the memory cells from their associated bit lines and/or source lines.

Abstract: A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.

Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

Abstract: A silicon-on-insulator semiconductor device which includes a substrate; and insulator layer overlying the substrate; a plurality of strained silicon islands overlying the insulator layer, the strained silicon islands are isolated from each other by mesa isolation; and a plurality of transistors formed on the strained silicon islands. A method for fabricating the silicon-on-insulator semiconductor device is further disclosed.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying subregions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

Abstract: A method for manufacturing a MOSFET equipped with a silicide layer over shallow source and drain junctions without leakage generation is provided. By restricting the temperature of manufacturing steps after the silicide formation below a critical temperature Tc, which is defined below as a function of a junction depth Dj from 20 nm to 60 nm, leakage generation is practically suppressed. Tc=a×Dj+b, where a = 6.11 ? ? ( 20 < Dj ? 26 ) ? = 1.60 ? ? ( 26 < Dj ? 60 ) , b = 290.74 ? ? ( 20 < Dj ? 26 ) ? = 408 ? ? ( 26 < Dj ? 60 ) , Dj is a junction depth (nm) measured from the lower surface of the silicide layer, and Tc is a critical temperature (° C.) during a heat treatment.

Abstract: The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate.

Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A first low impurity concentration source layer and a first low impurity concentration drain layer are formed by tilt angle ion implantation of double charge phosphorus ions (31P++) using the gate electrode as a mask. Then a second low impurity concentration source layer and a second low impurity drain layer are formed by tilt angle ion implantation of single charge phosphorus ions (31P+).

Abstract: A gate electrode is formed on a substrate via a gate insulating film. The gate insulating film includes a high dielectric constant film containing a metal, oxygen and hydrogen, and a lower barrier film formed below the high dielectric constant film and containing a metal, oxygen, silicon and nitrogen.

Abstract: A semiconductor device having a membrane includes a semiconductor substrate, which has an active surface, and a membrane. A cavity is located between the active surface and the membrane and hermetically sealed. The membrane includes a first film, which has a through hole that extends through the first film, and a second film, which has been formed by reflowing a reflow layer made of a material that becomes viscous and reflows when heated. The through hole has been plugged by the second film.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

Abstract: The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.

Abstract: Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (4). A second capacitor structure comprising a second dielectric layer (26) and a second gate layer (28) is formed overlying the first gate structure. A source region (22) of a second conductivity type formed in the semiconductor substrate (6) proximate the first lateral side of the gate and a drain extension region/well (12) lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region (24) of the second conductivity type formed within the drain extension region (12). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage.

Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.

Abstract: A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portions of the doped area. A P-type epitaxy layer is formed on the protection layer and the first doped area and then portions of the epitaxy layer and the protection layer are removed. An insulation layer is formed and at least a collector opening and emitter opening are formed within the insulation layer. Following that, a polysilicon layer is formed to fill the collector opening and the emitter opening. A spacer is formed beside the polysilicon layer and the epitaxy layer followed by performing a self-aligned silicidation process to form a salicide layer on the polysilicon layer and portions of the epitaxy layer.

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Abstract: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating a dispersion containing the above-mentioned binder and metal oxide fine particles on a sheet-shaped electrode; (3) a photoactive electrode for a dye-sensitized solar cell, obtained by the method, which electrode has metal oxide containing the above-mentioned binder and metal oxide fine particles; and (4) a dye-sensitized solar cell with the above-mentioned photoactive electrode.

Abstract: An example of a semiconductor device of the present invention includes a first semiconductor element including a first element body portion and a first element electrode that is provided on a first face of the first element body portion; a wiring board including an insulating substrate and a first wiring layer that is formed on one principal face of the insulating substrate, the wiring board being disposed such that the one principal face of the wiring board is opposed to a second face of the first element body portion; a first film that covers at least a portion of a face of the first semiconductor element that includes the surface of the first element electrode and at least a portion of a face on the first semiconductor element side of the wiring board; and a second wiring layer that is formed on a face on the wiring board side of the first film and that includes a first conductor having first and second ends.

Abstract: An integrated circuit device comprising an integrated circuit die mounted on a leadframe having a plurality of inner leads. The integrated circuit die has a plurality of bond pads that are electrically connected to the inner leads of the leadframe, wherein at least two bond pads are connected to a one of the plurality of inner leads and/or at least two inner leads are connected to one or more bond pads with a single bond wire. A single bond wire is connected to a first bond pad or inner lead and subsequently wedge or stitch bonded to a second bond pad or inner lead, then it is connected to a third bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and inner lead(s). The bond pad(s) of the die and inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a pillar and a routing line, and a ground plane. The pillar is press-fit into an opening in the ground plane, and the ground plane is electrically connected to the pad.

Abstract: A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

Abstract: Thermal spreading resistance, associated with small geometry electronic features that generate heat on a semiconductor, may be reduced through the addition of a thermally conductive fluid. For example, a dielectric fluid may be used within a volume between a semiconductor package and the semiconductor substrate. Therefore, direct thermal cooling may be employed to reduce the thermal spreading resistance often encountered in MMIC power amplifier devices. Furthermore, exemplary methods to achieve this sealing are described herein.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.

Abstract: Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of ?-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?.

Abstract: A SiP type semiconductor device and a method of producing the same is provided wherein curvature of a wafer is suppressed in the production steps, workability does not decline, and high throughput can be attained. An insulation layer is formed by stacking a plurality of resin layers on a semiconductor substrate, wiring layers are formed by being buried in the insulation layer so as to be connected to an electronic circuit, an insulating buffer layer for buffering a stress generated at the time of being mounted on a board is formed on the insulation layer, a conductive post is formed through the buffer layer and connected to the wiring layer, and a projecting electrode is formed projecting from a surface of the buffer layer and connected to the conductive post.

Abstract: A semiconductor device having: a semiconductor substrate; a plurality of circuit regions formed on the semiconductor substrate, the circuit regions including circuits driven at multiple supply voltages; interlayer insulating film or films formed above the semiconductor substrate; copper wirings buried in the interlayer insulating film or films, a minimum wiring spacing between adjacent wirings in a same layer so that an electric field between adjacent wirings due to an applied voltage difference is set to 0.4 MV/cm or lower; and a copper diffusion preventive film formed on the interlayer insulating film, covering an upper surface of the copper wirings. A semiconductor device is provided which has copper wirings capable of realizing a high reliability in a long term, basing upon newly found knowledge of time dependent failure rate of wiring.

Abstract: A method for creating a refractory metal and refractory metal nitride cap effective for reducing copper electromigration and copper diffusion is described. The method includes depositing a refractory metal nucleation layer and nitriding at least the upper portion of the refractory metal layer to form a refractory metal nitride. Methods to reduce and clean the copper lines before refractory metal deposition are also described. Methods to form a thicker refractory metal layer using bulk deposition are also described.

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Abstract: A disclosed bonded structure includes a first electric structure having a first electrode, a second electric structure having a second electrode, and a middle section for electrically and mechanically bonding the first electrode and the second electrode. The middle section consists of conductive adhesives, wherein fusion bonding of metal particles is provided to at least one of the first electrode and the second electrode. The metal particles are capable of fusion bonding at a temperature lower than a thermal hardening temperature of the conductive adhesives. The conductive adhesives contain conductive filler pieces that have a particle size at which fusion bonding does not take place at a temperature lower than the thermal hardening temperature of the conductive adhesives.

Abstract: A device for thermal sensing is disclosed based on one thermopile. The cold junctions of the thermopile are coupled thermally to a first channel comprising a first substance while the hot junctions of the thermopile are coupled thermally to a second channel comprising a second substance, the first and the second channel are separated and thermally isolated one from another. The device can further comprise a membrane to thermally and electrically isolate the thermopile and to mechanically support the thermopile. Particularly a liquid rubber, i.e., ELASTOSIL LR3003/10A, B can be used as a membrane material. Further disclosed is a method for fabricating such a device using micromachining techniques.

Abstract: An electrical power source is described. The electrical power source derives input power from a compressed gas which is fed into a transducer, generating electrical power. The compressed gas may be delivered to the unit by several means including manual pumps, thermal, chemical, or ammunition based sources, or connection to pressurized canisters. Optional power converting and feedback circuits and pneumatic valves serve to convert the raw output power into useful AC and DC output voltages, and to match the rate of power delivery to the applied electrical load.

Abstract: The present invention is an energy generating system which uses Lithium Metal Polymer (LMP) batteries in conjunction with a microturbine, a fuel cell, and commercial electrical power. The LMPs provide uninterruptible power when one or more of the other power systems fail.

Abstract: Because of the necessity of resolver for detecting a rotating position, which is very expensive, and noise suppression of the rotating position signal line on a doubly-fed machine, cost increase of the generator and reduced reliability due to possible failures are inevitable. In order to solve such problem, a generation system in the present invention is equipped with an exciter that estimates the slip frequency of the doubly-fed machine from each primary current I1 and voltage V1 and secondary current I2 and voltage V2 of the doubly-fed machine and excites the secondary of the doubly-fed machine at the estimated slip frequency.

Abstract: An electricity generation system having the ability to generate clean electrical power by mechanically capturing the power of the wind. The system utilizes one or more modular wind collecting sail assemblies that are mounted on an upright oriented pole assembly. The bottom end of the pole assembly is rigidly connected to a horizontally oriented elongated spring-motor primary winding axle who's opposite ends are journaled in a base assembly. Each end of the spring-motor primary winding axle is connected to a one way sprague coupling. That coupling is in turn connected to the spring-motor secondary winding axle having one or more spring motors mounted thereon. The inner end of each spring motor metal band is secured to the spring-motor secondary winding axle.

Abstract: This invention discloses a load and battery control device for controlling and distributing electrical energy in a vehicle electrical system comprising a generator, an electrical load, and a stored energy source. The device monitors and processes electrical signals generated by the vehicle electrical system and compares them to a vehicle operating state. The device operates on a switching system to controllably connect or disconnect the generator, electrical load, or stored energy source, or any combination thereof, with the vehicle electrical system to be consistent with a pre-determined vehicle operating configuration.

Abstract: A rectifier circuit powers three power conversion modules using a three phase AC input without a neutral connection. The rectifier circuit includes a first bridge rectifier that is connected to a first phase of the three phase AC input and that produces a first rectified waveform. A second bridge rectifier is connected to a second phase of the three phase AC input and produces a second rectified waveform. A third bridge rectifier is connected to a third phase of the three phase AC input and produces a third rectified waveform. A first inductor has one end that is connected to the first bridge rectifier. A second inductor has one end that is connected to the second bridge rectifier. A third inductor has one end that is connected to the third bridge rectifier. Opposite ends of the first, second and third inductors are connected to form a virtual neutral. A protection circuit prevents overvoltage when one of the DC outputs is shorted.

Abstract: A power supply control system for use with a tissue stimulating prosthesis, such as a cochlear implant. The power supply control system comprises a first battery (31), a second battery (32), at least a third battery (33), and a switching system (36). The first and second batteries (31, 32) are electrically connected in series to provide power to the prosthesis, while the third battery (33) is electrically connectable through the switching means (36) in parallel with either the first battery (32). The third battery (33) is electrically connected by the control system in parallel with whichever one of said first battery (31) or said second battery (32) has lowest voltage.

Abstract: A method and circuits for improving the inductive DC converter delivery of regulated current into the load(s), where the inductive DC converter provides the output voltage to an ensemble consisting of the load(s) and a current source or a current source circuit connected in series with the load. The load current is controlled by the current source or the current source circuit in series with the load and not by the inductive DC converter, which only provides the voltage and power required at the output, without directly controlling the load current. The inductive DC converter can operate under much more relaxed specs, while the load current regulation is much tighter, being current source controlled.