Abstract: The present invention relates to an ultra sensitive in-situ magnetometer system, and more particularly to an ultra sensitive in-situ magnetometer system that can in-situ monitor a magnetic moment of a magnetic thin film with sub-monolayer precision while depositing and growing the magnetic thin film in an ultra high vacuum (UHV) chamber.

Abstract: A system and method for tracking or otherwise determining positioning of an intracorporeal device is provided. The invention includes a device that may be inserted into a subject and tracked based on an imageable tag included with the device. The imageable tag is at least partially formed of a substance whose nuclei precess at a Larmor frequency different than the Larmor frequency of hydrogen when subjected to a polarizing magnetic field. MR data may be acquired from the imageable tag using an RF receiver tuned to the Larmor frequency of the substance and used to track movement of the device within the subject.

Abstract: A method and system for fat suppression with T1-weighted imaging includes a pulse sequence generally constructed to have a non-spectrally selective IR pulse that is played out immediately before a spectrally selective IR tip-up pulse. Thereafter, a fat suppression RF pulse is played out followed by the acquisition of fat-suppressed MR data. The pulse sequence maintains T1 contrast by not perturbing the non-fat signals from the IR preparation. The pulse sequence also ensures that the blood pool signal is homogeneously suppressed from the non-spectrally selective IR RF pulse. The pulse sequence also allows for increased fat suppression and provides flexibility for adjustment of the degree of fat suppression without affecting the view acquisition order for an image acquisition segment.

Abstract: The present invention discloses a method of simultaneously conducting more than one step of a radiofrequency phase cycle in a nuclear magnetic resonance (NMR) experiment. The method first involves providing a sample. Next, one or more radiofrequency pulses are applied to a plurality of spatially discrete slices of the sample under conditions effective to simultaneously conduct more than one step of a radiofrequency phase cycle in a single transient. Then, NMR signals generated from the step of applying the radiofrequency pulses are acquired. Finally, the NMR signals are processed to obtain an NMR spectrum.

Abstract: Coil sensitivity of a receive coil to a gradient null location is measured and, from the measurements, a coil calibration value is determined and used to modify the MR data acquired with that receive coil to reduce the adverse effects of gradient nulling on MR images. Coil sensitivity values are determined for each coil of a coil array and the data for each coil is respectively weighted. An image that is substantially free of gradient null artifacts or ghosting is then reconstructed from the weighted data.

Abstract: An NMR/ESR antenna is inserted into a magnet device for generating a static magnetic field, and irradiates a sample with an electromagnetic wave to detect a signal generated from the sample. The NMR/ESR antenna comprises a sample tube, an NMR solenoid coil, an ESR microwave cavity, and a microwave guide. The solenoid coil has a central axis coaxial with a central axis of the ESR microwave cavity, and orthogonal to a direction of a main magnetic field generated by the magnetic device.

Abstract: Cryostat configuration for keeping cryogenic fluids in at least one cryocontainer (1) which is suspended on thermally insulating suspension tubes (2) and/or suspension devices which are connected to an outer jacket (3) of the cryostat configuration, wherein the at least one cryocontainer (1) is centered relative to a container disposed further outside, preferably the outer jacket (3), using at least three centering elements (4) which are distributed about the periphery of the cryocontainer (1), wherein one end (5) of each centering element (4) abuts or is connected to the container disposed further outside, characterized in that in at least one of the cryocontainers (1), each end (6) of the centering elements (4) facing away from the outer jacket (3) is connected to an actuator (7) which exerts a pressure or tensile force on the respective centering element (4), and which is mounted to the cryocontainer (1) at at least one contact point (A, A?, B, B?), wherein, through fixation of the actuator (7) to the cryo

Abstract: The invention reduces a flow of a heat making an intrusion into an NMR probe, and uniformizes a spatial temperature generated in a sample pipe. A temperature modulated gas is supplied to a thermal anchor temperature modulated gas flow path constituted by a sample pipe insertion port around a sample pipe, and sample pipe insertion port structure bodies. A part of the temperature modulated gas is divided into a thermal anchor temperature modulated gas flow path by a temperature modulated gas division hole, and flows toward a thermal anchor. The thermal anchor is constituted by a porous member having a hole through which a gas can pass, and comes to the same temperature as the temperature modulated gas on the basis of a heat exchange with the temperature modulated gas.

Abstract: An RF coil suitable for use in imaging systems is provided which coil has a dielectric filled cavity formed by a surrounding conducting enclosure, the conducting enclosure preferably being patterned to form continuous electrical paths around the cavity, each of which paths may be tuned to a selected resonant frequency. The patterning breaks up any currents inducted in the coil and shortens path lengths to permit higher frequency, and thus higher field strength operation. The invention also includes improved mechanisms for tuning the resonant frequency of the paths, for selectively detuning the paths, for applying signal to the coil, for shortening the length of the coil and for controlling the field profile of the coil and the delivery of field to the object to the image.

Abstract: A method and apparatus for the detection of buried objects and subterranean anomalies using detector technology including, for example, existing metal detector technology is provided. A grid having defined coordinates is established over a desired search area, and a survey is conducted over the desired search area using a metal detector. Output data generated by the metal detector are assigned values, and such values are correlated to the various coordinates of the search area. A converter is used to convert an audible analogue signal of existing metal detectors to digital values. Such digital values are then plotted against coordinates of the search area in order to develop a graphical representation or map of the search area. The graphical representation can be used, together with other information from the metal detector, to discern qualitative characteristics of buried objects and/or subterranean anomalies encountered in the search area.

Abstract: An active system and method for determining the physical characteristics and geological composition of subterranean formations is described. Plane polarized electromagnetic waves at specific frequencies are transmitted by a mobile transmitting antenna held stationary in the far-field about a prospecting point. The plane polarized electromagnetic waves penetrate the Earth and return to the surface to be picked up at a separate mobile receiving antenna held stationary about a prospecting point. The differences in intensity and polarization between transmitted and received waves are measured and carry geological information. Further, a coordinated series of transmissions, receptions, and measurements are made, in which the angle of incidence and the revolution angle about a centerline emanating perpendicularly from the prospecting point are carefully and systematically varied and repeated for a specific set of frequencies.

Abstract: Measurements made by a resistivity imaging tool in a borehole having non-conductive mud in a conductive earth formation are corrected using the tool standoff. The correction involves removing a calibration signal determined in a medium of high conductivity from the measured impedance. The magnitude and/or the real part of the impedance may be used.

Abstract: A system for monitoring an electrical power system includes one or more transducer units, each of which has a current measuring device and a voltage measuring device coupled to a respective one of the phase conductors of the power system, and a transducer wireless communications device. The transducer wireless communications device of each transducer unit transmits the measured current data and voltage data to a base unit. The base unit generates one or more electrical parameters relating to the power system using the received current data and voltage data. Also, a method of monitoring a power system including generating current and voltage data for each phase conductor at a first location, wirelessly transmitting the current and voltage data to a second location, and generating at the second location electrical parameters relating to the power system using the current and voltage data for each phase conductor.

Abstract: A DC component detecting circuit (18) detects a small DC component contained in the AC output power of a grid-connection inverter device (12), accurately within a short period of time, and has a simple, small-size, and lightweight configuration. The DC component detecting circuit (18) comprises separators (21, 22) for separating a voltage which is proportional to the output current of the inverter device into voltages in positive and negative half periods, integrators (23, 24) for integrating the separated voltages in the positive and negative half periods, and an adder (25) for adding integral signals in the positive and negative half periods from the integrators (23, 24).

Abstract: A method and system for measuring noise of an on-chip power supply. In an embodiment, the system comprises a delay line that receives as an input a signal such as a square wave. The delay line may comprise a series of inverters connected to the power supply. The output of the delay line may combine the input signal and the noise signal from the power supply to produce a series of delayed versions of the input signal. Analysis of the output signal yields characteristics associated with the noise signal of the power supply such as its spectrum. In another embodiment, the system may comprise at least one mixer that modulates an input signal, such as a sinusoid, with the noise signal of the power supply. Demodulating the mixed signal then yields the noise signal of the power supply for further analysis.

Abstract: A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor includes an oscillator configured to generate an oscillating signal, a phase comparator coupled to the oscillator to output a signal responsive to a phase difference between the oscillating signal delayed by the first capacitor and the oscillating signal delayed by the second capacitor, an integration circuit coupled to the phase comparator to output an integrated signal made by integrating the signal responsive to the phase difference over a time period equal to a predetermined number of cycles of the oscillating signal, and a sample-and-hold circuit coupled to the integration circuit to output a signal made by sampling and holding the integrated signal at substantially an end of the time period.

Abstract: A bias tee for connecting a measurement device to a DUT, where the measurement device has a guard output, includes a DC port; a HF port; and a measurement port. The HF input port is guarded with the guard output during operation of the bias tee.

Abstract: An electroimpedance tomograph is provided with a plurality of electrodes (1), which can be placed on the body of a patient and are connected to a control and evaluating unit (20) via a selector switch (60). The control and evaluating unit (20) cooperates with the selector switch (60) such that two electrodes each are supplied with alternating current from an AC power source (22). The detected analog voltage signals of the other electrodes are sent into the control and evaluating unit (20) via a measuring amplifier (62) and AD converter (64) and are processed there in order to reconstruct the impedance distribution of the body in the plane of the electrodes therefrom. A symmetrical AC power source (22) is used to reduce common-mode signals.

Abstract: A method for reducing integral stress of a vertical probe with specific structure is disclosed. The vertical probe includes a probe tip, an insert part and a bent part. The bent part has a first circular arc and a second circular arc and the second circular arc is provided with a radius much greater than that of the first circular arc and the second circular arc is farther away from the probe tip and smoothly extends from the first circular arc. The integral stress of the probe during probing is effectively reduced to avoid overstress.

Abstract: The resolution and contrast of impedance measurements and scans are improved by using a non-contact impedance probe comprising an inner conductor configured to bear a measurement signal and an outer conductor configured to bear a shielding signal. The measurement signal and shielding signal are selected to increase the directionality of the flux emitted from the impedance probe. In one embodiment, the measurement signal and the shielding signal are phase locked signals. A sample may be placed in a basin having a conductive surface that receives the flux emitted from the impedance probe. By filling the basin with a conductive solution, direct contact between the probe and the sample may be avoided along with the associated variability in contact resistance. The small highly-directional flux emitting area achievable with the present invention enables high resolution high contrast non-contact scanning of biological and non-biological materials.

Abstract: A circuit board storage bag and a storage rack are disclosed. The stock in process, of the printed circuit boards between processes, is reduced while at the same time saving the space otherwise required for the stock, and the inward and outward delivery of the printed circuit boards are facilitated. A plurality of printed circuit board storage bags (1) each for accommodating a circuit board (90) each comprise a front surface portion (11) and a rear surface portion (12) opposed to the obverse and reverse surfaces, respectively, of the circuit board (90) accommodated in the circuit board storage bag (1) in closed state and connecting portions (13 to 15) for connecting the front surface portion (11) and the rear surface portion (12). The front surface portion (11) and the rear surface portion (12) connected to each other are adapted to bend at the connecting portions (13 to 15) thereby to open and close the circuit board storage bag (1) for use in transporting the circuit board (90) between processes.

Abstract: A probe card assembly can include an insert holder configured to hold a probe insert, which can include probes disposed in a particular configuration for probing a device to be tested. The probe card assembly can provide an electrical interface to a tester that can control testing of the device, and while attached to the probe card assembly, the insert holder can hold the probe insert such that the probe insert is electrically connected to electrical paths within the probe card assembly that are part of the interface to the tester. The insert holder can be detached from the probe card assembly. The probe insert of the probe card assembly can be replaced by detaching the insert holder, replacing the probe insert with a new probe insert, and then reattaching the insert holder to the probe card assembly. The probe insert and holder can be integrally formed and comprise a single structure that can be detached from a probe card assembly and replaced with a different probe insert and holder.

Abstract: A device for enabling testing of electrical paths through a circuit assembly is presented. The device may include a non-contact connector test probe for a testing a connector of the circuit assembly. A method for testing continuity of electrical paths through a circuit assembly is presented. In the method, one or more nodes of the circuit assembly are stimulated, connector pins of a connector on the circuit assembly are capacitively coupled to a non-contact connector test probe, and an electrical characteristic is measured by a tester coupled to the non-contact connector test probe to determine continuity of electrical paths through the circuit assembly.

Abstract: A probe device includes a tester; a probe card; a base card holder; an auxiliary card holder for adaptively mounting the probe card to the base card holder; and a conversion ring for allowing the auxiliary card holder to be fitted to the base card holder. In the probe device, the base card holder is configured to accommodate any one of selected different conversion rings and the conversion ring is the one chosen from the different conversion rings according to the probe card.

Abstract: An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.

Abstract: Parallel dies testing, mostly implemented on memory ICs—Integrated Circuits, significantly reduced overall test time. In order to minimize the need for physical probing, wafer probe card technology to allow simultaneous probing, ATE—Automated Test Equipment with enough channels and CPU power to handle the parallel testing. While new devices are designed with enough channels, and probe cards are designed and manufactured for each new device, the need to purchase new ATE to benefit from the technology is a heavy burden on parallel testing. It is proposed to interpose a multiplexer between the probe card and the ATE accompanied by a system that optimizes tester resources. The proposed system will allow test houses to benefit most from their investment without paying the full penalty of keeping less capable ATE.

Abstract: A test head for a semiconductor integrated circuit tester includes a main support structure defining a device interface board location, and a contact support frame that is displaceable relative to the main support structure for engaging a device interface board at the device interface board location.

Abstract: A test head is described for simultaneous test and/or burn-in of all of the chips on a semiconductor product wafer. The test head is suitable for testing wafers containing high powered chips such as microprocessors. A stimulus wafer is supported on a base with connections for power plus an interface to a test support computer. Attached to a first face of the stimulus wafer are all of the IC chips required to implement test circuits, power distribution, local memory, temperature sensing, and communication interfaces. The second face of the stimulus wafer is used to attach the first face of the product wafer using compliant connectors. The second face of the product wafer is available for cooling. Advanced flip chip connectors are preferably employed for assembling the chips on the stimulus wafer; they enable rework of any chips that prove defective. Embedded in the stimulus wafer are interconnection circuits plus through-wafer connectors. The product wafer is bumped at the I/O pads.

Abstract: A socket for an inspection apparatus for connecting an inspection circuit board and an inspected device includes: a plate-like housing including a first surface opposed to a surface on which a terminal of the inspected device is disposed and a second surface opposed to a surface on which an electrode of the inspection circuit board is disposed, the housing having a terminal-receiving holes which extends through the housing in the thickness direction thereof; and a connection terminal attached to the housing for electrically conducting the terminal of the inspected device and the electrode of the inspection circuit board, the connection terminal including a elastically deformable one-piece member which is a bent elongated member and being held in the terminal-receiving hole in the housing so as to be movable in the thickness direction of the housing.

Abstract: Provided are external input/output signal terminals, an interface circuit including a plurality of unit input/output circuits accompanying the respective signal terminals, a memory macro, a BIST (built-in self-test) circuit for performing a self test of the memory macro, and a logic circuit including a plurality of circuit blocks for generating various control signals. The unit input/output circuits are individually controlled by the various control signals. By externally controlling a specific one of the external input/output signal terminals, the logics of other external input/output signal terminals are individually controlled by the various internal signals.

Abstract: An apparatus for hot-probing integrated semiconductor circuits on wafers is disclosed that includes a support device for accommodating the wafer, a measurement card with electronic circuitry for functional verification of the integrated semiconductor circuits on the wafers, and a test head with contact needles which establishes an electrical contact between the measurement card and the integrated semiconductor circuits, wherein a detachable and coolable shield plate is provided between the measurement card and wafer in order to protect the apparatus.

Abstract: A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The system can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component.

Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.

Abstract: Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports.

Abstract: An exemplary testing device (2) includes plural lenses (22) for inspecting a display of a liquid crystal display (LCD) display (90), and analyzing devices (25) for receiving data obtained by the lenses and analyzing the data. The testing device including the plural lenses can collect a group of data simultaneously, and all needed data can be obtained in a short period. This helps assure that an accurate determination regarding true parameters of the brightness and uniformity of the display is made.

Abstract: Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection between unused I/O pins and the ground and/or VCC signals of an IC device to reduce ground bounce and VCC sag, respectively.

Abstract: An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

Abstract: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

Abstract: Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nth resistance elements, where N is an integral number equal to or more than 2, and a first to an nth cut-off elements connected in serial with each of the corresponding n(1?n<N) first to the Nth resistance elements of the first to the Nth resistance elements.

Abstract: Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Abstract: An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

Abstract: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

Abstract: A mechanism within an electronic system for adapting a field programmable gate array (FPGA) to a flash memory device that supports a synchronous serial peripheral interface (SPI) by coupling a small amount of MSI logic with the FPGA and the flash memory device, to configure the FPGA to a designed configuration state. The system comprises a first and additional FPGAs that support a serial configuration interface, SPI flash memory, and a parallel-load 8-bit shift register. SPI flash memory is initialized with a first configuration data pattern that is read from SPI flash memory and applied to the FPGAs during a first device configuration process resulting in the FPGAs each attaining a designed configuration state. The SPI flash memory is subsequently initialized with a second configuration data pattern by means of the first FPGA. Each FPGA attains another distinct designed configuration state by a second device configuration process.

Abstract: A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.

Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Abstract: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Abstract: A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.

Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

Abstract: An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to derive from the input signal a limited swing driver output signal. The receiver circuit is configured to derive from the limited swing driver output signal a limited swing receiver output signal.

Abstract: An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second power supply input region; and an interface circuit including a receiving circuit receiving the pair of differential signals that are input from the input pad region, wherein the first power supply input region and the second power supply input region are disposed in a direction along one side of the interface circuit so as to sandwich the differential signal input region.