Abstract: There is provided an output driver of a semiconductor device in which a slew rate variance is small despite an environmental change and a slew rate can be easily controlled. The output driver includes a main driver for driving an output terminal, a delay unit for controlling a delay time of a driving control signal in response to a delay control signal, and a pre-driver for pre-driving an input terminal of the main driver in response to an output signal of the delay unit.

Abstract: An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of which is connected to an internal node; and a second transistor which is formed at the substrate, a second gate of which is connected to a second power supply terminal, one of a second source and drain of which is connected to an input/output node, and the other of the second source and drain of which is connected to the internal node. The substrate of the second transistor has an electrically floating potential.

Abstract: A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first output unit for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, a second output unit for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal, and an output data initializer for, when a no-operation period is generated in a series of data output operations, initializing the arbitrary output data and supplying the resulting data to the first comparator.

Abstract: A source driver for controlling a slew rate of a liquid crystal display (LCD) and a method for controlling the slew rate is provided. The source driver includes a plurality of output buffers for driving data lines, and a bias circuit for varying a bias voltage inputted to the output buffers to control a slew rate of the output buffers.

Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Abstract: A computer circuit includes a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock. The clock and locally regulated voltage supply of each of the plurality of digital logic circuits are operable to vary under control of a common power controller. A synchronizer coupled to each of the plurality of digital logic circuits, and each synchronizer is operable to synchronize the exchange of data with at least one other digital logic circuit.

Abstract: A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.

Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Abstract: A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The logic gate design disclosed herein utilizes fewer transistors than traditional static designs and, therefore, requires a smaller amount of integrated circuit layout area while nevertheless affording higher speed operating performance than that exhibited in existing conventional circuits.

Abstract: A high speed ramp generator is presented. The high speed ramp generator is advantageous over the prior art because it provides a ramp response without the delay incident with a simple integrator approach. A closed loop system generates a continuous ramp and, in an open loop manner, subtracts a mirror of the current ramp from itself. A switch is provided which when open, triggers an immediate current ramp output that is not dependent on the amplifier or any other component of prior art feedback circuits. Two such ramp generators may be used in tandem to provide alternating portions of a precision ramp signal, such as may be used to cancel the magnetization current induced in the primary of an isolation transformer.

Abstract: A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for inverting the initial output signal to provide a final output signal. The input stage includes a first circuit including a plurality of transistors and a complimentary circuit including a plurality of transistors. When a low common mode input voltage causes the transistors of the first circuit to turn off, the transistors of the complimentary circuit will take over to accomplish the same task as the first circuit.

Abstract: A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a plurality of discrete biasing control signals. At least one input buffer is configured to adjust the biasing current in response to the plurality of discrete biasing control signals. The plurality of discrete biasing control signals are generated in response to variations in biasing current of the at least one input buffer. The method compares a representative bias current indicator from a replica of an input buffer with a reference current to determine variations in biasing current of at least one input buffer. A plurality of discrete biasing control signals are generated indicating a configuration of a biasing control for the at least one input buffer. The at least one input buffer is biased according to the plurality of discrete biasing control signals.

Abstract: A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by as simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. 2A. The modulation waveform is input to a VCO (voltage-controlled oscillator). In response to the modulation waveform, the oscillation frequency of the VCO is modulated, and the output clock that varies its frequency as illustrated in FIG. 2B is obtained. The frequency transition of the output clock involves such temporal variations as indicated by solid lines in FIG. 2C.

Abstract: A switching element for polymer electronic devices is constructed from organic materials.

Abstract: The present invention relates to an output buffer circuit. The output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and the internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and is composed of a plurality of switching elements and resistors so as to detect an offset voltage to compensate.

Abstract: An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit component coupled to the drive component. The latch further includes a reset threshold component coupled to the drive component for inhibiting oscillation of the drive component, and a latch component for passing the present state of the input signal to the output signal when configured as the repeater state and for maintaining the previous state of the output signal during transitions of a clock signal when configured as the latch state.

Abstract: The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association with the delay circuit. The correction circuit comprises a PMOS diode-connected in the forward direction, and resistors that connect the drain of the PMOS to the ground voltage VSS terminal side. The correction circuit outputs the control signal from an internal node provided between the resistors. Thus, when a power supply voltage rises, the voltage of the control signal also rises. Hence, gate-to-source voltages of the delay PMOSs are kept constant, and drain currents remain unchanged and a delay time is kept constant as well.

Abstract: A differential-type delay cell is disclosed herein. The delay cell provides two signal paths, each of which has a capacitor connected to the ground. The capacitance difference between the two capacitors determines the finest delay resolution of the delay cell. The delay cell does not rely on logic gates to increase driving capability. Additionally, unlike conventional approaches that implement multiplexing at the output end, the delay cell has de-multiplexing at the input end so that the components along one single signal path will be activated at any point of time.

Abstract: A gate clock circuit and related method for generating a gate clock signal according to a clock and an enable signal. The gate clock circuit includes a transmission unit for receiving an enable signal and a clock signal, a latch unit connected to the transmission unit for generating a latch signal, and an operation unit for processing a logic operation on the clock signal and the latch signal to generate a gate clock signal.

Abstract: A gate clock circuit and related method for generating a gate clock signal according to a clock and an enable signal. The gate clock circuit includes a transmission unit for receiving an enable signal and a clock signal, a latch unit connected to the transmission unit for generating a latch signal, and an operation unit for processing a logic operation on the inverse of the clock signal and the latch signal to generate a gate clock signal.

Abstract: A clamping circuit for restoring the DC level of video input signals. The clamping circuit comprises a coupling capacitor, a latch, a logic element, a charge switch, and a constant current source. The latch is coupled to the coupling capacitor to receive a video input signal therethrough and comprises a bias current source for generating first and second output signals in response to the AC-coupled signal and a reference voltage. The logic element receives the first and second output signals, generating a charging control signal to the charge switch. The charge switch, responsive to the charging control signal, is turned on to direct the current of the bias current source to the coupling capacitor, raising the level of the AC-coupled signal. Meanwhile, the constant current source continuously discharges the coupling capacitor slowly.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Abstract: In a over boosting prevention circuit that prevents over boosting of a voltage boosting circuit, ripples caused in the voltage boosting circuit are removed to prevent malfunctioning. The over boosting prevention circuit controls the output voltage Vout (<0V) of a charge pump circuit so that a difference (Vdd?Vout) between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit does not exceed a predetermined value VMAX. That is, the charge pump circuit performs boosting operation when Vdd?Vout<VMAX, and stops the boosting operation when Vdd?Vout>VMAX. Influence of the ripples caused in the charge pump circuit is removed because the reference voltage Vref to an operational amplifier is determined relative to a ground voltage Vss.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, and a charge pump type step-up circuit formed in the semiconductor substrate. The step-up circuit includes a charge pump circuit and a bipolar transistor. The charge pump circuit has an input line to which a power supply voltage is to be applied, and an output line through which an output voltage is to be output. The bipolar transistor is formed in the semiconductor substrate so as to be provided between the input line and the output line. The bipolar transistor is constituted so as to be turned ON when an absolute value of the output voltage is lower than an absolute value of the power supply voltage, and so as to be turned OFF when the absolute value of the output voltage is higher than the absolute value of the power supply voltage.

Abstract: Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers (OTAs), having a controllable transconductance Gm from a differential voltage input having first and second differential voltage input terminals to a single current output carrying a single phase current output signals, said first and second OTAs being provided with first and second control inputs, respectively, said filter input being coupled to the first differential voltage input terminal of said first OTA.

Abstract: The present invention provides a method for the correction of signal distortions in an amplifier device (20), wherein a digital PWM modulator (17) is operated with a variable-frequency system clock (18). The present invention likewise provides a device for the correction of signal distortions in an amplifier device (20).

Abstract: A 90-degree phase delay power divider part PSPD is connected to an input side of a carrier amplifier Amp1 and a peak amplifier Amp2, and a variable electric length power combiner VTL2 is connected to an output side thereof. A control signal Sig is applied through a control terminal Ctrl of the variable electric length power combiner VTL2, and adjustment is performed in correspondence to a carrier frequency band of a carrier signal RFs so that an electric length of the variable electric length power combiner VTL2 becomes nearly 90 degrees. As a result, an electric length of an output power combining circuit of a Doherty type amplifier can be made variable, and a power-added efficiency can be enhanced for a multi-band or broad band.

Abstract: A predistortion amplifier for compensating distortion includes an amplifying unit; a power detection unit; a distortion compensation table; a control unit; and a predistortion unit for generating a predistorted signal to be inputted to the amplifying device by performing a predistortion on the amplitude and a phase of the input signal, the predistortion being performed by using the compensation values corresponding to the input level outputted from the power detection unit stored in the distortion compensation table. The predistortion unit includes an offset adder for adding an offset value to an amplitude compensating value, the amplitude compensating value being assigned to the amplitude of the input signal by the compensation values based on the input level, and the offset value being determined regardless of the input level. Further, the control unit includes an offset generator for generating the offset value.

Abstract: A load circuit for use with a switching mode circuit. The novel load circuit includes a series inductive-capacitive network coupled to an output of the switching mode circuit and a circuit for providing a capacitance coupled to the output of the switching mode circuit. In an illustrative embodiment, the circuit for providing capacitance includes one or more lumped capacitors adapted to compensate for an intrinsic capacitance in the switching mode circuit. The load circuit may also include a shunt inductance coupled to the output of the switching mode circuit. In an illustrative embodiment, the load circuit is adapted to provide a Class-E load to a two-stage Class-E high power amplifier. The amplifier includes a driver stage, a novel Class-E inter-stage matching network (ISMN), and a high power stage using the novel load circuit.

Abstract: An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.

Abstract: A Miller-compensated amplifier, having an amplifier input and an amplifier output, comprises a first gain stage, a second gain stage, a third gain stage, and a capacitor. The first gain stage has the amplifier input as a first gain stage input thereto and a first gain stage output. The second gain stage has a second gain stage input, coupled to the first gain stage output, and a second gain stage output. The third gain stage has a third gain stage input, coupled to the second gain stage output, and provides an output voltage at the amplifier output. The capacitor is coupled between the amplifier output and the second gain stage input. The second gain stage amplifies a small signal part of a current received thereby and leaves a DC component thereof substantially the same.

Abstract: There is provided a high frequency power amplifier circuit capable of enhancing detection accuracy of an output level, necessary for feedback control of the high frequency power amplifier circuit, and capable of executing output power control with higher precision, With the high frequency power amplifier circuit, the detection of the output level, necessary for feedback control of the high frequency power amplifier circuit is executed by use of a current detection method, and in an electronic device comprising a differential amplifier for comparing an output power detection signal with an output level designation signal and for generating a signal for controlling a gain of the high frequency power amplifier circuit according to a potential difference between the two signals, a power source voltage with variation less than that for the power source voltage of the high frequency power amplifier circuit is used as the operational power source voltage of the output power detection circuit.

Abstract: A power amplifier arrangement includes a power amplifier with an input for a radio-frequency signal and an output for delivering a second radio-frequency signal. The second radio-frequency signal has a current and a voltage. A second element is configured to deliver a first signal derived from the current of the second radio-frequency signal. Furthermore, a first element is provided to deliver a second signal derived from the voltage of the second radio-frequency signal. An evaluating circuit detects in-phase components of the first and the second signal. As a result, in-phase current and voltage components can be detected together which produce the active power of the second radio-frequency signal by multiplication.

Abstract: An apparatus and a method for reducing drain modulation in a high power amplifier are provided, in which an adder supplies a current corresponding to a voltage reduced by a drain modulation, and a bias unit adds the current supplied from the adder to a DC bias and supplies the added current to a drain of a transistor. Accordingly, the drain modulation occurring in the transistor can be minimized and an output characteristic of the high power transistor can be improved.

Abstract: A digital phase locked loop includes a digital phase detector, a downstream digital filter and an oscillator. In addition, a frequency divider resides in a feedback path and has an actuating input for setting a divider ratio, the input of which is connected to the oscillator and the phase detector. The phase locked loop comprises a sigma-delta modulator having a data input for supplying a data word and having an actuating output for supplying a frequency setting word to the actuating input of the frequency divider. The data word is configured such that the sigma-delta modulator generates jitter in the frequency setting word, with the result that the signal which is applied to the feedback input of the phase detector is not constant over a relatively long period of time.

Abstract: Time base including two oscillators, one of which has a lower frequency than the other, the latter being intermittently set to standby mode, generating according to the same intermittency a first stable time reference (REF) by difference between the frequencies of the two oscillators, a second permanent time reference (RTC) being obtained by division of the frequency of the oscillator having the lowest frequency and the division factor being dependent on the pulses counted for the first oscillator (OSC1) during a time interval determined by the first stable time reference (REF).

Abstract: An oscillator comprises a data storage unit, an oscillation unit, and a control unit. The data storage unit is adapted to store a plurality of reference condition codes and a plurality of reference control codes. The oscillation unit is adapted to output an oscillation signal having an oscillation frequency that varies according to a control code. The control unit is adapted to generate the control code with a target value based on the reference condition codes and the reference control codes and a current condition code input to the control unit. Where control code has the target value, the oscillation unit outputs the oscillation signal with the oscillation frequency substantially equal to a target oscillation frequency.

Abstract: A delay cell for use in a voltage controlled oscillator includes a differential amplifier having a pair of outputs, a common source resistive element supplying current to said differential amplifier, a varactor arrangement between the outputs having a control input, and a pair of load resistive elements connected to the respective outputs. The delay cell has a simple design, a small die area, low power dissipation, constant amplitude of oscillation versus control voltage, and a Figure of Merit (FOM) comparable to that of LC oscillators.

Abstract: A test circuit comprises a delay circuit 11 with controllable delay, a phase comparator circuit 12 for comparing the phases between the clock signal S0 and a delay clock signal S1 delayed from the clock signal S0 by the delay circuit 11, a meas counter 13 for counting the number of outputs of the prescribed comparison result from the phase comparator circuit 12, a signal switching circuit 14 for switching an input signal to the delay circuit 11 from the clock signal S0 to a delay signal satisfying an oscillation condition where the delay signal is received from the delay circuit 11 and developing a ring oscillator, and a frequency measuring circuit 15 for measuring an oscillation frequency when the ring oscillator is developed, the delay circuit 11 includes a variable delay circuit 17 with variable delay units connected to control the delay in each variable delay units independently.

Abstract: An RF-discharge lamp stabilization system for preferred use in a Rubidium atomic clock, senses acoustic oscillations of plasma ions in the 20.0 kHz range to assess the performance of the lamp for determining radio frequency parameters of the lamp while the lamp is in operation and while the performance of an atomic clock is influenced by the plasma character, with lamp spectral outputs being actively stabilized for improved vapor-cell clock performance.

Abstract: An apparatus and method are provided for tracking the poles of an integrated RC filter as well as the absolute value of a current source. A single tracking oscillator contains integrated elements such as a programmable resistor and fixed capacitor or a programmable capacitor and fixed resistor. The programmable element is programmed such that a particular response from the RC filter is achieved and the word used to program the programmable element is then supplied to other integrated RC filters having components that were fabricated at the same time as the RC filter in the tracking oscillator. A highly accurate external capacitor or resistor is supplied to determinate the absolute value of the programming element, which is used to program one or more current sources containing the programmable resistor.

Abstract: An integrated quartz oscillator circuit is disclosed having a capacitive voltage divider, which has a first capacitor and a second capacitor, as well as having a first transconductance amplifier, which is placed in a loop connecting a first terminal and a second terminal of the first capacitor. An input of the first transconductance amplifier is connected to a center tap between the first capacitor and the second capacitor, an output of the first transconductance amplifier is connected to the first junction of the first capacitor, and the quartz oscillator circuit has a conductive element connected parallel to the second capacitor.

Abstract: A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinear shock wave generators, which are oppositely biased to produce periodic outputs that are mirror images of each other, one with a very steep rising edge and one with a very steep falling edge. The combined outputs would cancel each other completely but for the introduction of a slight time delay in one of them, which results in a narrow peak in the combined signals.

Abstract: The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.

Abstract: A bulk acoustic resonance and a method for fabricating the bulk acoustic resonator, the bulk acoustic resonator including: a substrate including an upper surface defining a predetermined area including a cavity; a resonance part positioned above the cavity and including a surface comprising a dimple; and an anchor part connecting the resonance part to the substrate. The resonance part includes: a lower electrode including a lower surface including a predetermined dimpled area and an upper surface opposite to the predetermined dimpled area; a piezoelectric layer stacked on the upper surface of the lower electrode; and an upper electrode stacked on the piezoelectric layer. Because direction of the vibration of the resonator is adjustable by adjusting position, area, and the number of the dimples, process freedom can be improved.

Abstract: There is provided an electronic component excellent in moisture resistance capable of ensuring electrical connection between electrodes and hermeticity of a sealed region including a vibrating part and suppressing an increase in size.

Abstract: A surface acoustic wave apparatus has a configuration by which the spurious of the higher-order transverse modes is suppressed and a SAW excitation intensity distribution is not changed in the propagation direction. The surface acoustic wave apparatus has at least one interdigital transducer, which is disposed such that a plurality of comb-shape electrodes respectively connected to common electrodes are interleaved, wherein a region with the plurality of interleaved comb-shape electrodes has a first overlapping region with a overlapping length constant over a whole area along a propagation direction of a surface acoustic wave and a second overlapping region formed on at least one side of the first overlapping region with a overlapping length weighted in the propagation direction of the surface acoustic wave, and wherein an overlapping-length weighting envelope curve in the second overlapping region has at least two changing points in the propagation direction of the surface acoustic wave.

Abstract: To reduce the internal resistance of small electromagnetic relays of a one-circuit three-contact gap type in order to make it possible to allow large electric currents and at the same time to improve the connection between the fixed contacts and the moveable contacts. Fixed contacts on the fixed terminals are positioned at each apex of an approximate triangle on the upper surface of the insulation base. Moveable contacts are installed on the lower surface of the moveable plate, and are respectively placed in a position which corresponds to each of the fixed contacts. The moveable plate is fastened to the moveable spring whose both ends are held onto the sides of the insulation base, and moves at a specified distance from the fixed contacts due to the pressure of the moveable spring. The construction results in the movable contacts contacting their corresponding fixed contacts at the three positions with uniform contact strength.

Abstract: An opening assist mechanism is for the cradle assembly of a circuit breaker including a housing enclosing separable contacts, and an operating mechanism for opening and closing the separable contacts. The operating mechanism includes a trip bar and a cradle assembly. The cradle assembly includes a first toggle link, a second toggle link pivotally coupled to the first toggle link by a first pivot, and a cradle member pivotally coupled to the second toggle link by a second pivot. The cradle member includes a third pivot and a latching portion structured to engage the trip bar when the cradle assembly is disposed in a position corresponding to the separable contacts being closed or otherwise closeable. The opening assist mechanism comprises an actuator, such as a kicker pin, disposed on the cradle member and structured to engage and move at least one of the first and second toggle links in response to an actuation of the operating mechanism.

Abstract: A superconducting magnet coil configuration comprising at least one section of a superconducting strip conductor, which is continuously wound in a cylindrical winding chamber (1) between two end flanges (2, 3) in several solenoid-like layers is characterized in that the section comprises an axial region of reduced current density (=notch region (10)), and the winding layers (6, 9) have hollow cylindrical blind regions (4a, 4b, 4c) which are filled with filler and which have different axial lengths, and radially sequential blind regions (4a, 4b, 4c) each alternately abut one of the two end flanges (2, 3) and are each radially separated from each other by at least one continuous winding layer (7), wherein the axial overlapping region of the blind regions (4a, 4b, 4c) forms the notch region (10). The inventive device thereby realizes a magnet coil configuration comprising a strip conductor which has a notch region for correcting inhomogeneities, wherein the mechanical load on the strip conductor is minimized.