Abstract: A dual feedback control system maintains the temperature of an IC-chip near a set-point while the IC-chip dissipates a varying amount of electrical power. The first feedback circuit sends electrical power to an electric heater with a variable magnitude that compensates for changes in the IC-chip power. The second feedback circuit passes a liquid refrigerant to an evaporator, which is connected to the heater, with a variable flow rate that reduces electrical power usage in the heater over that which occurs if the flow rate is fixed.

Abstract: One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.

Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.

Abstract: The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit.

Abstract: A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A measurement closest to the storage percentile is stored.

Abstract: A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A number of spatial regions on the wafer is designated. A first group of measurements from the set of measurements is obtained for a first spatial region of the spatial regions. A measurement closest to the storage percentile is stored.

Abstract: AC and/or DC testing of an optoelectronic device at the wafer level. In one example embodiment, a method of testing one or more devices at a wafer level includes generating a test signal; supplying the test signal to a single device on a wafer; providing an output of the single device to each of a plurality of devices on the wafer by way of a common electrical connection between the single device and the plurality of devices; providing an output of each of the plurality of devices to a corresponding return connection by way of electrical connections between the plurality of devices and the plurality of return connections; and receiving return currents from each of the return connections.

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

Abstract: A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode.

Abstract: A fault on a measuring point and information about a driving circuit of the fault are extracted. A signal value of the portion related to the fault on the measuring point and an input value of the driving circuit of the portion are obtained in case that a fault is not included. A fault candidate is extracted from detected faults based on a difference between a measured IDDQ value on a failed measuring point and a measured estimated IDDQ value in case that the fault is not included. An estimated calculation value to be a difference of an IDDQ value is calculated in case that each of the faults is included with respect to the case that the fault on the failed measuring point is not included. The estimated calculation value to be the difference is compared with a difference between the measured value on the failed measuring point and the measured estimation value so as to decide whether the fault candidate is the fault corresponding to a defective portion or not.

Abstract: Provided is electrical test equipment and method for testing semiconductor packages in an in-tray state. The equipment may include a loading site configured to receive a customer tray having a plurality of semiconductor packages therein, a test site configured to align the customer tray, and also configured to test all the plurality of semiconductor packages in the customer tray in-situ, a sorting site configured to sort the tested plurality of semiconductor packages in the customer tray, and an unloading site configured to unload the sorted plurality of semiconductor packages in the customer tray.

Abstract: A system for docking an electronic test head with a handling apparatus is provided. The system includes an assembly for at least partially aligning and subsequently bringing together the electronic test head and the handling apparatus. The system also includes a power driven actuator for providing only partially powered assistance in bringing together the electronic test head and the handling apparatus.

Abstract: A system and method is disclosed which relates to reading test strips. The method may include reading and storing initial values of a front photodiode and a rear photodiode, reading current values of the front and rear photodiodes, detecting at least one change between initial and current values in the front or the rear photodiodes, comparing the detected value change of one of the photodiodes with the value of the other photodiode, and determining a condition of the test strip in response to the resulting comparison.

Abstract: A coefficient indicating the relationship between a measurement voltage of voltage measuring unit and a voltage drop in a drain bias voltage due to drain current is determined based on an S parameter of a bias tee and an input impedance of the measuring unit. A voltage drop at the drain is determined from the coefficient. Based on the determined voltage drop, a drain bias voltage actually applied to the drain of an FET is determined. Also, a coefficient for converting the measurement voltage of the measuring unit into a drain current is determined based on an S parameter of a two-terminal-pair network of the bias tee and the input impedance of the voltage measuring unit. Based on the determined coefficient, a drain current actually flowing in the FET is determined.

Abstract: An interface 100, which connects a prober 14 having a contact probe 15 which contacts an electrode pad on a display panel 12 with a test head 13 which applies a test signal to the electrode pad and detects an output signal from the electrode pad. The interface 100 includes a performance board 1 which is attached to the test head 13 and transmits the test signal, a connection board 2 which is attached to the prober 14 and wires a conductive pattern on the performance board 1 to a conductive pattern corresponding to the electrode pad on the display panel 12, an elastomer connecting body 3 which electrically connects a first connection pad group 5 formed on the performance board 1 with a second connection pad group 6 formed on the connection board 2, and a quick lock 4 which fixes the performance board 1 and connection board 2 releasably.

Abstract: A digitally controlled high-voltage power supply and a method thereof are provided. The high-voltage power supply includes an output unit having a primary winding connected in parallel with a capacitor and a secondary winding inducing a voltage by current flowing in the primary winding. A switching unit switches on and off current flowing into the output unit with an LC resonance voltage across the primary winding. A digital interface unit provides communication interface for certain formats. A digital control unit controls the switching unit to be switched on and off, depending on control data input through the digital interface unit and the LC resonance voltage across the primary winding. Accordingly, switching operations are performed at time voltages across a switching device that fall in voltage-minimized intervals, which reduce an amount of heat generation from the switching device and switching device loss caused by the heat generation.

Abstract: An integrated receiver circuit for amplifying an input signal based on a reference signal includes two voltage converters to respectively convert the input and reference signals to level-converted input and reference signals. An amplifier stage includes a PMOS input differential amplifier driven by the converted input and reference signals, and an NMOS input differential amplifier driven by the input and reference signals. The amplifier stage is connected to a first control stage to compensate an output offset current generated by the amplifier stage. A second control stage is cascaded to the first control stage to provide a duty cycle correction of an output signal. The receiver circuit ensures amplification of an input signal even if a level of the reference signal is close to a supply voltage, the input and reference signals have a large variation range, or the input signal has an asymmetrical input swing about the reference signal.

Abstract: High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.

Abstract: A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semiconductor layer; a terminal contact semiconductor region on a surface portion of the terminal upper semiconductor layer adjacent to the cell region; an insulation layer on the terminal upper semiconductor layer having a first part adjacent to the cell region with a small thickness and a second part adjacent to the first part with a large thickness; and a conductive layer in the cell region and a part of the terminal region, the conductive layer extending from the cell region to the part of the terminal region beyond the first part of the insulation layer.

Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

Abstract: A circuit for setting a reference voltage in a floating gate circuit is configured as a precise voltage comparator circuit with a built-in programmable voltage reference. Once the one or more floating gates in the floating gate circuit are set during the a SET operation, the floating gate circuit is configured during a READ mode as a comparator circuit with a built-in voltage reference.

Abstract: A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the first capacitor are coupled in series between input signal and first voltage, and a common node is coupled to a first positive input terminal of the amplifier. The first switch is on during first period and off during second period. The second switch and the second capacitor are coupled in series between the input signal and second voltage, and a common node is coupled to a second positive input terminal of the amplifier. The second switch is on during second period and off during first period. The switchable bias current source biases the second input stage during first period, and switches to bias the first input stage during second period.

Abstract: An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.

Abstract: There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. There is also provided a method comprising receiving an input signal with a frequency between 2.5 gigahertz and 4 gigahertz and producing an output signal with a frequency approximately one-third of the frequency of the input signal.

Abstract: The embodiments of the present invention provide methods, systems, and devices for improving network management in a centralized network, which typically includes a central coordinator (CCO) that manages and schedules activities within the network. The embodiments of the invention provide a manner of selecting a CCO, including a backup CCO, best suited to manage the network based on a set of rules. Furthermore, the embodiments provide a manner of transferring the current CCO functions to a new CCO, e.g., via message exchanges. Moreover, a process of a backup CCO assuming the function of an unavailable CCO is also described.

Abstract: An internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL. The internal voltage generator includes a standby voltage generator that generates the DLL internal voltage as a reference voltage level, a controller that generates an active control signal in response to a power-down signal and an active signal, and an active voltage generator that generates the DLL internal voltage of the reference voltage level in response to the active control signal. After the power-down mode is ended, the active voltage generator is additionally operated during a predetermined time when the DLL is initially enabled. It is therefore possible to generate stabilized DLL internal voltages.

Abstract: Systems and methods for active clock deskew are provided. The disclosed systems/methods advantageously achieve desirable clock deskew at reduced power levels by employing a resistance-based distributed clock deskew technique. The disclosed technique has broad commercial/industrial applicability, e.g., in VLSI/ULSI chips, such as microprocessors, digital signal processing systems (DSPs), integrated circuits, application-specific integrated circuits (ASICs), micro-controllers, embedded systems, memory chips and the like.

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.

Abstract: A differential dual-edge triggered multiplexer flip-flop configured and operated to capture a first data signal on one edge of the clock and a second data signal on the other clock edge. By so doing, the output data rate of such a flip-flop is twice that of the input data rate but clocked with half the frequency, as compared to a single-edge triggered flip-flop implementation. This reduction in clock frequency reduces power consumption, as compared to a conventional single-edge triggered flip-flop, for an identical throughput. Such a flip-flop includes two main latches that operate in complementary fashion, that is, when one is holding data, the other is providing data for sampling by the corresponding circuitry in the multiplexer of the flip-flop. In an alternate embodiment, two main latches have both data inputs tied together to accomplish the function of a regular dual-edge triggered flip-flop. In this case, a data signal is sampled and passed to the output of the multiplexer during every clock transition.

Abstract: The present invention relates to integrated circuit storage element topologies with reduced sensitivity to process mismatch. Such storage elements have lower minimum retention voltage that enables lower standby voltage and therefore lower standby leakage and standby power.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a delay time control signal and a phase inverting element 9 inverting a phase of the signal, and an adjusting element 10, connected in series to the second delay element 8, to which the signal is propagated, wherein a total of the delay time of the second delay element 8 and the delay time of the adjusting element 10 is adjusted.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: A clamper circuit (1) receives an input signal (3) from the signal wire being clamped, i.e. the victim wire. The clamper circuit (1) also receives aggressor signals (5, 7) from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire. An output signal (9), for clamping the victim wire, is selectively enabled based on the logic states of the input signal (3) and the aggressor signals (5, 7). In addition to selectively providing a clamping signal, the clamper circuit (1) also has the advantage of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, thereby reducing worst case delay and improving the signal integrity.

Abstract: A method and apparatus for stabilizing the charge on a floating gate in a floating gate reference voltage generator. After an initial high voltage set mode, the method and apparatus allows for a controlled ramp down sequence to ramp down the voltages at the floating gate erase and program electrode generated by first and second bias sources coupled thereto, such that, when these bias sources are completely shut down in the generator, a more accurate voltage is set on the floating gate. The first bias source is preferably a voltage source and the second bias source is preferably a current source. The voltage at the erase electrode that is coupled to the floating gate is controlled during the ramp down sequence by shutting off the current source coupled thereto while allowing a feedback circuit in the generator to remain active.

Abstract: A floating gate circuit having a floating gate and a level shift circuit. A first tunneling device formed between a first and second tunnel electrode is included for removing electrons from the floating gate. Electrons are injected onto the floating gate without the use of a tunneling device, e.g., using avalanche injection. A first circuit is coupled to the floating gate for generating an output voltage at an output terminal. The level shift circuit has a second tunnel device coupled between the output terminal and the first tunnel electrode. The second tunnel device is for tracking changes in the characteristics of the first tunneling device connected to the floating gate. The level shift circuit level shifts the output of the floating gate circuit to a voltage that enables the tunnel device coupled to a floating gate to precisely set the floating gate to a desired voltage during a set mode.

Abstract: A semiconductor device includes: a transmission switch having multiple first FETs connected in series between a first terminal connected to a transmission part and a second terminal connected to a common connection portion, gates of the multiple first FETs being connected to transmission drive circuits; a reception switch having multiple second FETs connected in series between a third terminal connected to a reception part and a fourth terminal connected to the common connection portion, gates of the multiple second FETs being connected to reception drive circuits; and a booster circuit generates a boosted voltage having a positive or negative polarity on the basis of a given power supply voltage. When the transmission switch is in a conducting state, the boosted voltage is applied to gates of the multiple first FETs in order to switch the transmission switch to a non-conducting state.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A charge pump circuit with a regulated charge current where the amount of current flowing into the flying capacitor depends on the magnitude of the output voltage error, using an OTA to convert the output voltage error into a current. Thus the flying capacitor is not charged when the output load is very low or when the output voltage error is minimal. Voltage overshoots are reduced by a stop circuit which forces pulse skipping and which inhibits the charging of the flying capacitor. Current limiting devices further limit the charge current into the flying capacitor. Full short-circuit protection is provided in one preferred embodiment by current limiting the driver stage of the charge pump circuit. Except for pulse skipping, the charge pump runs at a constant frequency supplied by a clock.

Abstract: A charge pump circuit comprises a decoder for generating a plurality of control signals, a ring oscillator an output frequency of which varies according to the plurality of the control signals, a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator, and a fuse tuning unit for fixing one of the plurality of the control signals.

Abstract: The present invention provides a bandgap reference circuit, which includes a first current source, a second current source, a first reference circuit, a second reference circuit, and a selection circuit. The first reference circuit is coupled to the first current source and the second current source for outputting a first voltage signal. The second reference circuit is coupled to the first current source and the second current source for outputting a second voltage signal, wherein there is a phase difference between the first voltage signal and the second voltage signal. The selection circuit is coupled to the first reference circuit and the second reference circuit. One of the first voltage signal and the second voltage signal is alternatively selected by the selection circuit as an output reference voltage.

Abstract: A leakage current compensated multiplex driver system includes a multichannel mux having a predetermined leakage current at the switched side of each channel and a leakage current compensation circuit associated with the switched side of each channel for providing a compensation current matched to the predetermined leakage current.

Abstract: An amplifier circuit includes an input chopping circuit for chopping first and second input signals, a transconductance stage for amplifying an output of the chopping circuit and applying it to the input of a folded cascode stage, to the input of an un-chopping circuit, and to the input of a chopper-stabilized gain boost amplifier. The output of the un-chopping circuit drives sources of cascode transistors of the folded cascode stage. The gain boost amplifier includes another transconductance stage having another un-chopping circuit coupled to the gate of one of the cascode transistors of the folded cascode stage. The drains of cascode transistors of the folded cascode stage drive a class AB output stage. The amplifier provides both highly linear operation and low 1/f noise.

Abstract: A circuit arrangement is disclosed herein comprising an amplifier circuit having inputs configured to receive an input signal, and an output configured to provide an output signal. The circuit arrangement further comprises a first operational amplifier. The first operational amplifier includes inputs coupled to the inputs of the amplifier circuit, an output coupled to the output of the amplifier circuit, and a first compensation input. The compensation input is configured to feed an offset compensation signal to the first operational amplifier. The circuit arrangement further comprises a first compensation circuit configured to provide the offset compensation signal. The first compensation circuit is coupled to the inputs of the first operational amplifier. The circuit arrangement further comprises a deactivation circuit which is designed to temporarily deactivate the first compensation circuit.

Abstract: An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources.

Abstract: An apparatus and method amplifies a delta-sigma modulated signal and delivers the amplified signal to a power amplifier without distortion in a communication system. The apparatus receives a delta-sigma modulated signal, phase-delays the received delta-sigma modulated signal by a multiple of 360° for a bandwidth of the delta-sigma modulated basic signal, and amplifies the phase-delayed signal, facilitating implementation of a high-efficiency delta-sigma modulation-based amplification system.

Abstract: An amplifier, in particular for RF-applications, comprises a circuit board (2), at least one amplifier stage with at least one transistor package (8) arranged on the circuit board (2), and a feedback path (12) around the at least one transistor package (8), said feedback path (12) comprising a feedback element (15) with at least one capactive (C) element for blocking the flow of direct current through the feedback path (12) and preferably further comprising at least one inductive (L) and/or resistive element (R). In order to reduce negative effects on the performance of the amplifier due to long printed feedback lines, the feedback path (12) in an amplifier according to the invention is formed of a feedback bridge (9) comprising two feedback lines (13, 14) extending out of the plane of the circuit board (2) from two contact flags (10, 11) of the transistor package (8), and the feedback element (15) bridging over the transistor package (8) between the two feedback lines (13, 14).

Abstract: A compartmental gain limiter and a controlling method thereof. The compartmental gain limiter connects to an audio amplifier, which has a gain value and generates an output signal according to an input signal and the gain value. The compartmental gain limiter includes a comparator and a clamper. The comparator having a critical value receives the output signal and outputs a driven signal when the output signal is greater than the critical value. The clamper receives the driven signal and outputs a control signal according to the driven signal so as to clamp the output signal via the audio amplifier.