Abstract: Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations caused by, e.g., thermal fluctuations and astray fields. Stable MTJ cells with low aspect ratios can be fabricated using CMOS processing for, e.g., high-density MRAM memory devices and other devices, using the magnetic biasing layer. Such multilayer structures can be programmed using spin transfer induced switching by driving a write current perpendicular to the layers. Each free ferromagnetic layer can include two or more layers and may be a multilayered free ferromagnetic stack that includes first and second ferromagnetic layers and a non-magnetic spacer between the first and second ferromagnetic layers.

Abstract: A semiconductor memory includes a conducting film formed on a substrate; a ferroelectric film formed above or below the conducting film; a source electrode and a drain electrode disposed in positions opposing the conducting film with the ferroelectric film sandwiched therebetween and spaced from each other; and an insulating film formed between the source electrode and the drain electrode.

Abstract: A semiconductor device includes: a substrate; a first insulating layer formed on the substrate; a groove formed in the first insulating layer; a barrier layer formed on at least a side surface and a bottom surface of the groove; a second insulating layer formed on the barrier layer; a first electrode formed on at least the barrier layer and the second insulating layer; a ferroelectric layer formed over the first electrode; and a second electrode formed over the ferroelectric layer.

Abstract: An integrated electronic circuit includes electrical connections located in metallization layers superposed on top of a substrate. The circuit further incorporates a capacitor having two plates that are placed in two adjacent metallization layers. Each of the metallization layers containing a capacitor plate further contains electrical connections. The capacitor is compatible with a high level of integration of the circuit and may be produced using the damascene process.

Abstract: The semiconductor device comprises a capacitor formed over a semiconductor substrate 10 and including a lower electrode 32, a dielectric film 34 formed over the lower electrode and an upper electrode 36 formed over the dielectric film, a first insulation film 42 formed over the semiconductor substrate and the capacitor, a first interconnection 48 formed over the first insulation film and electrically connected to the capacitor, a first hydrogen diffusion preventive film 50 for preventing the diffusion of hydrogen formed over the first insulation film, covering the first interconnection, a second insulation film 58 formed over the first hydrogen diffusion preventive film and having the surface planarized, a third insulation film 62 formed over the second insulation film, a second interconnection 70b formed over the third insulation film, and a second hydrogen diffusion preventive film 72 for preventing the diffusion of hydrogen formed on the third insulation film, covering the second interconnection.

Abstract: A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions of the cross-shaped active areas. The word lines and digit lines provide a unique contact to each capacitor of the array of memory cells. Each memory cell has an area of 5 F2. An electronic system and method for fabricating a memory cell are also disclosed.

Abstract: A new structure is provided to replace the existing common planar capacitor structure used in printed circuit boards. The conventional common planar capacitor structure utilizes a single dielectric layer and embedded capacitors with different capacitances are achieved by adjusting the sizes of the embedded capacitors' conductive terminals. Since general applications usually require capacitors whose capacitance range covers several orders of magnitude, these embedded capacitors have significant differences in terms of their conductive terminals' sizes. This will make the manufacturing process more complicated and difficult. The new structure combines inorganic material having a specific dielectric constant and polymer having another specific dielectric constant into a singulated non-overlapping coplanar capacitor structure that is easy to manufacture and provides better precision.

Abstract: The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

Abstract: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.

Abstract: A solid capacitor and the manufacturing method thereof are disclosed. The solid capacitor consists of a dielectric layer and two electrodes. A plurality of holes formed by an opening process is disposed on surface of the dielectric layer. The two electrodes connect with the dielectric layer by the holes. By means of a plurality of high temperature volatile matters, the plurality of holes is formed on surface of the dielectric layer during sintered process. The holes are connected with the outside so as to increase surface area of the dielectric layer and further the capacity is increased. And the solid capacitor stores charge by physical means. Moreover, the solid capacitor can be stacked repeatedly to become a multilayer capacitor.

Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

Abstract: A flash memory device is disclosed. The flash memory device includes a housing enclosing a memory board, a serial port extending from the housing and electrically coupled to the memory board, and a swivel cap rotatably coupled and removably attached to the housing. In this regard, the swivel cap is rotatable between a closed position covering the serial port and an open position exposing the serial port, and the swivel cap is rotatable to at least one removal position enabling a separation of the swivel cap from the housing.

Abstract: A split gate field effect transistor is fabricated with a sidewall of a control gate electrode aligned with a sidewall of a floating gate electrode. The aligned sidewalls are on a side of the split gate field effect transistor device opposite the control gate electrode channel of the split gate field effect transistor device. The aligned sidewalls provide for enhanced performance of the split gate field effect transistor device.

Abstract: A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a volatile memory device having a volatile memory device formed therein.

Abstract: The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.

Abstract: A semiconductor device and a method of manufacturing the same can satisfy a design rule reduction in a peripheral region. The semiconductor device includes a silicon substrate having an activation region formed by recessing a center portion of the silicon substrate lengthwise. A device isolation layer is formed on the silicon substrate for restricting the activation region. A gate is formed on the recessed activation region and has a smaller length than that of the recess, a source/drain extension region formed on a surface of the recessed activation region having no gate, spacers formed on both sidewalls of the gate, and a source/drain region formed on a surface of the activation region including the spacers at both sides of the gate.

Abstract: A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another side of the floating gate, where the source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line.

Abstract: In non-volatile memory devices and methods of manufacturing the non-volatile memory devices, a barrier layer having an upper portion of silicon nitride and a lower portion of silicon oxide is formed on a substrate by providing a silicon oxide layer on the substrate and performing a radical nitridation process on an upper portion of the silicon oxide layer. A trapping layer including silicon nitride is formed on the barrier layer. A blocking layer and a gate electrode layer are subsequently formed on the trapping layer. The gate electrode layer, the blocking layer, the trapping layer and the barrier layer are then partially etched to provide a gate structure.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.

Abstract: High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A floating-gate layer, having at least one silicon-containing layer, overlies the tunnel dielectric layer. An intergate dielectric layer overlies the floating-gate layer, and a control gate layer overlies the intergate dielectric layer. A first silicon oxide layer is formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extends across a first portion of an edge of the tunnel dielectric layer. A second silicon oxide layer is formed on a sidewall of the trench and extends across a second portion of the edge of the tunnel dielectric layer.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract: A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction and connect to the drain regions of the memory units in the same row. Word lines are arranged in parallel in the column direction and connect to the select gates of the memory units in the same column. Control lines are arranged in parallel in the column direction and connect to the control gates of the memory units in the same column. The control lines are grouped into several groups with n control lines (n is a positive integer not less than 2) in one group, and the control lines in each group are electrically connected to each other.

Abstract: Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 ? to about 15 ?.

Abstract: A semiconductor device includes a semiconductor region; a first high dielectric constant insulating film provided on the semiconductor region, the first high dielectric constant insulating film being a film other than alumina; a second high dielectric constant insulating film provided on the first high dielectric constant insulating film, the second high dielectric constant insulating film being an alumina film; and a conductive layer provided on the second high dielectric constant insulating film.

Abstract: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

Abstract: A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a p-doped semiconductor material, so that the memory cell is particularly suitable to erase through hole injection from the gate.

Abstract: A trench type IGBT has a gate oxide lining the side walls and bottom of the trench which have a thickness greater than 1500? and in the range of 1800? to 2500?, and preferably 2000? to increase the device short circuit capability.

Abstract: A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.

Abstract: In a lateral double-diffused field effect transistor of the present invention, a gate insulating film includes a first gate insulating film covering a source diffusion layer up to a region beyond the pattern of a body diffusion layer and a second gate insulating film having a film thickness larger than that of the first gate insulating film and covering a region closer to a drain diffusion layer than the region covered by the first gate insulating film. A boundary between the first gate insulating film and the second gate insulating film is composed of a straight portion parallel to a side of the pattern of the body diffusion layer and a corner portion surrounding an vertex of the pattern of the body diffusion layer from a distance. A distance between the vertex of the pattern of the body diffusion layer and the corner portion of the boundary is equal to or smaller than a distance between the side of the pattern of the body diffusion layer and the straight portion of the boundary.

Abstract: A semiconductor power device has a semiconductor body with a first conductivity type. A trench extends in the semiconductor body and accommodates an insulating structure, which extends along the side walls and bottom of the trench. The insulating structure surrounds a conductive region, arranged on the bottom of the trench, and a gate region, arranged on top of the conductive region, the conductive region and the gate region being electrically insulated by an insulating layer. A body region, with a second conductivity type, extends within the semiconductor body, at the sides of the trench, and a source region, with the first conductivity type, extends within the semiconductor body, at the sides of the trench and within the body region. The conductive region and the gate region are both of polycrystalline silicon but have different conductivities and doping levels so as to have different electrical characteristics such as to improve the static and dynamic behaviour of the device.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near the center of the gate insulating film in the thickness direction. The peak value of nitrogen concentration in the gate insulating film is equal to or greater than 10 atm % and less than or equal to 40 atm %.

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract: Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013/cm2, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1×1016/cm2, thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Abstract: A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.

Abstract: A thin film transistor array substrate having a display area and a non-display area is provided. Pixel units, scan lines and data lines are disposed within the display area, and the scan line and data line are electrically connected to the corresponding pixel units. The non-display region has first chip bonding area and at least one first connecting line disposed within the non-display region. Scan line terminals and first bonding pads are disposed within the first chip bonding area. The scan line terminal is electrically connected to the corresponding scan line. The first connecting line is arranged between two of the adjacent chip bonding areas for making the first bonding pads within the adjacent chip bonding areas electrically connect to each other. The first connecting line comprises conductive layers which are electrically connected to one another.

Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.

Abstract: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

Abstract: A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in a width direction of the semiconductor film on both edge portions in the channel region.

Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

Abstract: In a power supply apparatus in which a source of a MOSFET is connected to a node of a rectifier diode and a choke coil through a resonance coil, a series circuit including a capacitor and a MOSFET i s connected to a series circuit including the resonance coil and the rectifier diode, and the MOSFET and the MOSFET are driven by PWM control so that the MOSFET and the MOSFET are alternately turned on with a period in which both MOSFETs are turned off, a resistor is connected in parallel with the capacitor, and optionally another diode is connected in series with the resistor.

Abstract: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with an insulating film which applies lower stress than the stresses applied by the above-described two films.