Abstract: A down converter includes an interface section, which connects the down converter to switches and respective driver circuits, wherein the driver circuits and the switches are combined on an integrated circuit. The driver circuits include a high-side driver circuit, and a low-side driver circuit. The integration of the driver circuits with the switches reduces parasitic inductance, particularly in power applications.

Abstract: A complimentary metal oxide semiconductor (CMOS) circuit may include a CMOS output stage comprising at least one p-channel metal oxide semiconductor (PMOS) component and at least one n-channel metal oxide semiconductor (NMOS) component connected in series between first and second voltage rails, a juncture between the at least one PMOS component and at least one NMOS component providing an output. A predriver stage includes first and second predriver paths electrically connected between at least one input and the output stage. The first predriver path is configured to perform a logic function on the at least one input and to provide a first logic signal to an input of the at least one PMOS component. The second predriver path is configured to perform the logic function on the at least one input and to provide a second logic signal to an input of the at least one NMOS component.

Abstract: A pre-emphasis apparatus of a LVDS transmitter includes a pre-emphasis signaling generation unit and a pre-emphasis current output unit. The pre-emphasis signal generation unit generates a pre-emphasis pulse signal based on N parallel data signals received from an external source and N-phase clock signals received from a phase locked loop, where N is an integer greater than 1. The pre-emphasis current output unit provides an additional current for a pre-emphasis operation to a current source of a LVDS driver in response to the pre-emphasis pulse signal generated by the pre-emphasis pulse signal generation unit. The pulse signal for pre-emphasis is generated based on the parallel data signals received from the external source and the multi-phase clock signals, which are output from the phase locked loop for performing a sampling of the parallel data signals.

Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element.

Abstract: A method for testing a data recovery circuit (DRC) includes disturbing a running variable in a closed control loop of the DRC, as the DRC is processing a received test signal. Data recovered by the DRC, while the DRC was affected by the disturbance, is evaluated. Other embodiments are also described and claimed.

Abstract: The calculating unit includes a dual rail input stage, a switching stage for a bit to be calculated and an output stage for an output bit, wherein the output stage provides a dual rail output. The switching stage is not implemented in dual rail technology but according to a “one-hot” realization. The switching stage includes at least one internal node which is, in the preparation mode according to a control signal on a control line from a control means, connected to a reference potential, while the node potential circuit for handling the internal node in the data mode is not active. Thus, an area-efficient, cross-current-reduced and reliable calculating unit is obtained, which may additionally be clocked at high speed, as a transition form a preparation mode to a data mode takes place without time-consuming discharge processes.

Abstract: A signal detector for detecting and indicating the duration of a signal pulse by comparing the relative polarities of two voltages generated during the two states of the pulsed signal.

Abstract: This invention provides a clock switching circuit that can switch clocks without causing a hazard or a distortion of a duty ratio of the clocks. The clock switching circuit of this invention includes a first synchronization circuit that synchronizes a clock selection signal with a first clock, a second synchronization circuit that synchronizes with a second clock the clock selection signal that has been synchronized with the first clock by the first synchronization circuit and a clock selection circuit that outputs “1”, that is a high level, in synchronization with the clock selection signal that has been synchronized with the first clock by the first synchronization circuit and after that selects the second clock in synchronization with the clock selection signal that has been synchronized with the second clock by the second synchronization circuit.

Abstract: In case of time-stationary encoding, every instruction that is part of the processor's instruction-set controls a complete set of operations that have to be executed in a single machine cycle. These operations may be processing several different data items traversing the data pipeline. Time-stationary encoding is often used in application-specific processors, since it saves the overhead of hardware necessary for delaying the control information present in the instructions, at the expense of larger code size. A disadvantage of time-stationary encoding is that is does not support conditional operations. The invention proposes to dynamically control the write back of result data to the register file of the timestationary processor, using control information obtained by the program. By controlling the write back of data at run-time, conditional operations can be implemented by a timestationary processor.

Abstract: An active load arrangement is used to provide proper output load to an object TO under test. The arrangement Z comprises a voltage_controlled transistor MOSFET having a source S, a gate G and a drain D. The drain D is associated with the gate G and connected to an arrangement input I2 associated with an output O1 of the object under test. The source S is connected to an arrangement output O2 associated with an input I1 of the object under test. A feedback arrangement is connected to the source S and the gate G. The feedback arrangement changes phase and amplitude of the gate-to-source voltage by varying frequency in order to obtain low impedance at low frequencies and high impedance at high frequencies.

Abstract: A switching circuit of the present invention can be advantageously used in an electronic control unit mounted on an automotive vehicle. The switching circuit is constituted by a pair of P-channel MOS-FETs connected in series between an input terminal and an output terminal. Sources of both MOS-FETs are connected to a common source junction and gates thereof are connected to a common gate junction. A Zener diode connected between the common source junction and the common gate junction is used for protecting the MOS-FETs. A resistor is connected in parallel to the Zener diode to bring the switching circuit to a non-conductive state when the gate voltage at the common gate junction becomes indefinite and a high voltage is supplied to the output terminal. In place of the resistor, an additional P-channel MOS-FET may be used in the switching circuit to bring the switching circuit to the non-conductive state when the voltage at the common gate junction becomes indefinite.

Abstract: A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locked clock signal over a second frequency range. The second circuit is configured to signal the first circuit to lock onto the clock signal to provide the second locked clock signal as the frequency changes from the first frequency range to the second frequency range. Also, the second circuit is configured to signal the first circuit to provide a locked one of the first locked clock signal and the second locked clock signal in a locked output clock signal.

Abstract: Matched current delay cells and a delay locked loop based on such cells that may be used for timing data interfaces between semiconductor devices is described. In one embodiment, the delay cell includes a delay cell having a PMOS portion and a NMOS portion, gates of the PMOS portion being coupled to a vp-bias and gates of the NMOS portion being coupled to a vn-bias, the delay cell further being coupled to a reference clock to drive a pulse output of the delay cell, a first bias generation circuit to generate the vn-bias based on a phase comparison of the pulse output to the reference clock, and a second bias generation circuit to generate the vp-bias based on a reference voltage and the vn-bias.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.

Abstract: Master-slave flip flop including a master latch having a data input for receiving a data input signal, an inverting clock input for receiving a first clock signal, and a data output, a slave latch having a data input which is connected to the data output of the master latch, a clock input for receiving a second clock signal, and a data output for outputting an output signal, and a time delay element connects the clock input of the slave latch to the clock input of the master latch.

Abstract: The instantaneous value of an intermediate waveform I is the instantaneous value of a unipolar waveform U multiplied through amplification by an upscaling factor UF of 1.5. A plateau value P is subtracted from the intermediate value I, and the result of this subtraction is multiplied by a multiplication factor MF of 0.6. The result of the multiplication is added to the plateau value P, which sum becomes an auxiliary waveform A. During the fall-below periods F, the value of a combined waveform C is arranged to follow whichever is the highest of the auxiliary value A and the plateau value P. Outside the fall-below periods, the value of the combined waveform C follows whichever is the highest of the unipolar value U and the plateau value P. This combined waveform C has, for a given plateau level P, a narrower fall-below window. Phase-chopping thus has an effect on the power of the output signal over a greater range of the cycle than can be provided by the corresponding prior art arrangement.

Abstract: A frequency generator is specified which includes a pulse generator with a downstream signal conditioning circuit. The pulse generator is designed for recurring emission of pulses. The signal conditioning circuit derives a signal at a desired frequency from higher harmonic frequency components of the electrical pulses. The circuit makes it possible to produce a radio-frequency signal from a low-frequency clock signal, with little complexity and a small chip area. This is suitable, for example, for mixing with a further signal frequency onto a carrier frequency or an intermediate frequency in transceivers.

Abstract: A method for generating spread spectrum clock signals having harmonic emission suppressions is disclosed. A set of delayed clock signals is initially generated by delaying a high-speed clock signal via a set of delay modules. Then, the leading edge of a first one of the delayed clock signals is selectively combined with a trailing edge of any one of the delayed clock signals to form a half-period spread spectrum clock signal having low harmonic emissions.

Abstract: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.

Abstract: Methods and systems for a DC offset correction loop for a mobile digital cellular television environment are disclosed. Aspects of one method may include removing at least a portion of a DC offset from output of an amplifier. The DC offset may be removed from a single stage amplifier, or from each stage of a N stage amplifier, where N may be an integer. The DC offset may be removed by using second differential signals generated from first differential signals, where the second differential signals may be communicated to inputs of the amplifier. The first differential signals may by a first circuit that integrates outputs of the amplifier. The first circuit may perform the integration using a variable corner frequency that may be adjusted by changing a resistance of at least one variable resistor in the first circuit.

Abstract: A voltage divider circuit can be realized by dividing a higher than rated operating voltage across a plurality of MOS transistors. The voltage divider circuit can be used for a wide variety of ratios of low and high operating voltages. Only one gate input voltage is needed, minimizing power dissipation, heat, and hot carrier effects. The voltage divider circuit is employed in a voltage driver circuit to generate a high output voltage in response to a low voltage input while minimizing damage to the MOS transistors within the voltage driver circuit.

Abstract: In the structure in which an input signal IN and a reverse-phase signal XIN thereof are externally input, an external IC is required for generating the reverse-phase signal XIN, and the number of required input signal terminals is two. A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of a signal externally input from the substrate to generate complementary signals from a single-phase input signal IN. The complementary signals generated by the complementary generator unit (11) are level-shifted by a level shift unit (14). Therefore, it is no longer necessary to externally input the reverse-phase signal XIN.

Abstract: A charge pump comprises a single voltage multiplier stage (1) which converts an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO). An oscillator (2) receives the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period (Tr1, Tr2) which is substantially proportional to a squared input voltage (VDD2).

Abstract: A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.

Abstract: Provided is a charge pump booster circuit capable of outputting desired boosted voltage that is not limited to an integral multiple of input voltage and further outputting stable boosted voltage even if a load fluctuates. In the charge pump booster circuit, gate voltage of a transistor for pumping is controlled according to voltage, which is a feedback of boosted voltage, to control the boosted voltage.

Abstract: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Abstract: An audio amplifier comprising a Class D audio amplifier having an input receiving an analog input signal, a pulse width modulation stage for converting the analog input signal to a pulse width modulated signal, a driver stage receiving the pulse width modulated signal and for producing a driver PWM signal and an output switching audio amplifier stage receiving the driver PWM signal and providing an amplified PWM signal; an output filter stage receiving the amplified PWM signal for converting the amplified PWM signal into an analog audio signal; and a linear output amplifier stage receiving as inputs the analog input signal and the output of the output filter stage, the output of the output filter stage serving to bias the linear output amplifier stage.

Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.

Abstract: It is an object of this invention to provide a high-frequency amplifier which can efficiently amplify an input signal in a plurality of different frequency bands in a simple configuration. The high-frequency amplifier is configured such that an RF signal having n frequencies (f1>f2 , , , >fn) applied to the amplifier is converted by an impedance conversion circuit to a higher impedance than the output impedance of the amplifier, and is branched into the highest frequency f1 and lower frequencies lower than that by a high-pass filter and a low-pass filter. Frequency f1 passes high-pass filter 31, and is thereby converted to 50 ohms. The frequencies lower than frequency f1 filtered by the low-pass filter are converted to a high impedance by an impedance conversion circuit, and are branched into the second highest frequency f2 and lower frequencies by high-pass filter 32 and low-pass filter 42.

Abstract: An amplifier is disclosed that contains a transistor (BJT), a switch (MOSFET), and a transformer. The collector of the BJT is connected to an end of the transformer while the base of the BJT is connected to a point between the ends of the transformer through the MOSFET. When the amplifier is in an active mode in which the amplifier has gain, signals supplied to the amplifier are provided to the transformer through the BJT. When the amplifier is in a bypass mode in which the amplifier does not have gain, signals supplied to the amplifier are provided to the transformer through the MOSFET and the BJT is turned off. The amplifier is designed such that the amplifier characteristics are optimized and then the MOSFET is connected to the transformer such that the input impedance of the amplifier is independent of the mode.

Abstract: An AC amplifier has an amplification circuit, and a bias circuit connected together by connecting wiring. The bias circuit receives an input of an AC signal from the amplification circuit via the connecting wiring. A DC voltage of the bias circuit conformed to the amplitude of the AC signal of the amplification circuit is supplied to the amplification circuit via the connecting wiring.

Abstract: A system and a method create a pre-distorted signal y(k) from an interpolated broadband baseband signal x(k) for a transmitter power amplifier having at least three branches to which the signal x(k) is respectively connected on the input side. A first branch contains a distortion device for taking into account memory effects of the transmitter power amplifier to which the signal x(k) is supplied on the input side. Where 2=j=n, each other j-th branch contains the following serially mounted elements: a deceleration device with a signal x(k) supplied on the input side, a first adder, a digital low-pass filter, and a second adder, the output signal formed by the second adder being used to create the pre-distorted signal y(k). The distortion device pertaining to the first branch is connected, on the input side, to another input of the second adder of the second branch, and on the output side, to another input of the first adder of the second branch.

Abstract: A power amplifier pre-distorter is formed by a FIR filter structure which includes an individual look-up table for each filter tap, where each look-up table represents a sampled polynomial in a variable representing signal amplitude, and means for selecting, from each filter tap look-up table, a filter coefficient that depends on the amplitude of a corresponding complex signal value to be multiplied by the filter tap. A training method for such a pre-distorter determines (S1) a first estimate of a first look-up table assigned to a first filter tap, assuming a second look-up table assigned to a second filter tap is set to predetermined table values. Thereafter the method determines (S2) a second estimate of the second look-up table, assuming the first look-up table is set to the determined first estimate.

Abstract: A bias-T circuit including a radio frequency signal input device and a dc bias input device connected in parallel with an output. The radio frequency signal input device includes a capacitive element in series with the output. The dc bias input device includes a radio frequency transistor for controlling the dc bias level at the output. The fT value of the radio frequency transistor is at least 30 GHz, more preferably at least 50 GHz and yet more preferably at least 70 GHz.

Abstract: A predistortion linearized amplifier system that uses analog polynomial based predistortion is disclosed. An analog polynomial function generator receives polynomial parameter updates from a polynomial parameter generator. The polynomial parameter generator uses a combination of analog and digital signal processing to create the parameter updates. This processing is performed on input signal amplitude, detected using analog circuits, and RF coupled samples of the input signal, and the output signal. By using a combination of analog and digital signal processing means, digital processing can be performed at sub-Nyquist rates, significantly reducing the cost of digital circuits. Also, since the predistortion modulation signal is created with an analog function generator, time correlating delay is minimized reducing circuit costs.

Abstract: Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. A secondary output is added to the amplifier for the purpose of steering the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: A method and apparatus is provided for use with a power amplifier to provide a regulated supply to the power amplifier. The invention uses a combination of voltage and current regulation to overcome the problems encountered in the prior art. In one example, voltage regulation is used at high power levels, while current regulation is used at low power levels.

Abstract: A first and a second resonator are fabricated monolithically adjacent to one another. The first resonator is the reference resonator. The resonant frequency of the second resonator is offset by a difference frequency Fo from the first resonator. Each resonator is included within an oscillator. A mixer receives the output of both oscillators. A low pass filter receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo.

Abstract: A semiconductor integrated circuit is provided with an external interface circuit, which includes a clock generation circuit for generating a synchronous clock signal to establish synchronization between data input and output through input and output of a data string sectioned at fixed intervals. The clock generation circuit includes a self-excited oscillator circuit serving as an oscillation source for the synchronous clock signal, and a control circuit for trimming the oscillation frequency of the self-excited oscillator circuit. The control circuit detects the sections made at the fixed intervals to the data string, measures the section interval based on an oscillation output of the self-excited oscillator circuit, and controls the oscillation frequency of the self-excited oscillator circuit to match the measurement value to a target value.

Abstract: A radio frequency (RF) device includes first and second electrodes and a polar dielectric made from a material having electrostrictive properties between the first and second electrodes. The polar dielectric and the first and second electrodes collectively form an active device having an operational frequency band. The RF device also includes one or more layers that affect the acoustic properties of the RF device such that the RF device absorbs RF energy at a frequency that is within the operational frequency band, whereby the RF device is an active device because the RF energy is absorbed at a frequency within the operational frequency band.

Abstract: A crystal oscillation circuit can correctly suppress the resonance of a B mode, thereby correctly excite the resonance of a C mode. Since the crystal oscillation circuit uses a quartz oscillator of an SC cut or an IC cut, the B mode (unnecessary mode) frequency is close to the C mode (main mode) frequency. Therefore, a C mode resonance circuit (main mode resonance circuit) for passing a C mode frequency and a trap circuit for suppressing the oscillation at an unnecessary mode frequency are provided in the feedback loop of the crystal oscillation circuit.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: The invention relates to oscillation detection and, more particularly, concerns a method and apparatus for identifying oscillation in a signal due to feedback, permitting appropriate action to be taken to suppress the oscillation. The method involves using an FFT device or similar to convert a signal at each of a series of successive time windows into the frequency domain, calculating, for each of a plurality of frequency bands, the change in signal phase from a time window to a subsequent time window, and comparing, for some or all of said frequency bands, the results of the calculation step to one or more defined criteria to provide a measure of whether oscillation due to feedback is present in the signal. For additional discrimination, the change in signal amplitude from a time window to a subsequent time window may also be calculated for each of the frequency bands, and the result compared with one or more further defined criteria. The invention has particular application in hearing aid devices.

Abstract: A voltage controlled oscillator device with amplitude control is provided. A voltage controlled oscillator (VCO) (101) receives an input current. An error amplifier (117) compares an amplitude of oscillation (113) of the input current to a reference voltage (115) to provide a difference, and outputs a shunting current responsive to the difference.

Abstract: A differential transmission line according to the present invention includes: a substrate 101; a ground conductor layer 105 formed on a rear side of the substrate 101; and a first signal conductor 102a and a second signal conductor 102b disposed in parallel to each other on a front side of the substrate 101. The first signal conductor 102a and the ground conductor layer 105 compose a first transmission line, whereas the second signal conductor 102b and the ground conductor layer 105 compose a second transmission line. The first transmission line and the second transmission line compose a differential transmission line 102c. The differential transmission line 102c includes a curved region 104a, with a straight region 104b being connected to each end of the curved region 104a.

Abstract: A differential transmission line according to the present invention includes: a substrate 101; a ground conductor layer 105 formed on a rear side of the substrate 101; and a first signal conductor 102a and a second signal conductor 102b disposed in parallel to each other on a front side of the substrate 101. The first signal conductor 102a and the ground conductor layer 105 compose a first transmission line, whereas the second signal conductor 102b and the ground conductor layer 105 compose a second transmission line. The first transmission line and the second transmission line compose a differential transmission line 102c. The differential transmission line 102c includes a curved region 104a, with a straight region 104b being connected to each end of the curved region 104a.

Abstract: A nonreciprocal circuit device includes permanent magnets, a ferrite core to which a DC magnetic field is applied from the permanent magnets, center electrodes disposed on the ferrite core, a circuit substrate, a magnetic yoke, and an electromagnetic shield plate. The ferrite core and the permanent magnets are longitudinally disposed on the circuit substrate, and the yoke has a ring-like shape so as to surround side surfaces of the ferrite core and the permanent magnets. The electromagnetic shield plate includes a dielectric substrate and a shield conductor made of a nonmagnetic metal conductive film on the dielectric substrate. The shield conductor includes opening areas having slits.

Abstract: A rotating data transmission device for computer tomographs, for transmission from a rotating part to a stationary part that is rotatably supported relative to the rotating part, comprises at least one dielectric waveguide assigned to the rotating part, at least one first line coupler for coupling electrical signals into the at least one dielectric waveguide, and at least one coupler assigned to the stationary part for tapping electrical signals from the at least one dielectric waveguide. The dielectric waveguide is divided into at least two segments of approximately the same length, signals are coupled into the segments of the dielectric waveguides through a first line coupler to propagate in opposite directions, and ends of the segments distant from the line coupler are provided with terminations.

Abstract: A balanced-to-unbalanced converter includes a transformer and a bias feeding circuit. The transformer has an unbalanced signal input/output (I/O) circuit and a balanced signal I/O circuit. The bias feeding circuit is electrically connected with the balanced signal I/O circuit of the transformer. The balanced-to-unbalanced converter equips with the bias feeding function, and thus the extra bias feeding circuit, which provides the operating power for the active component, is unnecessary in the system with the balanced-to-unbalanced converter.