Abstract: A semiconductor memory includes first to sixth ridges, an insulating layers on the first to sixth ridges, a first gate line above the first to fourth ridges, and a second gate line above the third to sixth ridges, wherein the first and sixth ridges, the insulating layers, and the first and second gate lines implement first and second capacitors, the second and third ridges and the first gate line implement first driver and load transistors, and the fourth and fifth ridges and the second gate lines implement second load and driver transistors.

Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: An improved semiconductor device is disclosed with a NMOS transistor formed on a P-Well in a deep N-well, a PMOS transistor formed on a N-Well in the deep N-well, a first voltage coupled to a source node of the PMOS, and a second voltage higher than the first voltage coupled to the N-well, wherein the second voltage expands a depletion region associated with the PMOS and NMOS transistor for absorbing electrons and holes caused by alien particles.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract: A split drain magnetic field effect transistor (MAGFET) includes at least one supplemental gate to exert a lateral electrical field in the channel of the MAGFET. Connection of the supplemental gate in feedback with one of the two drain contacts allows the MAGFET to act as a latch sensitive to the presence of an external magnetic field. Preferably, the MAGFET includes two laterally spaced supplemental gates, allowing for the detection of an external magnetic field and its orientation.

Abstract: Semiconductor devices containing a MOSFET and an on-chip current sensor in the form of a magnetic resistive element are described. The magnetic resistive element (MRE) is proximate the MOSFET in the semiconductor device. The current flowing through the MOSFET generates a magnetic field that is detected by the MRE. The MRE comprises a metal film that is placed proximate the MOSFET during the normal fabrication processes, thereby adding little to the manufacturing complexity or cost. Using the MRE adds an accurate, effective, and cheap method to measure currents in MOSFET devices.

Abstract: An attachment structure is used for attaching a solid-state imaging device to a light exit end face of a color-separating prism. When bonding the light exit end face on the color-separating prism side and the light entrance face on the solid-state imaging device side to each other, an adhesive is applied to a predetermined position between these faces outside a region through which a luminous flux incident on the imaging section of the solid-state imaging device passes.

Abstract: A method for embedding optical band gap (OBG) devices in a ceramic substrate (100). The method includes the step (320) of pre-forming an OBG structure (105). The OBG structure can be a micro optical electromechanical systems (MOEMS) device. Further, the OBG structure can be preformed from indium phosphide and/or indium gallium arsenide. The method also includes the step (325) of coating the OBG structure with a surface binding material (230). The surface binding material can be comprised of calcium and hexane. The ratio of the calcium to hexane can be from about 1% to 2%. At a next step (330), the OBG structure can be inserted into the ceramic substrate. A pre-fire step (335) and a sintering step (340) then can be performed on the substrate.

Abstract: An optical semiconductor package includes a substrate, a chip, a plurality of bonding wires, a window, a supporter, and an encapsulant. The chip is disposed on the substrate and has an optical element. The bonding wires are used for electrically connecting the chip to the substrate. The window is supported on the supporter and positioned over the optical element of the chip. The encapsulant is overmolded on the substrate for fixing the window and encapsulating the chip and the bonding wires.

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract: The present invention provides a low cost device that has a true die to external fiber optic connection. Specifically, the present invention relates to an optical device package joined to a semiconductor device package. In some cases, the combination is joined using wirebond studs and an adhesive material. In other cases, the combination is joined using an anisotropic conductive film. Yet, in other cases, the combination is joined using solder material. Each of these joining mechanisms provides high levels of thermal, electrical and optical performance. The joining mechanisms can apply to optical sub-assembly and chip sub-assembly interfaces in transceivers, transmitters, as well as receivers for opto-electronic packages.

Abstract: An optical integrated circuit having optical devices is fabricated. These optical devices must be biased in the mutually opposite directions. If such an optical integrated circuit is fabricated using a conductive semiconductor substrate as conventionally, it is not possible to drive the devices by a single power supply since the substrate side is shared as a common polarity by the devices. The present invention realizes a structure where both anode and cathode of each device can be isolated electrically by conventional process technology and provides an optical integrated circuit which can be driven by a single power supply. An optical integrated circuit is formed on a semi-insulative or insulative substrate. A high resistivity region which extends at least from the active layer to the substrate and includes part of an optical waveguide between the devices is formed so as to electrically isolate the anode and cathode of each integrated device from the other device.

Abstract: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.

Abstract: A band pass filter (114) is formed on an integrated circuit (IC) chip (102). Such band pass filter (114) may be used in a RF or wireless communication device, such as a mobile phone or a personal data assistant (PDA). The band pass filter (114) includes a transformer (202 and 204) made of a pair of metallic spirals formed on the IC chip. The metallic spirals may have substantially square or rectangular overall shape, and may be fabricated using copper. The metallic spirals may be co-planar and inter-wound or may be stacked, one on top of the other, and separated by a dielectric layer. The transformer (202 and 204) is capable of receiving an input signal, and providing high pass filtering to the input signal. The band pass filter (114) also includes a capacitor (226, 2; 230 and 232) that is capable of receiving the input signal and providing low pass filtering in conjunction with an inductance of the transformer (202 and 204).

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: An integrated capacitor on a packaging substrate. The integrated capacitor comprises a conductor plane, a first dielectric layer and a signal transmission layer. The conductor plane has an extrusion layer of a first thickness. The first extrusion layer and the conductor plane are made of the same material. The first dielectric layer is formed on the conductor plane. The signal transmission layer is formed on the first dielectric layer.

Abstract: An electrical resistor structure overlies a substrate and comprises a composite resistor having a first resistor of relatively low resistance and a second resistor of relatively high resistance overlying the first resistor. First and second electrodes make contact with the composite resistor at spaced locations, and a bond pad overlies the second resistor at a position between the electrodes. A metallized fiber is soldered a to a metal bond pad by providing a stacked resistor structure beneath the bond pad, disposing a solder preform over the bond pad, disposing the metallized fiber over the bond pad, and flowing a current through the stacked resistor structure. The stacked resistor structure, when subjected to a current flowing generally along a first axis, is characterized by a temperature profile that has first and second peaks on either side of the bond pad.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the microstructure of the substrate cause the bending of the substrate, in one or more propagation directions.

Abstract: A method used to form a semiconductor device comprises processing a semiconductor wafer to include one or more vias or through-holes only partially etched into the wafer, and scribe marks only partially etched into the wafer which define a plurality of semiconductor devices. Wafer material is removed from the back of the wafer to the level of the vias and scribe marks to form a via opening through the wafer while simultaneously dicing the wafer into individual semiconductor dice.

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The rare-earth oxide film having a [110] crystal lattice orientation. The substrate has a [001] crystal lattice orientation.

Abstract: A semiconductor device in which semiconductor chip(s) is or are mounted onto substrate(s) incorporating patterned wiring and the entirety or entireties has or have been sealed with resin(s), wherein by forming electrically conductive pattern(s) for shielding at end face(s) at top(s) of substrate(s) and attaching such electrically conductive pattern(s) to region(s) of ground plane pattern(s) on circuit board(s) of apparatus(es) which is or are provided with such semiconductor device(s), it is possible to shield semiconductor device(s) even without use of shield case(s). In such case, by applying material(s) possessing good shielding characteristics, e.g., gold plating, over electrically conductive pattern(s), it is possible to increase sensitivity with respect to electromagnetic noise and improve shielding effect (anti-electromagnetic-noise effect).

Abstract: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

Abstract: A radiation-emitting and/or radiation-receiving semiconductor component in which a radiation-emitting and/or radiation-receiving semiconductor chip is secured on a chip carrier part of a lead frame. The chip carrier part forms a trough in the region in which the semiconductor chip is secured wherein the inner surface of the trough is designed in such a way that it constitutes a reflector for the radiation emitted and/or received by the semiconductor chip.

Abstract: A semiconductor chip and a wiring strip are placed on a flat side of a base sheet. The semiconductor chip has parallel first and second surfaces. Electrodes are connected to the first surface. The electrodes all terminate in the plane of the flat side of the base sheet and adhesively connected to the flat side of the base sheet. The wiring strip has one end portion connected to the second surface of the semiconductor chip and the opposite end portion terminating in the plane of the flat side of the base sheet and adhesively connected to the flat side of the base sheet. A mold resin fills gaps between the semiconductor chip, the wiring strip, and the base sheet to lock the semiconductor chip and the wiring strip. The base sheet is removed.

Abstract: The invention relates to an injection moulded product comprising an attached body which has been attached by an intermediate layer. The body has been attached to the injection moulded product by an intermediate layer attached to the body prior to the injection moulding. The invention also relates to a method for the manufacture of an injection moulded product comprising a body which has been attached by an intermediate layer.

Abstract: The present invention relates to a thin film circuit board device having passive elements in wiring layers. The thin film circuit board device includes a base board (2) and a circuit part (3) including insulating layers (11) and (16) and pattern wiring (14) and (17) formed on a build-up forming surface (2a). On the first insulating layer (11), a receiving electrode part (21) is formed and the passive elements electrically connected to the receiving electrode part (21) are formed. In the circuit part (3), a substrate titanium film and a substrate film are laminated so as to cover the receiving electrode part (21) and the passive elements respectively. The substrate film and the substrate titanium film in areas in which a metallic film is not formed are etched through the metallic film serving as the first pattern wiring (14) formed on the substrate film as a mask. Thus, a substrate layer (23) and a substrate titanium layer (22) are formed.

Abstract: In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.

Abstract: A semiconductor package without bonding wires and a fabrication method are provided. The semiconductor package includes a substrate having a front surface and a back surface, two chips formed on the front surface, two dielectric layers formed on the chips respectively, two conductive trace layers formed on the dielectric layers respectively, an insulating layer formed on one of the dielectric layers, and a plurality of solder balls implanted on the back surface of the substrate. One of the dielectric layers is formed on one of the chips and attached to an entire non-active surface of the other of the chips.

Abstract: A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a layer in which power supply/ground wiring lines and wiring lines for supplying associated control signals to a memory cell unit and a control circuit are formed. The uppermost layer of the semiconductor device is comprised only of a plurality of pads 11 as an electrode for providing electrical connection with an external connection line for transmitting a signal to and from the semiconductor device, a plurality of contact holes 12 for providing electrical connection with lower wiring lines formed in a lower layer below the uppermost layer, and uppermost wiring lines 13 for connecting the plurality of pads 11 to the plurality of contact holes 12 correspondingly.

Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.

Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient ?upper of the upper part is defined by the Equation of ? upper = ? i = 1 n ? ? i × E i × v i ? i = 1 n ? E i × v i , where ?i is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g.

Abstract: A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.

Abstract: Semiconductor device structures include protective layers that are formed from healable or healed materials. The healable materials are configured to eliminate cracks and delamination, including singulation-induced cracks and delamination. The protective layers may be formed by applying a layer of protective material to surfaces of semiconductor device components that are carried by a fabrication substrate. The layer of protective material is then severed and the fabrication substrate is at least partially severed. Cracks and delaminated regions that are formed during severing are then healed. If a curable polymer is employed as the protective material, it may be partially cured before severing is effected, then self-healed before being fully cured. Alternatively, a thermoplastic material may be used as the protective material, with healing being effected by heating at least regions of the thermoplastic material.

Abstract: A semiconductor package wire bonding system and method of use are provided. The wire bonding system includes a heating block that heats and supports a printed circuit board on which a multi-layered semiconductor chip structure having an overhang is mounted. A support inserted through an opening in the printed circuit board supporting the overhang portion of the semiconductor chip structure is installed in a predetermined region of the heating block. Multiple supports on the heating block may support overhand portions on multiple semiconductor chip structures.

Abstract: A substrate is provided that may include an area designated for mounting of an integrated circuit and one or more areas for retaining a thermal interface material proximate the integrated circuit mounting area. A thermal interface material containment area(s) may be formed by creating a through-hole in the substrate, or a recess in the substrate that opens either to the die placement side or the opposite side of the substrate.

Abstract: A semiconductor device includes a semiconductor chip, a heat dissipation member for dissipating heat generated by the semiconductor chip, and a coupling member which thermally couples the semiconductor chip to the heat dissipation member, wherein the coupling member is made of metal and deformable to absorb a stress generated between the semiconductor chip and the heat dissipation member, the coupling member and the semiconductor chip being joined through metal-metal bonding.

Abstract: In order to prevent short-circuiting when a chip component is brazed to pads of a conductive wiring layer, a hybrid semiconductor circuit includes the chip component with terminal electrodes formed at both ends, a first conductive wiring layer on which the pads are provided such that they correspond to the terminal electrodes, and an overcoat resin that covers the first conductive wiring layer excluding the pads. The terminal electrodes of the chip component are adhered to the pads by a conductive adhesive and an insulating adhesive is provided between the pads.

Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.

Abstract: Surface-mountable semiconductor component having a semiconductor chip (1), at least two external electrical connections (31/314/41, 32/324/42), which are electrically conductively connected to at least two electrical contacts of the semiconductor chip (1), and an encapsulation material (50). The two external electrical connections are arranged at a film (2) having a thickness of less than or equal to 100 ?m. The semiconductor chip (1) is fixed at a first main surface (22) of the film (2) and the encapsulation material (50) is applied on the first surface (22).

Abstract: An integrated circuit (78) includes a memory circuit (10, 110, 210, 310, 410) having a group of bitlines (21–28, 121–128, 221–228, 321–328, 421–428), and having an array of memory cells (11–18) which are each electrically coupled to two bitlines of the group. Each bitline has alternating first (61, 63, 65) and second (62, 64, 66) portions that are respectively located in metalization layers disposed on opposite sides of an insulating layer (84). The first and second portions are electrically coupled by vias (51–54, 334, 437) which extend through the insulating layer. Along the length of each bitline, each first and second portion thereof is disposed in a metalization layer opposite from the metalization layer containing the adjacent portion of each adjacent bitline.

Abstract: In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.

Abstract: This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surfaces of the layer H2 plasma without any prior anneal prior to the deposition of the upper layer.

Abstract: Electronic packages with uninsulated portions of copper circuits protected with coating layers having thicknesses that are suitable for soldering without fluxing and are sufficiently frangible when being joined to another metal surface to obtain metal-to-metal contact between the surfaces.

Abstract: An electronic device has at least one semiconductor chip, which has mutually opposing contact sides, of which one first contact side is electroconductively surface-bonded via a first, solid soldering-agent layer to at least one first metallic conductor part. The semiconductor chip is electroconductively surface-bonded on its second contact side facing opposite the first contact side via a second soldering-agent layer to at least one second metallic conductor part. The softening temperature of the second soldering-agent layer is adapted to an operating temperature that occurs in this soldering-agent layer during operation of the device in such a way that the second soldering-agent layer is doughy or liquid at the operating temperature. The second soldering-agent layer is laterally bounded by a flow-off protection device.

Abstract: A package for a semiconductor die comprises a semiconductor die with a bond pad. The package further includes a package lead and a bond wire with a first end portion coupled to the package lead, a second end portion coupled to the bond pad, and an intermediate portion. A non-conductive intermediate lead finger mounting substrate with an intermediate lead finger is positioned within the package. The intermediate lead finger is positioned between the lead finger and the bond pad and is attached to the intermediate portion of the bond wire.