Abstract: A method for measuring and analyzing bioluminescence, including the steps of receiving in real-time a luminescence measurement result group from a creature sample group, displaying and maintaining in real-time the luminescence measurement result group, receiving in real-time another luminescence measurement result group from the creature sample group, and displaying and maintaining in real-time the another luminescence measurement result group, instead of the luminescence measurement result group.

Abstract: An image storage screen or panel, suitable for use in applications related with computed radiography, has been disclosed, wherein said screen or panel comprises a binderless needle-shaped stimulable (storage) phosphor and a substrate, characterized in that said substrate has a surface roughness of less than 2 ?m and a reflectivity of more than 80%.

Abstract: A radiation image storage panel has a phosphor layer formed by a gas phase-accumulation method, in which the phosphor layer is composed of a lower sub-layer of a spherical crystal structure and an upper sub-layer of a columnar crystal structure.

Abstract: A performance of a stimulable phosphor layer is enhanced by filling a filler in spacing of columnar crystals of a stimulable phosphor layer in a radiation image conversion panel having a stimulable phosphor layer in the form of columnar crystals formed by a vapor deposition method. According to the foregoing radiation image conversion panel, entire columnar crystals were able to be evenly surface-treated by penetrating the surface treatment agent into spacing of columnar crystals and by being treated for the surface of columnar crystals with the surface treatment agent in surface tension not more than 25 mN/m, and functions concerning properties such as the prevention of reflection and scattering of a stimulating light, water-repelling, oil-repelling, moisture resistance, antifouling and so forth can also be added.

Abstract: A patient alignment system for a radiation therapy system. The alignment system includes multiple external measurement devices which obtain position measurements of components of the radiation therapy system which are movable and/or are subject to flex or other positional variations. The alignment system employs the external measurements to provide corrective positioning feedback to more precisely register the patient and align them with a radiation beam. The alignment system can be provided as an integral part of a radiation therapy system or can be added as an upgrade to existing radiation therapy systems.

Abstract: A method for reducing particles during ion implantation is provided. The method involves the use of an improved Faraday flag including a beam plate having thereon a beam striking zone comprising a recessed trench pattern on which the ion beam scans to and fro. An ion beam selected from the mass analyzer is blocked by the Faraday flag in a closed position between the mass analyzer and the semiconductor wafer. A beam current of the ion beam impinging on the beam striking zone of the beam plate is measured. After the beam current measurement, the Faraday flag is removed such that the ion beam impinges on the semiconductor wafer.

Abstract: An apparatus for producing light includes a chamber that has a plasma discharge region and that contains an ionizable medium. The apparatus also includes a magnetic core that surrounds a portion of the plasma discharge region. The apparatus also includes a pulse power system for providing at least one pulse of energy to the magnetic core for delivering power to a plasma formed in the plasma discharge region. The plasma has a localized high intensity zone.

Abstract: The invention relates to a method and to an apparatus for the detection of objects moved on a segmented conveyor means by means of an optoelectronic sensor, in which in each case the geometric center of the objects is determined via the optoelectronic sensor, whereupon the objects are each associated with that conveyor segment in the region of which the respectively determined geometric center is located. The invention further relates to a method and to an apparatus for the determination of the dimensions of objects moved on a conveyor means by means of an optoelectronic sensor, in which the dimensions of the objects are detected and corresponding.

Abstract: A system and a method for detecting defects in a light-management film are provided. The system includes a first light source configured to emit light onto a first side of the film in a first predetermined region of the film. The system further includes a second light source configured to emit light onto a second side of the film in the first predetermined region of the film. The system further includes a first camera configured to receive a first portion of light reflected from the first predetermined region of film from the first light source and a second portion of the light propagating through the film from the second light source. Finally, the system includes a signal-processing device operably coupled to the first camera configured to detect a defect in the first predetermined region of the film based on at least one of the first and second portions of light.

Abstract: An apparatus and method for detecting a relatively narrow predetermined pattern, such as a trigger mark, on a moving printed product uses a plurality of sensor elements arranged linearly in an array and a switching apparatus for selecting a properly located subset of the sensor elements for detecting the predetermined pattern. During the operation of the apparatus, only those signals from sensors in the selected subset are checked continuously for the occurrence of a signal pattern corresponding to the predetermined pattern. Each time the predetermined signal pattern is found in the output signal from a sensor within the selected subset, a detection signal is generated. The lateral shifting of the predetermined pattern over time may be monitored by the selected sensors, and the selection of the subset of sensors for the continuous evaluation may be changed in response to the lateral shifting.

Abstract: The present invention aims at attaining a liquid surface level detecting apparatus, which can be used in various detection targets and usage environments without selecting a detection target, can efficiently irradiate a light to a liquid surface level detecting unit and detect a variation in a light reception amount of a light receiving means at a high sensibility, and can be excellent in durability, easy to manufacture, and be actually used. By placing a light shielding means 14 so as not to directly irradiate the light from a light emitting means 12 to a light receiving means 13, the light from the light emitting means is scattered by an optically scattering means 16, and a part of that scattering light is radiated to an outside by the liquid surface level detecting unit on a light radiating means (an optically transmitting member) 11.

Abstract: A residual image signal, which represents a residual image remaining on a stimulable phosphor sheet having been subjected to an erasing operation, is acquired. A radiation image of an object is then recorded on the stimulable phosphor sheet, from which the residual image signal has been detected. A radiation image signal, which represents the radiation image of the object, is then acquired, the thus acquired radiation image signal containing a residual image signal, which represents the residual image. The residual image signal is subtracted from the radiation image signal, and a radiation image signal, which represents the radiation image of the object and which is free from the residual image signal, is acquired.

Abstract: This invention is about a window interface layer in a light-emitting diode which comprises an n-type GaAs substrate with an n-type ohmic electrode at the bottom side thereof; an n-type AlGaInP cladding layer formed atop the substrate; an undoped AlGaInP active layer formed atop the n-type cladding layer; a p-AlGaInP cladding layer formed atop the active layer; a p-type window layer made of GaP; a p-type ohmic electrode formed atop the p-type window layer; and a highly doped p-type interface layer made of GaxIn1-xP (0.6?x?0.9) and interposed between the p-type cladding layer and p-type window layer wherein the highly doped p-GaInP interface layer possesses a band gap which is higher than that of the active layer and, however, smaller than that of the p-type cladding layer, and wherein the lattice constant lies between GaAs and GaP.

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a layer of quantum dots disposed between adjacent layers of the device; and providing an auxiliary layer disposed in one of the adjacent layers, and spaced from the layer of quantum dots, the auxiliary layer being operative to communicate carriers with the layer of quantum dots.

Abstract: The present invention is generally directed to electroluminescent Ir(III) compounds, the substituted 2-phenylpyridines, phenylpyrimidines, and phenylquinolines that are used to make the Ir(III) compounds, and devices that are made with the Ir(III) compounds.

Abstract: Semiconductor nanocrystals surface-coordinated with a compound containing a photosensitive functional group, a photosensitive composition comprising semiconductor nanocrystals, and a method for forming semiconductor nanocrystal pattern by producing a film using the photosensitive semiconductor nanocrystals or the photosensitive composition, exposing the film to light and developing the exposed film, are provided. The semiconductor nanocrystal pattern exhibits luminescence characteristics comparable to the semiconductor nanocrystals before patterning and can be usefully applied to organic-inorganic hybrid electroluminescent devices.

Abstract: Systems and methodologies are provided for of enabling a polymer memory cell to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell. Short retention times can be obtained by programming the polymer memory cell via a low current or a low electrical field. Similarly, long retention times can be obtained by employing a high current or electrical field to program the polymer memory cell.

Abstract: An i-type amorphous silicon film and an anti-reflection film made of amorphous silicon nitride or the like are formed in this order on a main surface of an n-type single-crystalline silicon substrate. On a back surface of the n-type single-crystalline silicon substrate are provided a positive electrode and a negative electrode next to each other. The positive electrode includes an i-type amorphous silicon film, a p-type amorphous silicon film, a back electrode, and a collector electrode formed in this order on the back surface of the n-type single-crystalline silicon substrate. The negative electrode includes an i-type amorphous silicon film, an n-type amorphous silicon film, a back electrode, and a collector electrode formed in this order on the back surface of the n-type single-crystalline silicon substrate.

Abstract: The invention relates to an active matrix of thin-film transistors or TFTs for an optical sensor, comprising a matrix of transistors formed on a substrate comprising a gate, a drain and a source, a set of rows and a set of columns that are connected to the gates and to an electrode of the transistor, respectively, pixel electrodes and, according to the invention, a set of capacitive electrodes lying at the same level as the electrodes of the transistors so as to form, with the pixel electrodes, storage capacitors.

Abstract: In an active matrix organic light emitting diode (AMOLED) display panel having an improved OLED circuit layout in the TFT back panel, the AMOLED pixels in the AMOLED pixel array are arranged to have the TFT circuit portions of the AMOLED pixels in clustered regions so that each pulse of laser beam during laser annealing of the amorphous silicon film irradiates mostly TFT circuit portions, thus, allowing more efficient laser annealing process.

Abstract: A nitride semiconductor light emitting device includes at least a substrate, an active layer formed of a nitride semiconductor containing mainly In and Ga, a p-electrode and an n-electrode. At least one of the p-electrode and n-electrode is electrically separated into at least two regions.

Abstract: A thin film transistor includes a channel layer of a specific shape, a thermal gradient inducer body, a gate insulating film, a gate electrode and an interlayer insulating film, a source electrode and a drain electrode. The channel layer is formed on a substrate. The channel layer has a nucleation region and a crystal end. The thermal gradient inducer body partially circumscribes the channel layer. The gate insulating film is formed on the substrate, and the channel layer is at least partially covered with the gate insulating film. The gate electrode is formed on the gate insulating film. The interlayer insulating film is formed on the gate insulating film, and the gate electrode is at least partially covered with the interlayer insulating film. The source electrode and the drain electrode are formed on the interlayer insulating film, passed through the gate insulating film and the interlayer insulating film, and electrically connected to the channel layer.

Abstract: A semiconductor package comprising a base material, an FPC substrate bonded through the intervention of an adhesive or an adhesive sheet on the base material and a semiconductor chip mounted on the FPC substrate, the semiconductor chip being mounted on the FPC substrate by FC bonding, the base material being formed by a resin, the base material having a concave portion or hole, and the semiconductor chip being mounted on the FPC substrate inside the concave portion or hole of the base material.

Abstract: An LED includes a semiconductor region having an active layer sandwiched between two confining layers of opposite conductivity types for generating heat. A cathode is arranged centrally on one of the opposite major surfaces of the semiconductor region from which is emitted the light. Attached to the other major surface of the semiconductor region, via an ohmic contact layer, is a reflective metal layer for reflecting the light that has traversed the ohmic contact layer, back toward the semiconductor region. A transparent antidiffusion layer is interposed between the ohmic contact layer and the reflective layer in order to prevent the ohmic contact layer and the reflective layer from thermally diffusing from one into the other to the impairment of the reflectivity of the reflective layer.

Abstract: The present invention provides a semiconductor device embracing (a) a first semiconductor region defined by a first end surface, a second end surface opposing to the first end surface and a side boundary surface connecting the first and second end surfaces; (b) a second semiconductor region connected with the first semiconductor region at the second end surface; (c) a third semiconductor region connected with the first semiconductor region at the first end surface; and (d) a fourth semiconductor region having inner surface in contact with the side boundary surface and an impurity concentration lower than the first semiconductor region. The fourth semiconductor region surrounds the first semiconductor region, and is disposed between the second and third semiconductor regions. The first, second and fourth semiconductor regions are first conductivity-type, but the third semiconductor region is a second conductivity type.

Abstract: The invention relates to a semiconductor arrangement having a MOSFET structure and an active zener function. A n+-doped zone and a p+-doped zone are provided at the bottom of a trench for the purpose of forming zener diodes, the n+-doped zone being directly connected to the gate electrode.

Abstract: A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 ?m thick is inserted between a heavily-doped phosphorus layer 11 composing the drain of a vertical MOSFET and an n?-type drift layer. The heavily-doped arsenic layer functions as a barrier layer which prevents phosphorus from diffusing from the heavily-doped phosphorus layer into the n?-type drift layer. This is successful in maintaining spreading of the depletion layer during OFF time of the vertical MOSFET to thereby improve the OFF-stage breakdown voltage, and in maintaining the low ON-stage resistance.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: A method for manufacturing a transistor includes forming a semiconductor layer on a substrate, a first insulation film on the semiconductor layer, and a gate electrode on the first insulation film. The method also includes forming a source region, a channel region, and a drain region in the semiconductor layer and forming a second insulation film on the gate electrode. A source electrode and a drain electrode are formed on the second insulation film and are coupled to the source region and the drain region, respectively. The method further includes coupling the drain electrode to the gate electrode through a contact hole that is vertically above the channel region.

Abstract: An island-shaped floating conducting region is provided in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, or peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer. The floating conducting region has floating potential and blocks a depletion layer extending from the wire on the nitride film to the substrate. It is therefore possible to prevent leakage of a high frequency signal to the other side through the depletion layer extending from the wire on the substrate to the substrate in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer.

Abstract: A semiconductor device includes an underlying layer made of a group-III nitride containing at least Al and formed on a substrate, and a group of stacked semiconductor layers including a first semiconductor layer made of a group-III nitride, preferably GaN, a second semiconductor layer made of AlN and a third semiconductor layer made of a group-III nitride containing at least Al, preferably AlxGa1-xN where x?0.2. The semiconductor device suppresses the reduction in electron mobility resulting from lattice defects and crystal lattice randomness. This achieves a HEMT device having a sheet carrier density of not less than 1×1013/cm2 and an electron mobility of not less than 20000 cm2/V·s at a temperature of 15 K.

Abstract: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.

Abstract: An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.

Abstract: A solid-state imaging device is formed on a silicon substrate for providing a MOS type solid-state imaging device which has a device isolation structure and causes a small amount of leak current. The solid-state imaging device includes, for each pixel, an imaging region which includes a photodiode having a charge accumulation region of a first conductivity type, a transistor and a device isolation region whose depth is less than a depth of the charge accumulation region of the first conductivity type, at which an impurity density is at maximum.

Abstract: A production method for an image sensor which is provided with a plurality of sensor portions arranged on a semiconductor substrate and each having a first photodiode constituted by a first region of a first conductivity type and a second region of a second conductivity type different from the first conductivity type and a second photodiode constituted by the second region and a third region of the first conductivity type. The method includes the steps of: forming a second region of the second conductivity type on a first region defined in a semiconductor substrate by epitaxial growth; and forming a third region of the first conductivity type on the second region by epitaxial growth.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A metal film can be deposited in the trench according to a desired deposition thickness in order to seam close a narrow portion of the trench while form a dimple in a wide portion of the trench. The trench, after metal film deposition, exhibits a depression in wider trench portions relative to narrow trench portions. The depression can be utilized by placing one or more memory or selection layers in the depression, and a via can be formed over a portion of the trench to form an interconnect.

Abstract: A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and a collector region. The base region for the vertical bi-polar transistor serves as the source region for the vertical MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical MOS transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor. The base region for the vertical bi-polar transistor is coupled to a write data word line.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.

Abstract: A memory region including a capacitor element, a logic region including a logic circuit, and a boundary region located between the memory region and the logic region are provided on a silicon substrate. The memory region includes a plurality of memory transistors and memory transistor connection plugs. The boundary region includes a dummy contact plug in the same layer as the memory transistor connection plugs and logic transistor connection plugs. The upper face of the dummy contact plug is covered with a second insulating layer. An end portion of a capacitor layer and an upper electrode is located closer to an inner region of the memory region than the dummy contact plug is.

Abstract: Silicon-oxide-nitride-oxide-silicon (SONOS) devices and methods of manufacturing the same are provided. According to one aspect, a SONOS device includes a semiconductor substrate having a first surface, a second surface of lower elevation than the first surface, and a third surface perpendicular and between the first and second surfaces; a tunnel dielectric layer on the semiconductor substrate; a charge trapping layer in a form of a spacer on the tunnel dielectric layer on the third surface; a charge isolation layer on the tunnel dielectric layer, which covers the charge trapping layer; a gate that extends over a portion of the first surface, over a portion of the second surface, and is adjacent to a portion of the third surface of the semiconductor substrate on the charge isolation layer; a first impurity region formed below the first surface and near the gate; and a second impurity region formed below the second surface, opposite the first impurity region.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, that is fabricated in substantially the same process steps as a storage capacitor of the volatile memory region. The reduction of process steps allow mixed memory to be fabricated in a cost effective manner.

Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.

Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Abstract: The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second pair of source/drain regions arranged in a second direction intersecting the first direction with the channel region formed therebetween. The channel region and the gate electrode are common between a first memory cell transistor including the first pair of source/drain regions and a second memory cell transistor including the second pair of source/drain regions.

Abstract: A DMOS device is provided which is equipped with a floating gate having a first and second electrode in close proximity thereto. The floating gate is separated from one of the first and second electrodes by a thin layer of dielectric material whose dimensions and composition permit charge carriers to tunnel through the dielectric layer either to or from the floating gate. This tunneling phenomenon can be used to create a threshold voltage that may be adjusted to provide a precise current by placing a voltage between a programming electrode and the body/source and gate electrode of the device.