Abstract: Provided are a method for easily detecting phosphorylated peptides, namely, proteins, in samples derived from living organisms or the like, a method for selectively adsorbing the phosphorylated peptides, and compounds that are highly coordinated to the phosphorylated peptides and usable in the methods. The complex compound is represented by the formula: wherein X is a linker moiety, and Y is a labeling group. The compound (I) is highly coordinated to a phosphorylated peptide, and has a labeling group. Accordingly, with use of the compound (I), the phosphorylated peptide can be easily identified.

Abstract: A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one or more chips of a silicon substrate; forming a file containing the coordinates of each potential transient defect on the chip; converting the file into a CAD image layer capable of displaying such potential transient defects; and displaying such potential transient defects superimposed over a CAD image of the actual circuit to permit visual inspection of the compound CAD image and to permit optional action to be taken in view of such potential transient defects.

Abstract: A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irradiated with X-rays so that the proportions of three types of silicides with different compositions in the titanium silicide layer 104 are measured based on the intensity of hard X-rays emitted from oxygen in the silicon oxide film 102 and the intensity of hard X-rays emitted from titanium in the titanium silicide layer 104.

Abstract: The present invention discloses a control TFT structure (i.e. a driving TFT) for reducing leakage in an OLED display. A semiconductor layer, such as a polysilicon layer, is deposited on a transparent substrate as a channel region. A lightly doped region and a drain region are disposed on one side of the polysilicon layer and a source region is disposed on the opposite side of the polysilicon layer. An insulating layer is deposited covering the surface of the polysilicon layer, the lightly doped region, and the source/drain regions. Source and drain electrodes are disposed in the insulating layer, electrically connecting the source and drain region respectively. A gate metal layer is disposed on the insulating layer, at approximately the top right portion of the polysilicon layer to form a transistor structure.

Abstract: There are provided a light polarizing film of a grid type, usable for light at a wavelength in a range of a visible light region to an infrared region, a method of continuously fabricating the same, and a reflective optical film using the light polarizing film. A polypropylene film is passed through rolls 12, a first constant temperature cell 13, and rolls 12? to thereby undergo uniaxial drawing by 4-fold. Thereafter, an aluminum metal is vapor-deposited to a thickness of 100 nm in a vacuum deposition cell 14 to be subsequently passed through rolls 15, a second constant temperature cell 16, and rolls 15?, undergoing uniaxial drawing by 2-fold again while partially crystallizing the polypropylene film. At this point in time, the aluminum metal undergoes substantially uniform cracking in a direction orthogonal to a drawing direction. Thereafter, heat treatment is applied to the film in a third constant temperature cell 17, and the film is subsequently taken out by take-up rolls 18.

Abstract: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager array. In the resulting structure, the conserved sections absorb incident light. The patterned portions of conserved material provide additional light shielding for array pixels.

Abstract: Provided is a method of fabricating a laser diode including a lower Al-containing semiconductor material layer, a active layer, and an upper Al-containing semiconductor material layer. The method includes thermally cleaning the inside of a deposition reactor in which a substrate on which the lower Al-containing semiconductor material layer is stacked is loaded. During the thermal cleaning process, the inside of the deposition reactor is thermally treated at a predetermined temperature in an atmosphere of a gas mixture of AsH3 and H2 that is injected into the deposition reactor.

Abstract: The present invention relates to a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising: attaching a post wafer to a resonator wafer, forming a bottom post from the post wafer being attached to the resonator wafer, attaching the resonator wafer to a base wafer, wherein the bottom post fits into a post hole in the base wafer, forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and attaching a cap wafer on top of the base wafer. The present invention relates further to a gyroscope containing an integrated post with on or off-chip electronics.

Abstract: The present invention is directed to a structure comprised of alternating layers of metal and sacrificial material built up using standard CMOS processing techniques, a process for building such a structure, a process for fabricating devices from such a structure, and the devices fabricated from such a structure. In one embodiment, a first metal layer is carried by a substrate. A first sacrificial layer is carried by the first metal layer. A second metal layer is carried by the sacrificial layer. The second metal layer has a portion forming a micro-machined metal mesh. When the portion of the first sacrificial layer in the area of the micro-machined metal mesh is removed, the micro-machined metal mesh is released and suspended above the first metal layer a height determined by the thickness of the first sacrificial layer. The structure may be varied by providing a base layer of sacrificial material between the surface of the substrate and the first metal layer.

Abstract: A photodiode with a semiconductor intrinsic light absorption layer has at least one p-doped light absorption layer or an n-doped light absorption layer, and preferably both. The diode also has a cathode electrode and an anode electrode electrically coupled with the p-doped light absorption layer or the n-doped light absorption layer.

Abstract: A solid state image pickup element which can exponentially reduce the in-plane photoelectric conversion portion characteristic distribution created in forming color filters by a common photolithography technique and which, when color filters are formed by split exposure, can reduce image non-uniformity between exposure regions in a picked-up image, and a method of manufacturing the same. The method includes: applying negative type color resist for forming first color filters onto an entire surface of a given film; forming the first color filters by irradiation of given portions with exposure light and subsequent development; applying negative type color resist for forming second color filters onto the entire surface of the first color filters while covering the first color filters; and forming the second color filters by irradiating an area smaller than a region that is surrounded by the first color filters with exposure light and subsequent development.

Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.

Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.

Abstract: A process for producing a semiconductor component having a plastic housing in which at least one semiconductor chip is arranged includes providing a semiconductor wafer having semiconductor chips which are arranged in rows and columns and have active top surfaces and back surfaces, the active top surfaces being provided with contact surfaces. The semiconductor wafer are divided into individual semiconductor chips, which are mounted on a carrier plate that has a thermosensitive adhesive on its top surface, such that the active top surfaces of the individual semiconductor chips are placed onto the top surface of the carrier plate. A common carrier is produced from a plastic embedding compound on the carrier plate, with the semiconductor chips being embedded in the plastic embedding compound. The carrier plate is removed by heating the thermosensitive adhesive to a predetermined, defined temperature at which the thermosensitive adhesive loses its adhesive action.

Abstract: In a semiconductor device, in which an insulating layer is disposed on the main face of the silicon substrate, and the insulating layer includes the protruding portion that protrudes from the end face of the silicon substrate, the protruding portion has an interconnect of Cu embedded within the insulating layer.

Abstract: In an integrated circuit package, a method for insulation and reinforcement of individual bonding wires in an integrated circuit package. Using an airbrush, bonding wires are sprayed and coated with an insulating material prior to the molding process. Mold flow induced short rejects are eliminated as a result of: (a) Electrically insulating the bonding wires by coating them with an insulating mixture; (b) Physically isolating the bonding wires as a result of bead formation around individual bonding wires, with the insulating beads acting as contact barriers between the bonding wires; and (c) Enhancing the structural rigidity of the bonding wires as a result of the coating. Reinforcement and separation of bonding wires also reduces inductive coupling and/or crosstalk interference due to proximity of bonding wires.

Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

Abstract: A microelectronic package and a method of forming the same comprising a microelectronic device attached by an active surface to a substrate. A heat dissipation device having a base portion is positioned over a back surface of the microelectronic device and having at least one lip portion extending from the base portion which is attached to the substrate. An inlet extends through the heat dissipation device base portion and is positioned to be over the microelectronic device back surface. A thermal interface material is dispensed through the inlet and by capillary action is drawn between the microelectronic device back surface and the heat dissipation device base portion.

Abstract: A method of making a microelectronic package includes providing a lead frame having at least one bus element and a plurality of branches extending from the bus element, each branch including a terminal and an elongated lead extending between the bus element and the terminal. The method includes applying a carrier element to the lead frame to form a laminate with the branches adhering to a first surface of the carrier element, and severing the branches from the bus element, leaving the branches mechanically connected to one another by the carrier element so as to form an in-process unit. The method also includes assembling a microelectronic element with the in-process unit so that the microelectronic element overlies a second surface of the carrier element.

Abstract: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead frame with target dimple areas, creating dimples in the lead frame corresponding to the gate contact and source contacts, printing a conductive epoxy on the lead frame in the dimples, curing the lead frame and semiconductor die wafer together, and dicing the wafer to form the semiconductor device packages.

Abstract: A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

Abstract: On an insulating substrate, a first insulating buffer layer, a heat accumulating-light shielding layer having at least a silicon layer on the surface thereof, a second insulating buffer layer and a first silicon layer are laminated in the order recited from the bottom. The lamination structure of the heat accumulating-light shielding layer, second buffer layer and first silicon layer is patterned. A laser beam is applied the patterned first silicon layer to melt and crystallize the first silicon layer. A thin film transistor is formed by using the crystallized first silicon layer. A polysilicon thin film transistor of high performance and small leak current to be caused by light as well as a display device using such thin film transistors is provided.

Abstract: A thin film transistor substrate for a display device having a plurality of thin film transistors and pixel electrodes connected to the thin film transistors, said thin film transistor substrate includes: a plurality of pad electrodes in a non-display area of the display device for applying signals to the plurality of thin film transistors in a non-display area of the display device; a protective film covering the pad electrodes in the non-display area; and a slit in the protective film adjacent to at least one of the plurality of pad electrodes.

Abstract: A silicon layer interposed between the top silicon nitride layer (SiN) and a silicon germanium layer (SiGe) which in turn is over a thick oxide (BOX) is selectively etched to leave a stack with a width that sets the gate length. A sidewall insulating layer is formed on the SiGe layer leaving the sidewall of the Si layer exposed. Silicon is epitaxially grown from the exposed silicon sidewall to form in-situ-doped silicon source/drain regions. The nitride layer is removed using the source/drain regions as a boundary for an upper gate location. The source/drain regions are coated with a dielectric. The SiGe layer is removed to provide a lower gate location. Both the upper and lower gate locations are filled with metal to form upper and lower gates for the transistor.

Abstract: A fully depleted SOI MOSFET arrangement includes a buried oxide (BOX) layer with recesses in the BOX layer and a post extended upwardly between the recesses. A thin channel region is formed on the post and a gate over the channel. Deep source/drain region are adjacent to the channel region and extend into the recesses.

Abstract: An orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is increased, a distortion thereof is suppressed, and a TFT using such a crystalline semiconductor film is provided. At the time of formation of the amorphous semiconductor film (102) or after the formation thereof, a noble gas element, typically, argon is included in the film and crystallization is performed therefor. Thus, an orientation ratio of the semiconductor film (104) can be increased and a distortion present in the semiconductor film (104) after the crystallization is suppressed as compared with that present in the semiconductor film before the crystallization. Then, the noble gas element in the film is removed or reduced by laser light irradiation performed later.

Abstract: A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.

Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm in thickness are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI semiconductor devices can be efficiently manufactured by mesa isolation techniques. A method of forming a plurality of semiconductor devices is provided comprising a SOI structure. The SOI structure comprises a substrate, an insulating layer overlying the substrate, and a silicon layer overlying the insulating layer, wherein the silicon layer has a thickness less than 20 nm. The silicon layer is patterned to create at least two laterally spaced apart silicon layers. A semiconductor device is formed at each of the at least two laterally spaced apart silicon layers.

Abstract: A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over the tensilely strained gettering layer. Additionally, the donor wafer may possess a particle-confining region proximate the tensilely strained layer. The method also includes introducing particles into the donor wafer to a depth below the surface, and accumulating at least some particles within the tensilely strained gettering layer. Next, the method includes initiating a cleaving action so as to separate at least one of the material layers form the substrate. The tensilely strained gettering layer may accumulate particles and/or point defects and reduce the implantation dose and thermal budget required for cleaving.

Abstract: A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.

Abstract: A semiconductor device comprises a semiconductor substrate, and a capacitor provided above the semiconductor substrate, the capacitor comprises a lower electrode containing metal, a first dielectric film provided above the lower electrode and containing tantalum oxide or niobium oxide, a top surface of the first dielectric film including a projecting portion, an upper electrode provided above the projecting portion of the first dielectric film and containing metal, a second dielectric film provided between the lower electrode and the first dielectric film and having a lower permittivity than the first dielectric film, and a third dielectric film provided between the projecting portion of the first dielectric film and the upper electrode and having a lower permittivity than the first dielectric film.

Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.

Abstract: A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.

Abstract: A source line is formed by forming a source slot in a bulk insulation layer overlying a substrate to expose a portion of a substrate within the source slot, where the exposed portion of the substrate includes source regions of select gates associated with two or more columns of serially-connected floating-gate transistors formed on the substrate. A layer of epitaxial silicon is grown on the exposed portion so as to partially fill the source slot. A conductive layer is formed on the bulk insulation layer and on the layer of epitaxial silicon so as to substantially fill an unfilled portion of the source slot. The conductive layer is removed from a surface of the bulk insulation layer.

Abstract: A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.

Abstract: A method of fabricating a semiconductor device is provided, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a transistor channel area. The method includes forming a gate insulating layer on a semiconductor substrate, forming a channel ion area in the substrate, forming a gate electrode on the gate insulating layer, forming a sidewall insulating layer on the gate electrode, forming lightly doped regions in the substrate adjacent to the channel ion area and aligned with the gate electrode, forming a spacer insulating layer on the sidewall insulating layer, forming spacers on sidewalls of the gate electrode, and forming heavily doped regions in the substrate aligned with the spacer.

Abstract: Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a LDD implant is carried out to from LDD source and drain regions in the body region for the second transistor. After the LDD implant, main spacers are formed adjacent the off-set spacers of at least the second transistor. After forming the main spacers, a source/drain implant is carried out to form a highly doped region within each of the DDD drain and source regions and the LDD drain and source regions.

Abstract: A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5–25% germanium and 0–3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Abstract: A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device structure and to impart the material with a substantially planar surface and semiconductor device structures formed thereby. The thickness of the material covering the surface is less than the depth of the recesses. The surface may remain substantially uncovered by the material.

Abstract: An ultra thin MOSFET device structure located on an insulator layer, and a method of forming the ultra thin MOSFET device structure featuring a strained silicon channel located on the underlying insulator layer, has been developed. After epitaxial growth of a semiconductor alloy layer such as silicon-germanium (SiGe), on a first semiconductor substrate, a strained silicon channel layer, under biaxial tensile strain, is epitaxially grown on the underlying semiconductor alloy layer. Bonding of the strained silicon channel layer of the first semiconductor substrate, to a silicon oxide layer located on the surface of a second semiconductor substrate, is followed by a cleaving procedure performed at the interface of the strained silicon channel layer and the underlying semiconductor alloy layer, resulting in the desired configuration comprised of strained silicon channel layer-underlying insulator layer-second semiconductor substrate.

Abstract: A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs.

Abstract: A lift off process is used to separate a layer of material from a substrate by irradiating an interface between the layer of material and the substrate. According to one exemplary process, the layer is separated into a plurality of sections corresponding to dies on the substrate and a homogeneous beam spot is shaped to cover an integer number of the sections.

Abstract: A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.

Abstract: An oxide or nitride layer is provided on an amorphous semiconductor layer prior to performing metal-induced crystallization of the semiconductor layer. The oxide or nitride layer facilitates conversion of the amorphous material into large grain polycrystalline material. Hence, a native silicon dioxide layer provided on hydrogenated amorphous silicon (a-Si:H), followed by deposited Al permits induced crystallization at temperatures far below the solid phase crystallization temperature of a-Si. Solar cells and thin film transistors can be prepared using this method.