Abstract: A semiconductor thin film is manufactured by scanning laser light or a substrate onto an arbitrary region of the semiconductor thin film and irradiating a laser thereon. The semiconductor thin film is formed by the substantially belt-shaped crystal being crystallized such that crystalline grains grow in the scanning direction, on the substrate, on XY coordinates where value x of beam size W (?m) of the laser light measured in substantially the same direction as the scanning direction is defined as X axis, and where value y of scanning velocity Vs (m/s) is defined as Y axis, the crystallization processing is performed within a region where all of the following conditions hold: condition 1: the beam size W is larger than wavelength of the laser beam, condition 2: the scanning velocity Vs is smaller than upper-limit of crystal growth speed, and condition 3: x×(1/y)<25 ?s.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.

Abstract: A process for producing doped semiconductor wafers from silicon, which contain an electrically active dopant, such as boron, phosphorus, arsenic or antimony, optionally are additionally doped with germanium and have a defined thermal conductivity, involves producing a single crystal from silicon and processing further to form semiconductor wafers, the thermal conductivity being established by selecting a concentration of the electrically active dopant and optionally a concentration of germanium. Semiconductor wafers produced from silicon by the process have specific properties with regard to thermal conductivity and resistivity.

Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

Abstract: A photolithography and etch process sequence includes a photomask having a pattern with compensation features that alleviate patterning variations due to the proximity effect and depth of focus concerns during photolithography. The compensation features may be disposed near isolated or outermost lines of a device pattern. A photoresist pattern is formed to include the compensation features and the pattern etched to form a corresponding etched pattern including the compensation features. After etching, a protection material is formed over the layer and a trim mask is used to form a further photoresist pattern over the protection material. A subsequent etching pattern etches the protection material and removes the compensation features and results in the device lines being formed unaffected by proximity effects. Flare dummies may additionally be added to the mask pattern to increase pattern density and assist in endpoint detection.

Abstract: A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof.

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line.

Abstract: A method for fabricating semiconductor devices includes forming a protective layer on a metallic layer prior to forming a metallic silicide layer, the protective layer having a thickness greater than that of the metallic layer.

Abstract: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

Abstract: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive material is discharged locally and an electric conductor to function as a pillar is formed on a first pattern over a substrate, an insulator is formed to cover the electric conductor, the insulator is etched to expose a top surface of the electric conductor, and a second pattern is formed on the top surface of electric conductor that is exposed.

Abstract: A process for manufacturing a wiring substrate, comprising: a step of forming an insulating resin layer containing an inorganic filler over a wiring layer formed on at least one surface of an insulating substrate; a step of forming a thin copper film layer by roughening a surface of the insulating resin layer and plating the same electrolessly with copper; a step of forming an insulating film over the thin copper film layer; a step of forming plated resists profiling a pattern by exposing and developing the insulating film with the pattern; and a step of forming wiring pattern layers by an electrolytic copper plating on a surface of the insulating resin layer having the plated resists formed thereon, wherein at least one of the plated resists has a width of less than 20 ?m, and the plated resists include adjoining plated resists in which a clearance between said adjoining plated resists has a width of less than 20 ?m.

Abstract: A method for forming a metallic interconnect in a semiconductor device is disclosed. An example method forms an IDL on a substrate including predetermined devices, forms a via hole in the IDL, depositing a first metal diffusion preventive layer and a metal layer to form a via plug on the IDL, and performs a planarization process using the first metal diffusion preventive layer using as an etching stop layer. In addition, the example method forms a metallic interconnect on the first metal diffusion preventive layer, deposits the other metal diffusion preventive layer on the metallic interconnect, and etches a predetermined part of first and second metal diffusion preventive layers and the metallic interconnect using a mask pattern.

Abstract: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

Abstract: In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.

Abstract: There is provided a substrate processing method which, even when a material having a low mechanical strength is employed as an interlayer dielectric, can produce a semiconductor device having a multi-layer interconnect structure of fine interconnects in higher yield. A substrate processing method according to the present invention includes steps of: providing a substrate having interconnect recesses formed in a surface; forming a metal film on the surface of the substrate by plating to embed the metal film in the interconnect recesses; removing the metal film formed in an ineffective region of the substrate and an extra metal film formed in an effective region of the substrate; and flattening the surface of the substrate after removal of the metal film by performing chemical-mechanical polishing.

Abstract: A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type opening. To obtain the maximum adhesion benefit the tantalum nitride layer is formed via an atomic deposition layer procedure, performed at specific deposition conditions. The adhesion between the underlying copper structure and overlying materials such as a silicon nitride etch stop layer, as well the adhesion between the lower level copper structure and overlying upper level metal interconnect structures, is improved as a result of the presence of the atomic layer deposited tantalum nitride layer.

Abstract: A Local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern.

Abstract: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

Abstract: In the case that a stacked layer, in which another metal layer is stacked on an Al layer or Al alloy layer having a low resistance, is used as a wiring material, an etchant is provided which can etch to a substantially equal etching rate by executing only one etching on the each metal layer composing the stacked layer. A method of manufacturing a substrate for an electronic device uses the etchant, producing an electronic device having the substrate. In order to achieve the object, the etchant has fluoric acid, periodic acid and sulfuric acid wherein the total weight ratio of the fluoric acid and periodic acid is 0.05˜30 wt %, the weight ratio of the sulfuric acid is 0.05˜20 wt %, the weight ratio of periodic acid to fluoric acid is 0.01˜2 wt %. Also each layer of wiring (5, 12, 14) formed by stacking Al layer or Al alloy layer and Ti layer or Ti alloy layer can be uniformly etched to substantially equal etching rate by the etchant.

Abstract: Methods are provided for treating germanium surfaces in preparation for subsequent deposition, particularly gate dielectric deposition by atomic layer deposition (ALD). Prior to depositing, the germanium surface is treated with plasma products or thermally reacted with vapor reactants. Examples of surface treatments leave oxygen bridges, nitrogen bridges, —OH, —NH and/or —NH2 terminations that more readily adsorb ALD reactants. The surface treatments avoid deep penetration of the reactants into the germanium bulk but improve nucleation.

Abstract: A barrier limits the diffusion of a metal, such as copper, into an insulating layer. The barrier may take the form of insulating layer made of a silicon carbide type material which has been exposed to ionised hydrogen subsequent to deposition. Preferably the material contains nitrogen and it is particularly preferred that the material has a dielectric constant of 3.5 or less.

Abstract: A method of producing a semiconductor device according to an aspect of the present invention comprises forming a seed film of Cu on a substrate; polycrystallizing the seed film formed on the substrate; and forming a plated film of Cu on the polycrystallized seed film by electrolytic plating.

Abstract: A system and a method to remove a layer of high-k dielectric material during the manufacturing of an integrated circuit. In one embodiment of the invention, an etch reactant is employed to form volatile etch products when reacted with high-k layers. Alternately, high-k layers can be anisotropically etched of in accordance with a patterned photoresist or hard mask, where a hyperthermal beam of neutral atoms is used to aid in the reaction of an etch reactant with a high-k layer. Alternately, a hyperthermal beam of neutral atoms or a plasma treatment can used to modify a high-k layer, and subsequently etch the modified high-k layer utilizing an etch reactant that reacts with the modified high-k layer. In still another embodiment of the invention, the hyperthermal beam of neutral atoms is used to etch a high-k layer through physical bombardment of the high-k layer.

Abstract: A method of forming floating gates for flash memory devices. A plurality of substrates is provided, in which a film to be etched and an overlying masking pattern layer are provided overlying each substrate. Each of the films in a plasma chamber is etched in sequence using the masking pattern layer as an etch mask, a polymer layer being deposited over the inner wall of the plasma chamber during the etching. An intermediary cleaning process is performed in the plasma chamber between the etchings before the deposited polymer layer reaches such a degree as to induce lateral etching on the next film to be etched, thereby improving etching profile of the films.

Abstract: A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.

Abstract: A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

Abstract: Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the nanorod array. The contacts may allow I/V (current/voltage) characteristics of the nanorods to be measured.

Abstract: A method of forming a micro pattern in a semiconductor device, wherein a first polysilicon film, a buffer oxide film, a second polysilicon film, an anti-polishing film, and a first oxide film are sequentially laminated on a semiconductor substrate having a to-be-etched layer. The first oxide film, the anti-polishing film and the second polysilicon film are patterned. After nitride film spacers are formed on the patterned lateral portions, a second oxide film is formed on the entire structure. A Chemical Mechanical Polishing (CMP) process is performed using the anti-polishing film as a stopper. Thereafter, after the nitride film spacers are removed, the second oxide film and the second polysilicon film are removed using a difference in etch selective ratio between the oxide film and the polysilicon film. A hard mask for forming a micro pattern having a structure in which the first polysilicon film and the buffer oxide film are laminated is formed.

Abstract: The present invention discloses a technique of removing a substance from a substrate surface, such as stripping photoresist from a wafer, or forming a substance on a substrate surface. Substrates to be treated are parallel arranged at an equal interval and are immersed in a liquid with only a lower portion thereof being below the liquid surface. Gas such as ozone is introduced into the liquid and is continuously bubbling below the substrates. The bubbles will ascend between two adjacent substrates and climb on the surfaces of the substrates before they burst. The liquid boundary layers on the substrate surfaces are compressed and refreshed in the course of a dragging ascent of the bubbles, enhancing mass transfer between gas/liquid/solid substances across the liquid boundary layer, thereby resulting in a fast reaction and a fast treatment of the surface of the substrates.

Abstract: The present invention pertains to methods for removing unwanted material from a work piece. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer during semiconductor manufacturing. Methods involve implementing a hydrogen plasma operation with downstream mixing with an inert gas. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: A method of stripping an integrated circuit (IC) structure having a photoresist material and an organosilicate glass (OSG) material is described. The method comprises feeding a nitrous oxide (N2O) gas into a reactor, generating a plasma in the reactor and stripping the photoresist. The stripping process provides a high selectivity between the photoresist and the OSG material.

Abstract: A method of micro-machining a semiconductor substrate to form through slots therein and substrates made by the method. The method includes providing a dry etching chamber having a platen for holding a semiconductor substrate. During an etching cycle of a dry etch process for the semiconductor substrate, a source power is decreased, a chamber pressure is decreased from a first pressure to a second pressure, and a platen power is increased from a first power to a second power. Through slots in the substrate provided by the method can have a reentrant profile for fluid flow therethrough.

Abstract: This invention provides a method of forming at least one thin film device, such as for example a thin film transistor. The method includes providing a substrate and depositing a plurality of thin film device layers upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film layers and 3D template structure are etched and at least one thin film layer is undercut.

Abstract: Methods of forming a semiconductor device are provided by forming a gate pattern that includes a gate electrode on a substrate. Lightly doped impurity diffusion layers are formed in the substrate at both sides of the gate pattern. Spacers are formed on sidewalls of the gate pattern. The spacers having a bottom width. Impurity ions are implanted using the gate pattern and the spacer as a mask to form a heavily doped impurity diffusion layer in the substrate. The spacers are removed. A conformal etch stop layer is formed on the gate pattern and the substrate. The etch stop layer is formed to a thickness of at least the bottom width of the spacers.

Abstract: Fabrication of a light emitting device includes etching of a substrate of the light emitting device. The etch may be an aqueous etch sufficient to increase an amount of light extracted through the substrate. The etch may be a direct aqueous etch of a silicon carbide substrate. The etch may remove damage from the substrate that results from other processing of the substrate, such as damage from sawing the substrate. The etch may remove an amorphous region of silicon carbide in the substrate.

Abstract: The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.

Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.

Abstract: The present invention relates to a semiconductor device fabrication method, which includes forming an inter metal dielectric on a semiconductor substrate having wirings and planarizing the inter metal dielectric through a chemical mechanical polishing, wherein the inter metal dielectric is formed by carrying out at least one cycle of depositing polycrystalline silicon, plasma-processing the polycrystalline silicon, and oxidizing the polycrystalline silicon.

Abstract: An method employing atomic layer deposition (ALD) and rapid vapor deposition (RVD) techniques conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant and a high degree of surface smoothness. The method includes the following three principal operations: exposing a substrate surface to an aluminum-containing precursor gas to form a saturated layer of aluminum-containing precursor on the substrate surface; exposing the substrate surface to an oxygen-containing gas to oxidize the layer of aluminum-containing precursor; and exposing the substrate surface to a silicon-containing precursor gas to form the dielectric film. Generally an inert gas purge is employed between the introduction of reactant gases to remove byproducts and unused reactants. These operations can be repeated to deposit multiple layers of dielectric material until a desired dielectric thickness is achieved.

Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

Abstract: A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%–15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.

Abstract: A lead- and barium-free crystal glass having a refractive index of at least 1.55, with in % by weight, more than 50% and less than 60% SiO2, more than 0.6% and less than 4% B2O3, less than 3% K2O, more than 12% and less than 15% Na2O, more than 4% and less than 11% CaO, more than 0.25% and less than 5% Al2O3, less than 2% MgO, and between 8 and 16% ZnO, with the proviso that the total content of the oxides of Pb, Ba and As is below 0.1%, the total content of the oxides of Ti and La is below 5% and the total content of the oxides of Nb, Ta, Yb, Y, W, Bi and Zr is below 5%, wherein at most 1% oxides of Nb, Ta and Yb respectively and 3% of the oxides of Y, W, Bi and Zr respectively are included.

Abstract: A catalyst, a process for using the catalyst whereby the catalyst effectively transalkylates C7, C9, and C10 aromatics to C8 aromatics are disclosed. The catalyst comprises a support such as mordenite plus a metal component. The catalyst provides an enhanced life and activity for carrying out the transalkylation reactions at relatively low temperatures. This is achieved by reducing the maximum particle diameter of cylindrical pellets to 1/32 inch (0.08 cm) or a trilobe to 1/16 inch (0.16 cm).

Abstract: A supported catalyst system for polymerizing olefins comprising a) a support, b) a Lewis base of the formula M3R6R7R8 ??(I) wherein M3 is an element of main group III of the Periodic Table of the Elements, c) an organometallic compound of the formula II as cocatalyst, M3R6R7R8 ??(II) wherein M3 is an element of main group III of the Periodic Table of the Elements, d) at least one metallocene, e) an organometallic compound of the formula [M4R9j]kIII where M4 is an element of main groups I, II or III of the Periodic Table of the Elements, where the organometallic compound of the formula II is covalently bound to the support.

Abstract: It has been discovered that using n-butylmethyldimethoxysilane (BMDS) as an external electron donor for Ziegler-Natta catalysts can provide a catalyst system that may prepare polypropylene films with improved properties. The catalyst systems of the invention provide for controlled chain defects/defect distribution and thus a regulated microtacticity. Consequently, the curve of storage modulus (G?) v. temperature is shifted such that the film achieves the same storage modulus at a lower temperature enabling faster throughput of polypropylene film through a high-speed tenter.

Abstract: The alkylhalosilanes are directly synthesized by reacting an alkyl halide with silicon in the presence of a catalytically effective amount of (?) a copper metal or a copper-based compound catalyst and (?) a catalyst promoter intermixture therefor which comprises an effective minor amount of an additive ?1 selected from the group consisting of tin, a tin-based compound and mixture thereof, an effective minor amount of an additive ?2 selected from the group consisting of cesium, potassium and rubidium, and compound and mixture thereof, and an effective minor amount of an additive ?3 selected from the group consisting of the element phosphorus, a phosphorus-based compound and mixture thereof.

Abstract: A process for the carbonylation of an ethylenically unsaturated compound with carbon monoxide and a co-reactant. The carbonylation reaction is carried out in the presence of a novel catalyst involving: a) a source of a group VIII metal; b)a bidentate diphosphine of formula I, wherein R1 represents a bivalent radical that together with the phosphorus atom to which it is attached is an optionally substituted 2-phospha-tricyclo[3.3.1.1{3,7}]- decyl group or a derivative thereof in which one or more of the carbon atoms are replaced by heteroatoms (“2-PA” group); wherein R2 and R3 independently represent univalent radicals of up to 20 atoms or jointly form a bivalent radical of up to 20 atoms; and wherein A1 and A2 independently represent optionally substituted alkylene groups and R represents an optionally substituted aromatic group; and, c) a source of anions.