Patents Issued in April 10, 2007
  • Patent number: 7202546
    Abstract: An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as power, ground, and clock signals throughout the die of the device. The distribution layer overlies the copper interconnection layer in a grid pattern which connects to the copper interconnection layer through a plurality of vias. The distribution layer further includes a plurality of wire bond pads to permit wire bonding between the distribution layer and bonding pads of the integrated circuit package.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: April 10, 2007
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Salvador Salcido, Jr., Michael G. Kelly, Michael D. Cusack, Ravindhar K. Kaw
  • Patent number: 7202547
    Abstract: A capacitor is formed that includes a self-organized monolayer of an organic compound between two electrodes.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: April 10, 2007
    Assignee: Infineon Technologies, AG
    Inventors: Hagen Klauk, Marcus Halik, Ute Zschieschang, Guenter Schmid, Franz Effenberger
  • Patent number: 7202548
    Abstract: An embedded capacitors with interdigitated structure for a package carrier or a printed circuit board comprises a plurality of stacked conductive layers, at least one first via connecting structure and at least one second via connecting structure. In order to enhance the capacitance and the layout efficiency, this case fully utilizes the spaces between the via connecting structures for disposing at least one extending line extended from the via connecting structure to simultaneously increase side-to-side and layer-to-layer capacitances. Thus, the present invention provides a capacitance larger than that of conventional design.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: April 10, 2007
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7202549
    Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: April 10, 2007
    Assignee: Ricoh Company, Ltd.
    Inventors: Yasunori Hashimoto, Kimihiko Yamashita
  • Patent number: 7202550
    Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
  • Patent number: 7202551
    Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7202552
    Abstract: A MEMS package and a method for its forming are described. The MEMS package has at least one MEMS device located on a flexible substrate. A metal structure surrounds the at least one MEMS device wherein a bottom surface of the metal structure is attached to the flexible substrate and wherein a portion of the flexible substrate is folded over a top surface of the metal structure and attached to the top surface of the metal structure thereby forming the MEMS package.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: April 10, 2007
    Assignee: Silicon Matrix Pte. Ltd.
    Inventors: Wang Zhe, Miao Yubo
  • Patent number: 7202553
    Abstract: A method for forming device packages includes forming a perimeter with a reactive foil and a bonding material interposed between a first wafer and a second wafer, pressing the first and the second wafers against the reactive foil and the bonding material, initiating the reactive foil, wherein the reactive foil heats the bonding material to create a bond between the first and the second wafers, and singulating the first and the second wafers into the device packages.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: April 10, 2007
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Tanya Jegeris Snyder, Robert H. Yi, Robert Edward Wilson
  • Patent number: 7202554
    Abstract: A semiconductor package comprising paddle and a plurality of leads which extend at least partially about the die paddle in spaced relation thereto. Attached to the die paddle is a semiconductor die which is electrically connected to at least some of the leads. Attached to the semiconductor die is at least one inner package. A package body encapsulates the die paddle, the leads, the semiconductor die and the inner package such that a portion of each of the leads and a portion of the inner package are exposed in the package body.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: April 10, 2007
    Assignee: Amkor Technology, Inc.
    Inventors: Do Hyung Kim, Hyung Il Jeon, Doo Hyun Park
  • Patent number: 7202555
    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a bailout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: April 10, 2007
    Assignee: Staktek Group L.P.
    Inventors: David L. Roper, James W. Cady, James Wilder, James Douglas Wehrly, Jr., Jeff Buchle, Julian Dowden
  • Patent number: 7202556
    Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: April 10, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Victor Tan Cher 'Khng, Lee Kian Chai
  • Patent number: 7202557
    Abstract: A copackaged electronic device comprises a diode device having an anode coupled to a drain electrode of a switching device and a cathode capable of being coupled to an external circuit. The switching device may be controlled by an integrated circuit mounted on a source electrode of the switching device and electrically connected such that the integrated circuit is capable of controlling switching of the switching device. For example, the device is used in a power factor correction circuit. The diode device comprises at least one inverted diode having a solderable anode and a wire-bondable cathode.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: April 10, 2007
    Assignee: International Rectifier Corporation
    Inventors: Stephen Oliver, Hugh D Richard
  • Patent number: 7202558
    Abstract: A package base for a semiconductor element is made of a carbon composite material. The mounting surface of the package base includes a first area on which at least one first element including at least one semiconductor element is to be mounted, and a second area on which at least one second element including at least a terminal for electrode wiring is to be mounted. Preferably, the carbon composite material is a high-density, isotropic carbon-fiber composite material. In addition, the mounting surface may have a step change in surface elevation for alignment of either of the at least one first element and the at least one second element.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: April 10, 2007
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Teruhiko Kuramachi
  • Patent number: 7202559
    Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a substantially planar first surface of a stiffener. The first surface of a substrate is attached to a substantially planar second surface of the stiffener. The second surface of the stiffener is opposed to the first surface of the stiffener. A centrally located protruding portion on the second surface of the stiffener is opposed to the centrally located cavity. The protruding portion extends through an opening in the substrate. A wire bond is coupled from a bond pad of the IC die to a contact pad on the first surface of the substrate through a through-pattern in the stiffener. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, a notch in an edge of the recessed portion, and a notch in an edge of the opening.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: April 10, 2007
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 7202560
    Abstract: A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active device circuit on its first surface. The seal ring is adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component. An external contact is provided on the wafer package. The external contact is accessible externally to the wafer package and is electrically coupled to the active device circuit of the active device wafer.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: April 10, 2007
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Thomas E. Dungan, Ronald S. Fazzio
  • Patent number: 7202561
    Abstract: A semiconductor package in which heat is easily dissipated and a semiconductor chip is not damaged during a molding process, and a method of manufacturing the same. The semiconductor package with a heat dissipating structure includes a substrate, a semiconductor chip, which is mounted on the substrate and electrically connected with the substrate by bonding means, a heat slug which is adhered to the semiconductor chip and formed of a thermally conductive material, and a heat spreader partially exposed to the outside of the semiconductor package, and which is formed on the heat slug to be spaced a buffer gap apart from the heat slug.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong-Woo Seo
  • Patent number: 7202562
    Abstract: A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a semiconductor structure. The system includes a container to hold at least one semiconductor chip having surfaces to be in contact with a fluid. The system also includes a transducer and a heat exchanger disposed within the container and operably positioned with respect to each other to perform a thermoacoustic cooling process. In this system, the transducer is adapted to generate sound waves within the fluid such that compression and decompression of the fluid provides a temperature gradient across the semiconductor chip to transfer heat from the semiconductor chip to the heat exchanger, and the heat exchanger is adapted to remove heat from the fluid in the container. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 10, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 7202563
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 7202564
    Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Son Nguyen, Sarah L. Lane, Jia Lee, Kensaku Ida, Darryl D. Restaino, Takeshi Nogami
  • Patent number: 7202565
    Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: April 10, 2007
    Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.
    Inventors: Masazumi Matsuura, Hiroshi Horibe, Susumu Matsumoto, Tsuyoshi Hamatani
  • Patent number: 7202566
    Abstract: An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the substrate, wherein the pattern feature comprises at least one electrical contact. The integrated circuit also includes a plurality of interconnect layers for distributing electrical power to the plurality of microelectronic devices. The interconnect layers include a plurality of conductive members associated with each interconnect layer, wherein the members of at least one subsequent interconnect layer straddle members of at least one adjacent interconnect layer. The integrated circuit device further includes a plurality of bond pads connected to at least one of the plurality of members of the interconnect layers.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 7202567
    Abstract: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: April 10, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Kuniko Kikuta, Makoto Nakayama
  • Patent number: 7202568
    Abstract: A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas including at least one common chemical element.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Krishna Seshan, M. Lawrence A. Dass, Geoffrey L. Bakker
  • Patent number: 7202569
    Abstract: A semiconductor device comprises a semiconductor element which is flip-chip bonded to a circuit substrate. The semiconductor element and the circuit substrate are flip-chip bonded using a sealing resin having flux function. The semiconductor element includes a solder bump formed on a first electrode pad through a first low melting point solder layer. The circuit substrate includes a second electrode pad corresponding to the first electrode pad, and a second low melting point solder layer is formed on the second electrode pad. The solder bump is bonded to the first and second electrode pads through the first and second low melting point solder layers.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Tomono
  • Patent number: 7202570
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 7202571
    Abstract: An electronic module includes a substrate, at least one surface mounted integrated circuit (IC) component and an underfill material. The substrate includes a plurality of electrically conductive traces, formed on at least one surface of the substrate, and the component is electrically coupled to at least one of the conductive traces. The underfill material is positioned between the component and the substrate and provides at least one pedestal that supports the component during encapsulation. The underfill material, when cured, maintains the integrity of the electrical connections between the component and the conductive traces.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: April 10, 2007
    Assignee: Delphi Technologies, Inc.
    Inventors: Brian D. Thompson, Charles I. Delheimer, Derek B. Workman, Jeenhuei S. Tsai, Matthew R. Walsh, Scott D. Brandenburg
  • Patent number: 7202572
    Abstract: A generator/motor system and a method for operating this generator/motor system with which the filter currents are reduced. The generator/motor system has, for this purpose, a rotational field machine (DM) and a pulse-controlled inverter and filter capacitors (C1, C2). The pulse-controlled inverter is formed by two identical pulse-controlled inverters (PWR1, PWR2) which each have half the rated power. During operation, depending on the necessary rotational speed switching over is performed between a star circuit in which only the first pulse-controlled inverter is operational, and a single phase circuit in which both pulse-controlled inverters are operational. In order to obtain a torque which is comparable to the prior art, even if only one of the two pulse-controlled inverters is used, the rotational field machine has approximately twice the number of stator turns.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: April 10, 2007
    Assignee: DaimlerChrysler AG
    Inventor: Roland Blümel
  • Patent number: 7202574
    Abstract: This invention discloses a device in a vehicle electrical system which determines the vehicle's operating conditions and facilitates the transfer of electrical energy between systems of electrical energy sources and their associated electrical loads based on the vehicle operating conditions. The device further determines the operating conditions of the systems of electrical energy sources and their associated electrical loads and facilitates the transfer of electrical energy between them in accordance with said operating conditions.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: April 10, 2007
    Assignee: C.E. Niehoff & Co.
    Inventors: Shadi Jabaji, Issam Jabaji
  • Patent number: 7202575
    Abstract: There is disclosed a semiconductor integrated circuit device capable of eliminating an influence of a power voltage drop generated in a circuit disposed in the semiconductor integrated circuit device to inhibit an operation defect or an operation speed decrease of the circuit. In a semiconductor integrated circuit device 10 including a power wiring 18 connected to a power supply (Vdd) via a power terminal 12, a ground wiring 20 connected to a ground (0 V) via a ground terminal 14, and a plurality of circuits 301 to 30f connected in parallel with one another between the power wiring 18 and the ground wiring 20, a negative power terminal 16 connected to a negative power supply (?Vdd) is disposed, and a current source 22 is disposed as a current generating section between the negative power terminal 16 and a node Gf on a ground wiring 20 side of the f-th circuit 30f disposed in a region most distant from the ground.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: April 10, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Nobuyuki Endo
  • Patent number: 7202576
    Abstract: One embodiment of the invention provides a UPS including a precharge circuit and a battery pack sensor electrically coupled to the precharge circuit. The sensor senses the presence of an extra battery pack. The precharge circuit includes: a first precharge contact; a capacitor having first and second leads, the first lead electrically coupled to the first contact; a second precharge contact electrically coupled to the second lead of the capacitor; a current limiting circuit having first and second leads, the first lead of the current limiting circuit electrically coupled to the first lead of the capacitor; and a third precharge contact electrically coupled to the second lead of the current limiting circuit. The UPS can further include an enclosure having a housing and a battery connector integral to the housing, the battery connector adapted to receive the first, second and third precharge contacts.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: April 10, 2007
    Assignee: American Power Conversion Corporation
    Inventors: Joseph Dechene, Michael Manganese, Namwook Paik, Andrew Chase, Michael Lysik
  • Patent number: 7202577
    Abstract: An actuator for an active suspension system includes an armature and a housing enclosing an interior. The interior has a volume that varies in response to movement of the armature. A wall of the housing forms a first aperture through which air passes in response to movement of the armature.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: April 10, 2007
    Assignee: Bose Corporation
    Inventors: James A. Parison, John J. Breen
  • Patent number: 7202578
    Abstract: An electromagnetic drive device comprises a drive part (10) arranged to be reciprocated in the stroke direction (H) and possessing a circular or oval cross section, said drive part having a permanent magnet arrangement magnetized athwart the stroke direction (H), such arrangement possessing at least one pair of oppositely magnetized magnet portions (11 through 14) arranged sequentially in the stroke direction and being arranged in the intermediate space of a yoke arrangement (16) with pole pieces (19 through 22) provided in the direction of magnetization on opposite sides of the drive part (10). The yoke arrangement (16) possesses two pairs of pole pieces (19 through 22) delimiting the intermediate space and which are joined together by two yoke regions (23 and 24) extending essentially in parallelism to the stroke direction (H). At least one of the yoke regions (23 and 24) is surrounded by a coil (25 and 26) able to conduct current for performing a stroke.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: April 10, 2007
    Assignee: Festo AG & Co.
    Inventors: Jürgen Gerhartz, Reinhard Schwenzer
  • Patent number: 7202579
    Abstract: A water-cooled stator bar clip for electrical generators and a method for applying a corrosion-resistant protective coating, preferably Sc, Ti, Cr, Zr, Nb, Mo, Hf, Ta, W, Ni, and Al, and their alloys or oxides to existing stator bar end fittings in order to significantly reduce the possibility of leaks through the brazed connections of the copper stator bar end connections. The coatings can be applied locally using various known physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”) or other direct coating techniques known in the art. For example, the coatings can be applied using ion plasma deposition, sputtering or wire arc techniques (all PVD processes) or by using electroplating, high velocity oxygen free (“HVOF”) deposition, DC arc or electroless plating. Preferably, the coatings are applied either to new stator bar clips or to existing clips in the field.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: April 10, 2007
    Assignee: General Electric Company
    Inventors: Young Jin Kim, Paul Joseph Martiniano, Reed Roeder Corderman, Scott Andrew Weaver, Alan Michael Iversen, James Rollins Maughan
  • Patent number: 7202580
    Abstract: A permanent magnet type motor comprising a rotor main body rotatably supported with respect to a stationary member, a rotor which is provided on an outer periphery face of the rotor main body and which is arranged such that S poles and N poles of a plurality of permanent magnets are provided alternately, a stator composed of a stator core arranged at the outer periphery side or inner periphery side of the rotor, the stator core having winding storage sections, and stator windings stored in the winding storage sections, a sensor fixed to the stationary member so as to be proximal to the permanent magnets, the sensor detecting a position of the permanent magnets, a detection target member having a detector for detecting a magnetic resistance change portion formed on the rotor main body, and a rotational position detecting magnetic sensor arranged at the stationary member.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiyuki Yokoyama, Masahiro Kuroda, Tadahiro Nakayama, Shinichi Kominato, Tomokazu Harada, Yoshinori Saito
  • Patent number: 7202581
    Abstract: A stator (1) is configured so that a plurality of power supply terminals (4) each having a tab (4a) of a planar protrusion are located on an end face of a stator core (2), the power supply side end of the winding (3) is connected to the power supply terminal (4), and a lead wire (7) with a flag type terminal (14) is connected to the power supply terminal (4), the lead wire being connected to the flag type terminal (14) in a direction intersecting a press-fitting direction into the tab (4a), the plurality of power supply terminals (4) are arranged at the same height from the end face of the stator core (2) and are inclined so that the faces of the tabs (4a) of the plurality of power supply terminals (4) are not arranged on the same plane.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: April 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Sasaki, Osaaki Morino, Akihiko Yamazaki, Yasutake Seki, Takakatsu Hatae
  • Patent number: 7202582
    Abstract: An electric machine includes a stator having a plurality of slots and a winding system having windings placed in the slots. The windings of the winding system are interconnected by at least one flexible circuit board which is constructed for attachment to a radial surface area of the stator and for connection to the windings.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 10, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rainer Eckert, Jürgen Pawellek
  • Patent number: 7202583
    Abstract: Provided is a motor, which can minimize friction caused during initial operation and smoothly discharge static electricity generated during operation by employing both an air dynamic bearing and a fluid dynamic bearing using oil of predetermined viscosity. Bearing means employed in the motor includes a fluid dynamic bearing generating a fluid dynamic pressure by forming an oil gap between a rotor and a stator such that oil is accommodated in the oil gap, and an air dynamic bearing generating an air dynamic pressure by forming an air gap between the rotor and the stator such that air is introduced into the air gap. Specifically, the fluid dynamic bearing generates a fluid dynamic pressure by forming an oil gap between an axial hole of a sleeve and a shaft such that oil is accommodated in the oil gap, and the air dynamic bearing generates an air dynamic pressure by forming an air gap between an inner circumferential surface of a hub and an outer circumferential surface of the sleeve.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: April 10, 2007
    Assignee: G & W Technologies, Inc.
    Inventor: Sang Uk Kim
  • Patent number: 7202584
    Abstract: A position-control stage system is disclosed, which may ensure much space to install the armature assembly on the bed, even with small in dimension. Correspondingly, the position-control stage system itself is made high in propulsion and efficient in operating performances including high-speed traveling, high response, high-precision position-control, and so on, even with compact or slim in construction. Armature windings to provide an armature assembly are made of three-phase coreless windings wound in annular flat configuration, and disposed on the bed radially outside of a rolling-contact bearing in a way closely adjacent to the bearing. Magnets to provide a field magnet array are each made in a segment, and disposed on the turntable in opposition to the armature windings in a way alternating in polarity circularly on a desired circular surface.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: April 10, 2007
    Assignee: Nippon Thompson Co. Ltd.
    Inventor: Eiji Ida
  • Patent number: 7202585
    Abstract: A brushless motor is capable of increasing output torque while suppressing an increase in iron loss. A plurality of magnets are magnetized in reverse radial orientation in such a manner that magnetic fields directed toward a stator converge toward the stator, and each of the magnets is provided at opposite ends of its outer peripheral surface with a pair of notched portions that are cut away to gradually approach in an axial direction as they proceed from an intermediate portion to the opposite ends.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: April 10, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Ohata, Masatsugu Nakano, Tetsunao Takaki
  • Patent number: 7202586
    Abstract: There is provided an electrical contact member where wear can be reduced. The electrical contact member is characterized by one or both of conductive metal particles and conductive metal fibers, at least outer circumferential surfaces of which have been modified with carbon nanofibers or carbon nanotubes, being disposed in a contact layer through which current flows.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: April 10, 2007
    Assignee: Shinano Kenshi Kabushiki Kaisha
    Inventor: Masashi Okubo
  • Patent number: 7202587
    Abstract: The present invention facilitates the placement of laminations 10 onto keybars 6 of stator generators frames 2. Laminations need to be tightly fit onto keybars 6, however, the same need for tightness makes stacking laminations onto keybars particularly onerous. This is magnified when donuts, which are preassembled groups of laminations, are attempted to be stacked onto the keybars 6. The present invention provides for enlarged grooves 12 that more easily accept the keybars. This makes stacking laminations, both individually and in donuts, much easier. The laminations are then held in position by the insertion of a wedge 16. The wedge may be placed to disperse forces 20 transferred to the laminations in a circumferential manner 22.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: April 10, 2007
    Assignee: Siemens Power Generation, Inc.
    Inventors: John Barry Sargeant, Alex Christodoulou
  • Patent number: 7202588
    Abstract: The present invention is including: a piezoelectric element actuator provided on a chassis frame and capable of generating a load along the chassis frame; and, a control unit that controls the load of the piezoelectric element actuator.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 10, 2007
    Assignee: Honda Motor Co., Ltd.
    Inventor: Hiroyuki Mae
  • Patent number: 7202589
    Abstract: A surface acoustic wave (SAW) sensor includes a transducer (240 provided on a substrate (23), wherein the transducer (24) is oriented on the substrate (23) so that the direction of acoustic wave propagation is such that the variation of sensor output with temperature, associated with the variation of the substrate third-elastic constants with temperature, substantially equal but opposite to the sum total of the variation of sensor output with temperature associated with the substrate linear temperature coefficient of expansion and with the variations with temperature of the substrate non-zero third order elastic constants, the substrate first-order elastic constants and the substrate density. The effect of temperature variation on sensor output is thereby minimized. This is achieved with a 35-degree arrangement or with reflective gratings inclined at an angle of 3.1 degrees to normal. Additionally, a robust package with a dish is given. Particular applications include the measurement of torque.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: April 10, 2007
    Assignee: Transense Technologies PLC
    Inventors: Victor Alexandrovich Kalinin, Mark Lee
  • Patent number: 7202590
    Abstract: A surface acoustic wave device includes: a piezoelectric substrate that has two or more resonators formed on a surface; and a supporting substrate that is joined to another surface of the piezoelectric substrate. In this surface acoustic wave device, at least two of the resonators have exciting portions that overlap each other in the direction of propagating surface acoustic waves, and at least a part of the piezoelectric substrate is removed or modified to have different properties between at least one pair of overlapping resonators among the resonators having the overlapping portions.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: April 10, 2007
    Assignees: Fujitsu Media Devices Limited, Fujitsu Limited
    Inventors: Takashi Matsuda, Michio Miura, Yoshio Satoh, Masanori Ueda
  • Patent number: 7202591
    Abstract: The present invention presents a system for a compound actuator. The system includes first and second electrode layers each including two electrode sections, an intermediate electrode layer between the first and second electrode layers, and first and second electrostrictive materials that change length in an applied electrical field. The first electrostrictive material is positioned between the first and intermediate electrode layers. The second electrostrictive material is positioned between the intermediate and second electrode layers. The first electrostrictive material has a first length adjoining the first electrode section and a second length adjoining the second electrode section. The second electrostrictive material has a third length adjoining the fourth electrode section and a fourth length adjoining the fifth electrode section.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: April 10, 2007
    Assignee: The Boeing Company
    Inventors: Darin J. Arbogast, Frederick T. Calkins, Dan J. Clingman
  • Patent number: 7202592
    Abstract: A piezoelectric transformer includes a piezoelectric ceramic disc having one face and the other face opposite to each other in a thickness direction. A pair of low-impedance portions acting as one of a driving portion and a generator portion are disposed in the piezoelectric ceramic disc symmetrically with respect to a central axis of the piezoelectric ceramic disc, while a pair of high-impedance portions acting as the other of the driving portion and the generator portion are disposed in the piezoelectric ceramic disc symmetrically with respect to the central axis so as to be electrically separated from the low-impedance portions such that the piezoelectric transformer is driven in a radial extensional vibration mode of the piezoelectric ceramic disc.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: April 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsu Takeda, Hiroshi Nakatsuka
  • Patent number: 7202593
    Abstract: A steel sheet for an inner magnetic shield has a ratio of the anhysteretic magnetic permeability in the rolling direction to the anhysteretic magnetic permeability in the transversal direction, which is not higher than 0.7 or not lower than 1.4, preferably not higher than 0.5 or not lower than 2.0. A higher value of the two anhysteretic magnetic permeability values in the rolling direction and in the transversal direction is not lower than 18000. The inner magnetic shield formed of the particular steel sheet has a substantially truncated pyramid body which has a pair of short side members of a screen and a pair of long side members of a screen. The short side members are joined to the long side members at edge portions of the truncated pyramidal inner magnetic shield. The direction, in which the anhysteretic magnetic permeability of the steel sheet is the higher value, corresponds to the horizontal plane direction of the short side member.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: April 10, 2007
    Assignee: JFE Steel Corporation
    Inventors: Hideki Matsuoka, Reiko Sugihara, Kenji Tahara, Noriko Kubo, Keisuke Fukumizu, Teruo Takeuchi, Hiroaki Kato
  • Patent number: 7202594
    Abstract: A display device which includes, a display panel, a red emitting fluorescent film, a green emitting fluorescent film, and a blue emitting fluorescent film, each of the fluorescent films being formed on an inner surface of the display panel. The red emitting fluorescent film contains red fluorescent particles having an average particle diameter ranging from 6 to 12 ?m and covered with red pigment having an average particle diameter ranging from 1/100 to 1/10 of the average particle diameter of the red fluorescent particles, the red emitting fluorescent particles are formed of Y2O2S:Eu, a concentration of Eu in the red emitting fluorescent film is 60 ppm or less, and the x-value of luminescent chromaticity of the red emitting fluorescent film is not less than 0.620.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Chigusa, Keisuke Iida, Hidemi Matsuda
  • Patent number: 7202595
    Abstract: A green phosphor for a plasma display panel has improved color purity, improved lifespan, and improved discharge stability. The green phosphor comprises a core including at least one first phosphor material selected from the group consisting of Zn2SiO4:Mn, (Zn,A)2SiO4:Mn (A is an alkaline earth metal), (Ba,Sr,Mg)O.?Al2O3:Mn (? is an integer in a range of 1 to 23), and MgAlxOy:Mn (x is an integer in the range of 1 to 10, and y is an integer in a range of 1 to 30), and a coating layer including a second phosphor which is present on the surface of the first phosphor, and which is at least one selected from the group consisting of LaMgAlxOy:Tb:Tb (x is an integer in the range of 1 to 14, and y is an integer in the range of 8 to 47), ReBO3:Tb (Re is a rare earth element selected from the group consisting of Sc, Y, La, (Ce, and Gd), and (Y, Gd)BO3:Tb.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: April 10, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Sung-Yong Lee
  • Patent number: 7202596
    Abstract: An electron emitter is formed by in situ growth from the vapor on catalyst clusters that are adhered by an adhesion layer to a conductive electrode. The emitter comprises hemispheroidal nanofiber clusters that emit electrons at low field strengths and high current densities, producing bright light by the interaction of the electrons and a fluorescent and/or phosphorescent film on an anode spaced across an evacuated gap. The nanofibers may be grown such that the nanofiber clusters are entangled, restricting movement of individual nanofibers.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: April 10, 2007
    Assignee: Electrovac AG
    Inventors: Xinhe Tang, Ernst Hammel